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23#ifndef __QE_H__
24#define __QE_H__
25
26#include "common.h"
27
28#define QE_NUM_OF_BRGS 16
29#define UCC_MAX_NUM 8
30
31#define QE_DATAONLY_BASE 0
32#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
33
34
35
36typedef enum qe_snum_state {
37 QE_SNUM_STATE_USED,
38 QE_SNUM_STATE_FREE
39} qe_snum_state_e;
40
41typedef struct qe_snum {
42 u8 num;
43 qe_snum_state_e state;
44} qe_snum_t;
45
46
47
48#define QE_RISC_ALLOCATION_RISC1 0x1
49#define QE_RISC_ALLOCATION_RISC2 0x2
50#define QE_RISC_ALLOCATION_RISC3 0x4
51#define QE_RISC_ALLOCATION_RISC4 0x8
52#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
53 QE_RISC_ALLOCATION_RISC2)
54#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
55 QE_RISC_ALLOCATION_RISC2 | \
56 QE_RISC_ALLOCATION_RISC3 | \
57 QE_RISC_ALLOCATION_RISC4)
58
59
60
61#define QE_CR_FLG 0x00010000
62#define QE_RESET 0x80000000
63#define QE_INIT_TX_RX 0x00000000
64#define QE_INIT_RX 0x00000001
65#define QE_INIT_TX 0x00000002
66#define QE_ENTER_HUNT_MODE 0x00000003
67#define QE_STOP_TX 0x00000004
68#define QE_GRACEFUL_STOP_TX 0x00000005
69#define QE_RESTART_TX 0x00000006
70#define QE_SWITCH_COMMAND 0x00000007
71#define QE_SET_GROUP_ADDRESS 0x00000008
72#define QE_INSERT_CELL 0x00000009
73#define QE_ATM_TRANSMIT 0x0000000a
74#define QE_CELL_POOL_GET 0x0000000b
75#define QE_CELL_POOL_PUT 0x0000000c
76#define QE_IMA_HOST_CMD 0x0000000d
77#define QE_ATM_MULTI_THREAD_INIT 0x00000011
78#define QE_ASSIGN_PAGE 0x00000012
79#define QE_START_FLOW_CONTROL 0x00000014
80#define QE_STOP_FLOW_CONTROL 0x00000015
81#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
82#define QE_GRACEFUL_STOP_RX 0x0000001a
83#define QE_RESTART_RX 0x0000001b
84
85
86
87#define QE_CR_SUBBLOCK_INVALID 0x00000000
88#define QE_CR_SUBBLOCK_USB 0x03200000
89#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
90#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
91#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
92#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
93#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
94#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
95#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
96#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
97#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
98#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
99#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
100#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
101#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
102#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
103#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
104#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
105#define QE_CR_SUBBLOCK_MCC1 0x03800000
106#define QE_CR_SUBBLOCK_MCC2 0x03a00000
107#define QE_CR_SUBBLOCK_MCC3 0x03000000
108#define QE_CR_SUBBLOCK_IDMA1 0x02800000
109#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
110#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
111#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
112#define QE_CR_SUBBLOCK_HPAC 0x01e00000
113#define QE_CR_SUBBLOCK_SPI1 0x01400000
114#define QE_CR_SUBBLOCK_SPI2 0x01600000
115#define QE_CR_SUBBLOCK_RAND 0x01c00000
116#define QE_CR_SUBBLOCK_TIMER 0x01e00000
117#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
118
119
120
121#define QE_CR_PROTOCOL_UNSPECIFIED 0x00
122#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
123#define QE_CR_PROTOCOL_ATM_POS 0x0A
124#define QE_CR_PROTOCOL_ETHERNET 0x0C
125#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
126#define QE_CR_PROTOCOL_SHIFT 6
127
128
129
130#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
131
132
133
134typedef enum comm_dir {
135 COMM_DIR_NONE = 0,
136 COMM_DIR_RX = 1,
137 COMM_DIR_TX = 2,
138 COMM_DIR_RX_AND_TX = 3
139} comm_dir_e;
140
141
142
143typedef enum qe_clock {
144 QE_CLK_NONE = 0,
145 QE_BRG1,
146 QE_BRG2,
147 QE_BRG3,
148 QE_BRG4,
149 QE_BRG5,
150 QE_BRG6,
151 QE_BRG7,
152 QE_BRG8,
153 QE_BRG9,
154 QE_BRG10,
155 QE_BRG11,
156 QE_BRG12,
157 QE_BRG13,
158 QE_BRG14,
159 QE_BRG15,
160 QE_BRG16,
161 QE_CLK1,
162 QE_CLK2,
163 QE_CLK3,
164 QE_CLK4,
165 QE_CLK5,
166 QE_CLK6,
167 QE_CLK7,
168 QE_CLK8,
169 QE_CLK9,
170 QE_CLK10,
171 QE_CLK11,
172 QE_CLK12,
173 QE_CLK13,
174 QE_CLK14,
175 QE_CLK15,
176 QE_CLK16,
177 QE_CLK17,
178 QE_CLK18,
179 QE_CLK19,
180 QE_CLK20,
181 QE_CLK21,
182 QE_CLK22,
183 QE_CLK23,
184 QE_CLK24,
185 QE_CLK_DUMMY
186} qe_clock_e;
187
188
189
190#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
191#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
192
193
194
195#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
196
197
198
199#define QE_BRGC_ENABLE 0x00010000
200#define QE_BRGC_DIVISOR_SHIFT 1
201#define QE_BRGC_DIVISOR_MAX 0xFFF
202#define QE_BRGC_DIV16 1
203
204
205
206#define QE_SDSR_BER1 0x02000000
207#define QE_SDSR_BER2 0x01000000
208
209#define QE_SDMR_GLB_1_MSK 0x80000000
210#define QE_SDMR_ADR_SEL 0x20000000
211#define QE_SDMR_BER1_MSK 0x02000000
212#define QE_SDMR_BER2_MSK 0x01000000
213#define QE_SDMR_EB1_MSK 0x00800000
214#define QE_SDMR_ER1_MSK 0x00080000
215#define QE_SDMR_ER2_MSK 0x00040000
216#define QE_SDMR_CEN_MASK 0x0000E000
217#define QE_SDMR_SBER_1 0x00000200
218#define QE_SDMR_SBER_2 0x00000200
219#define QE_SDMR_EB1_PR_MASK 0x000000C0
220#define QE_SDMR_ER1_PR 0x00000008
221
222#define QE_SDMR_CEN_SHIFT 13
223#define QE_SDMR_EB1_PR_SHIFT 6
224
225#define QE_SDTM_MSNUM_SHIFT 24
226
227#define QE_SDEBCR_BA_MASK 0x01FFFFFF
228
229
230#define QE_CP_CERCR_MEE 0x8000
231#define QE_CP_CERCR_IEE 0x4000
232#define QE_CP_CERCR_CIR 0x0800
233
234
235#define QE_IRAM_IADD_AIE 0x80000000
236#define QE_IRAM_IADD_BADDR 0x00080000
237#define QE_IRAM_READY 0x80000000
238
239
240
241
242
243struct qe_firmware {
244 struct qe_header {
245 u32 length;
246 u8 magic[3];
247 u8 version;
248 } header;
249 u8 id[62];
250 u8 split;
251 u8 count;
252 struct {
253 u16 model;
254 u8 major;
255 u8 minor;
256 } __attribute__ ((packed)) soc;
257 u8 padding[4];
258 u64 extended_modes;
259 u32 vtraps[8];
260 u8 reserved[4];
261 struct qe_microcode {
262 u8 id[32];
263 u32 traps[16];
264 u32 eccr;
265 u32 iram_offset;
266 u32 count;
267 u32 code_offset;
268 u8 major;
269 u8 minor;
270 u8 revision;
271 u8 padding;
272 u8 reserved[4];
273 } __attribute__ ((packed)) microcode[1];
274
275
276} __attribute__ ((packed));
277
278struct qe_firmware_info {
279 char id[64];
280 u32 vtraps[8];
281 u64 extended_modes;
282};
283
284void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
285void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
286uint qe_muram_alloc(uint size, uint align);
287void *qe_muram_addr(uint offset);
288int qe_get_snum(void);
289void qe_put_snum(u8 snum);
290void qe_init(uint qe_base);
291void qe_reset(void);
292void qe_assign_page(uint snum, uint para_ram_base);
293int qe_set_brg(uint brg, uint rate);
294int qe_set_mii_clk_src(int ucc_num);
295int qe_upload_firmware(const struct qe_firmware *firmware);
296struct qe_firmware_info *qe_get_firmware_info(void);
297void ft_qe_setup(void *blob);
298
299#endif
300