1/* 2 * (C) Copyright 2004-2008 3 * Texas Instruments, <www.ti.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23#ifndef _I2C_H_ 24#define _I2C_H_ 25 26#define I2C_DEFAULT_BASE I2C_BASE1 27 28#define I2C_REV (I2C_DEFAULT_BASE + 0x00) 29#define I2C_IE (I2C_DEFAULT_BASE + 0x04) 30#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) 31#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) 32#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) 33#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) 34#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) 35#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) 36#define I2C_CON (I2C_DEFAULT_BASE + 0x24) 37#define I2C_OA (I2C_DEFAULT_BASE + 0x28) 38#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) 39#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) 40#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) 41#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) 42#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) 43 44/* I2C masks */ 45 46/* I2C Interrupt Enable Register (I2C_IE): */ 47#define I2C_IE_GC_IE (1 << 5) 48#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ 49#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ 50#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ 51#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ 52#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ 53 54/* I2C Status Register (I2C_STAT): */ 55 56#define I2C_STAT_SBD (1 << 15) /* Single byte data */ 57#define I2C_STAT_BB (1 << 12) /* Bus busy */ 58#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 59#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 60#define I2C_STAT_AAS (1 << 9) /* Address as slave */ 61#define I2C_STAT_GC (1 << 5) 62#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 63#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 64#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ 65#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ 66#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ 67 68/* I2C Interrupt Code Register (I2C_INTCODE): */ 69 70#define I2C_INTCODE_MASK 7 71#define I2C_INTCODE_NONE 0 72#define I2C_INTCODE_AL 1 /* Arbitration lost */ 73#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ 74#define I2C_INTCODE_ARDY 3 /* Register access ready */ 75#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ 76#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ 77 78/* I2C Buffer Configuration Register (I2C_BUF): */ 79 80#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ 81#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ 82 83/* I2C Configuration Register (I2C_CON): */ 84 85#define I2C_CON_EN (1 << 15) /* I2C module enable */ 86#define I2C_CON_BE (1 << 14) /* Big endian mode */ 87#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ 88#define I2C_CON_MST (1 << 10) /* Master/slave mode */ 89#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ 90 /* (master mode only) */ 91#define I2C_CON_XA (1 << 8) /* Expand address */ 92#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ 93#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ 94 95/* I2C System Test Register (I2C_SYSTEST): */ 96 97#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 98#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ 99#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 100#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 101#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ 102#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ 103#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ 104#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ 105 106#define I2C_SCLL_SCLL 0 107#define I2C_SCLL_SCLL_M 0xFF 108#define I2C_SCLL_HSSCLL 8 109#define I2C_SCLH_HSSCLL_M 0xFF 110#define I2C_SCLH_SCLH 0 111#define I2C_SCLH_SCLH_M 0xFF 112#define I2C_SCLH_HSSCLH 8 113#define I2C_SCLH_HSSCLH_M 0xFF 114 115#define OMAP_I2C_STANDARD 100000 116#define OMAP_I2C_FAST_MODE 400000 117#define OMAP_I2C_HIGH_SPEED 3400000 118 119#define SYSTEM_CLOCK_12 12000000 120#define SYSTEM_CLOCK_13 13000000 121#define SYSTEM_CLOCK_192 19200000 122#define SYSTEM_CLOCK_96 96000000 123 124/* Use the reference value of 96MHz if not explicitly set by the board */ 125#ifndef I2C_IP_CLK 126#define I2C_IP_CLK SYSTEM_CLOCK_96 127#endif 128 129/* 130 * The reference minimum clock for high speed is 19.2MHz. 131 * The linux 2.6.30 kernel uses this value. 132 * The reference minimum clock for fast mode is 9.6MHz 133 * The reference minimum clock for standard mode is 4MHz 134 * In TRM, the value of 12MHz is used. 135 */ 136#ifndef I2C_INTERNAL_SAMPLING_CLK 137#define I2C_INTERNAL_SAMPLING_CLK 19200000 138#endif 139 140/* 141 * The equation for the low and high time is 142 * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed 143 * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed 144 * 145 * If the duty cycle is 50% 146 * 147 * tlow = scll + scll_trim = sampling clock / (2 * speed) 148 * thigh = sclh + sclh_trim = sampling clock / (2 * speed) 149 * 150 * In TRM 151 * scll_trim = 7 152 * sclh_trim = 5 153 * 154 * The linux 2.6.30 kernel uses 155 * scll_trim = 6 156 * sclh_trim = 6 157 * 158 * These are the trim values for standard and fast speed 159 */ 160#ifndef I2C_FASTSPEED_SCLL_TRIM 161#define I2C_FASTSPEED_SCLL_TRIM 6 162#endif 163#ifndef I2C_FASTSPEED_SCLH_TRIM 164#define I2C_FASTSPEED_SCLH_TRIM 6 165#endif 166 167/* These are the trim values for high speed */ 168#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM 169#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 170#endif 171#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM 172#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 173#endif 174#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM 175#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 176#endif 177#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM 178#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 179#endif 180 181#define I2C_PSC_MAX 0x0f 182#define I2C_PSC_MIN 0x00 183 184#endif /* _I2C_H_ */ 185