LXR uboot/include/asm-blackfin/mach-bf548/ADSP-EDN-BF544-extended

   1/* DO NOT EDIT THIS FILE
   2 * Automatically generated by generate-cdef-headers.xsl
   3 * DO NOT EDIT THIS FILE
   4 */
   5
   6#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
   7#define __BFIN_CDEF_ADSP_EDN_BF544_extended__
   8
   9#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
  10#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
  11#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
  12#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
  13#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
  14#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
  15#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
  16#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
  17#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
  18#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
  19#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
  20#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
  21#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
  22#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
  23#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
  24#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
  25#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
  26#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
  27#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
  28#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
  29#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
  30#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
  31#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
  32#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
  33#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
  34#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
  35#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
  36#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
  37#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
  38#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
  39#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
  40#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
  41#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
  42#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
  43#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
  44#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
  45#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
  46#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
  47#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
  48#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
  49#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
  50#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
  51#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
  52#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
  53#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
  54#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
  55#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
  56#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
  57#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
  58#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
  59#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
  60#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
  61#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
  62#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
  63#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
  64#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
  65#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
  66#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
  67#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
  68#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
  69#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
  70#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
  71#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
  72#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
  73#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
  74#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
  75#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
  76#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
  77#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
  78#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
  79#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
  80#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
  81#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
  82#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
  83#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
  84#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
  85#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
  86#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
  87#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
  88#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
  89#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
  90#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
  91#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
  92#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
  93#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
  94#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
  95#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
  96#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
  97#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
  98#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
  99#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 100#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 101#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
 102#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 103#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 104#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
 105#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 106#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 107#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
 108#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 109#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 110#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
 111#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 112#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 113#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
 114#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 115#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 116#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
 117#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 118#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 119#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
 120#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 121#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 122#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
 123#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 124#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 125#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
 126#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 127#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 128#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
 129#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 130#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 131#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
 132#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 133#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 134#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
 135#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 136#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 137#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
 138#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 139#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 140#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
 141#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 142#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 143#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
 144#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 145#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 146#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
 147#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 148#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 149#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
 150#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 151#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 152#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
 153#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 154#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 155#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
 156#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 157#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 158#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
 159#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 160#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 161#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
 162#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 163#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 164#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
 165#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 166#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 167#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
 168#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 169#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 170#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
 171#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 172#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 173#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
 174#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 175#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 176#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
 177#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 178#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 179#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
 180#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 181#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 182#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
 183#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 184#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 185#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
 186#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 187#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 188#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
 189#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 190#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 191#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
 192#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 193#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 194#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
 195#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 196#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 197#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
 198#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 199#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 200#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
 201#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 202#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 203#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
 204#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 205#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 206#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
 207#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 208#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 209#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
 210#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 211#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 212#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
 213#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 214#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 215#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
 216#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 217#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 218#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
 219#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 220#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 221#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
 222#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 223#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 224#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
 225#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 226#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 227#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
 228#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 229#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 230#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
 231#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 232#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 233#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
 234#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 235#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 236#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
 237#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 238#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 239#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
 240#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 241#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 242#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
 243#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 244#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 245#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
 246#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 247#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 248#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
 249#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 250#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 251#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
 252#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 253#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 254#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
 255#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 256#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 257#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
 258#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 259#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 260#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
 261#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 262#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 263#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
 264#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 265#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 266#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
 267#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 268#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 269#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
 270#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 271#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 272#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
 273#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 274#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 275#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
 276#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 277#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 278#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
 279#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 280#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 281#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
 282#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 283#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 284#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
 285#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 286#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 287#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
 288#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 289#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 290#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
 291#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 292#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 293#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
 294#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 295#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 296#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
 297#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 298#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 299#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
 300#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 301#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 302#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
 303#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 304#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 305#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
 306#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 307#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 308#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
 309#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 310#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 311#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
 312#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 313#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 314#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
 315#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 316#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 317#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
 318#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 319#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 320#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
 321#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 322#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
 323#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
 324#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 325#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 326#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
 327#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 328#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 329#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
 330#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 331#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 332#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
 333#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 334#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 335#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
 336#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 337#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 338#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
 339#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 340#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 341#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
 342#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 343#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 344#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
 345#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 346#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 347#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
 348#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 349#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 350#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
 351#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 352#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 353#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
 354#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 355#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 356#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
 357#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 358#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 359#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
 360#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 361#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 362#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
 363#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 364#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 365#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
 366#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 367#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 368#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
 369#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 370#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 371#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
 372#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 373#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 374#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
 375#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 376#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 377#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
 378#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 379#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 380#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
 381#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 382#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 383#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
 384#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 385#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 386#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
 387#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 388#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 389#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
 390#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 391#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 392#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
 393#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 394#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 395#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
 396#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 397#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 398#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
 399#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 400#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 401#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
 402#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 403#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 404#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
 405#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 406#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 407#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
 408#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 409#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 410#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
 411#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 412#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 413#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
 414#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 415#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 416#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
 417#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 418#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 419#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
 420#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 421#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 422#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
 423#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 424#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 425#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
 426#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 427#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 428#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
 429#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 430#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 431#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
 432#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 433#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 434#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
 435#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 436#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 437#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
 438#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 439#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 440#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
 441#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 442#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 443#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
 444#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 445#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 446#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
 447#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 448#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 449#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
 450#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 451#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 452#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
 453#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 454#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 455#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
 456#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 457#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 458#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
 459#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 460#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 461#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
 462#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 463#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 464#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
 465#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 466#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 467#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
 468#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 469#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 470#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
 471#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 472#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 473#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
 474#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 475#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 476#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
 477#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 478#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 479#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
 480#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 481#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 482#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
 483#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 484#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 485#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
 486#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 487#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 488#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
 489#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 490#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 491#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
 492#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 493#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 494#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
 495#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 496#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 497#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
 498#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 499#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 500#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
 501#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 502#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 503#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
 504#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 505#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 506#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
 507#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 508#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 509#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
 510#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 511#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 512#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
 513#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 514#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 515#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
 516#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 517#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 518#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
 519#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 520#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 521#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
 522#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 523#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 524#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
 525#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 526#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 527#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
 528#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 529#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 530#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
 531#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 532#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 533#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
 534#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 535#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 536#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
 537#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 538#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 539#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
 540#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 541#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 542#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
 543#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 544#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 545#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
 546#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 547#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 548#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
 549#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 550#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 551#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
 552#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 553#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 554#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
 555#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
 556#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
 557#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
 558#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
 559#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
 560#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
 561#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
 562#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
 563#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
 564#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
 565#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
 566#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
 567#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
 568#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
 569#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
 570#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
 571#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
 572#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
 573#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
 574#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
 575#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
 576#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
 577#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
 578#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
 579#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
 580#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
 581#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
 582#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
 583#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
 584#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
 585#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
 586#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
 587#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
 588#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
 589#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
 590#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
 591#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
 592#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
 593#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
 594#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
 595#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
 596#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
 597#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
 598#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
 599#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
 600#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
 601#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
 602#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
 603#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
 604#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
 605#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
 606#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
 607#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
 608#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
 609#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
 610#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
 611#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
 612#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
 613#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
 614#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
 615#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
 616#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
 617#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
 618#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
 619#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
 620#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
 621#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
 622#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
 623#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
 624#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
 625#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
 626#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
 627#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
 628#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
 629#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
 630#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
 631#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
 632#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
 633#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
 634#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
 635#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
 636#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
 637#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
 638#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
 639#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
 640#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
 641#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
 642#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
 643#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
 644#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
 645#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
 646#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
 647#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
 648#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
 649#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
 650#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
 651#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
 652#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
 653#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
 654#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
 655#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
 656#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
 657#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
 658#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
 659#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
 660#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
 661#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
 662#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
 663#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
 664#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
 665#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
 666#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
 667#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
 668#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
 669#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
 670#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
 671#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
 672#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
 673#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
 674#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
 675#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
 676#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
 677#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
 678#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
 679#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
 680#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
 681#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
 682#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
 683#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
 684#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
 685#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
 686#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
 687#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
 688#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
 689#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
 690#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
 691#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
 692#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
 693#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
 694#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
 695#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
 696#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
 697#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
 698#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
 699#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
 700#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
 701#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
 702#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
 703#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
 704#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
 705#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
 706#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
 707#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
 708#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
 709#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
 710#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
 711#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
 712#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
 713#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
 714#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
 715#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
 716#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
 717#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
 718#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
 719#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
 720#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
 721#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
 722#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
 723#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
 724#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
 725#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
 726#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
 727#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
 728#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
 729#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
 730#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
 731#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
 732#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
 733#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
 734#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
 735#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
 736#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
 737#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
 738#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
 739#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
 740#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
 741#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
 742#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
 743#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
 744#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
 745#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
 746#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
 747#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
 748#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
 749#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
 750#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
 751#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
 752#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
 753#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
 754#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
 755#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
 756#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
 757#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
 758#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
 759#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
 760#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
 761#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
 762#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
 763#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
 764#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
 765#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
 766#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
 767#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
 768#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
 769#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
 770#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
 771#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
 772#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
 773#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
 774#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
 775#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
 776#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
 777#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
 778#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
 779#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
 780#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
 781#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
 782#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
 783#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
 784#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
 785#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
 786#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
 787#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
 788#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
 789#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
 790#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
 791#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
 792#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
 793#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
 794#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
 795#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
 796#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
 797#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
 798#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
 799#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
 800#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
 801#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
 802#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
 803#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
 804#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
 805#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
 806#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
 807#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
 808#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
 809#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
 810#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
 811#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
 812#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
 813#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
 814#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
 815#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
 816#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
 817#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
 818#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
 819#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
 820#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
 821#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
 822#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
 823#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
 824#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
 825#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
 826#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
 827#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
 828#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
 829#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
 830#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
 831#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
 832#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
 833#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
 834#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
 835#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
 836#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
 837#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
 838#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
 839#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
 840#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
 841#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
 842#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
 843#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
 844#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
 845#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
 846#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
 847#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
 848#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
 849#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
 850#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
 851#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
 852#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
 853#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
 854#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
 855#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
 856#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
 857#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
 858#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
 859#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
 860#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
 861#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
 862#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
 863#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
 864#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
 865#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 866#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
 867#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
 868#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
 869#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
 870#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
 871#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
 872#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
 873#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
 874#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
 875#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
 876#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
 877#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
 878#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
 879#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
 880#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
 881#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
 882#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
 883#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
 884#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
 885#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
 886#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
 887#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
 888#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
 889#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
 890#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
 891#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
 892#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
 893#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
 894#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
 895#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
 896#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
 897#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
 898#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
 899#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
 900#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
 901#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
 902#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
 903#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
 904#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
 905#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
 906#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
 907#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
 908#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
 909#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
 910#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
 911#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
 912#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
 913#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
 914#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
 915#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
 916#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
 917#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
 918#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
 919#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
 920#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
 921#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
 922#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
 923#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
 924#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
 925#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
 926#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
 927#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
 928#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
 929#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
 930#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
 931#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
 932#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
 933#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
 934#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
 935#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
 936#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
 937#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
 938#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
 939#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
 940#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
 941#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
 942#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
 943#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
 944#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
 945#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
 946#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
 947#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
 948#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
 949#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
 950#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
 951#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
 952#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
 953#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
 954#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
 955#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
 956#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
 957#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
 958#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
 959#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
 960#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
 961#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
 962#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
 963#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
 964#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
 965#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
 966#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
 967#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
 968#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
 969#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
 970#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
 971#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
 972#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
 973#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
 974#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
 975#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
 976#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
 977#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
 978#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
 979#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
 980#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
 981#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
 982#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
 983#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
 984#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
 985#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
 986#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
 987#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
 988#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
 989#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
 990#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
 991#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
 992#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
 993#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
 994#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
 995#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
 996#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
 997#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
 998#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
 999#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
1000#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)

1001#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
1002#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
1003#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
1004#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
1005#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
1006#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
1007#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
1008#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
1009#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
1010#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
1011#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
1012#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
1013#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1014#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
1015#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
1016#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
1017#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
1018#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
1019#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
1020#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
1021#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
1022#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
1023#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
1024#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
1025#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
1026#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
1027#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
1028#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
1029#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
1030#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
1031#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
1032#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
1033#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
1034#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
1035#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
1036#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
1037#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
1038#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
1039#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
1040#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
1041#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
1042#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
1043#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
1044#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
1045#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
1046#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
1047#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
1048#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
1049#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
1050#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
1051#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
1052#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
1053#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
1054#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
1055#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
1056#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
1057#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
1058#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
1059#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
1060#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
1061#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
1062#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
1063#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
1064#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
1065#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
1066#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
1067#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
1068#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
1069#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
1070#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
1071#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
1072#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
1073#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
1074#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
1075#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
1076#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
1077#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
1078#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
1079#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
1080#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
1081#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
1082#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
1083#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
1084#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
1085#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
1086#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
1087#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
1088#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
1089#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
1090#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
1091#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
1092#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
1093#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
1094#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
1095#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
1096#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
1097#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
1098#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
1099#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
1100#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
1101#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
1102#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
1103#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
1104#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
1105#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
1106#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
1107#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
1108#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
1109#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
1110#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
1111#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
1112#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
1113#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
1114#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
1115#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
1116#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
1117#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
1118#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
1119#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
1120#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
1121#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
1122#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
1123#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
1124#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
1125#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
1126#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
1127#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
1128#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
1129#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
1130#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
1131#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
1132#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
1133#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
1134#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
1135#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
1136#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
1137#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
1138#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
1139#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
1140#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
1141#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
1142#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
1143#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
1144#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
1145#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
1146#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
1147#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
1148#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
1149#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
1150#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
1151#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
1152#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
1153#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
1154#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
1155#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
1156#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
1157#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
1158#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
1159#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
1160#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
1161#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
1162#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
1163#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
1164#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
1165#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
1166#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
1167#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
1168#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
1169#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
1170#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
1171#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
1172#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
1173#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
1174#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
1175#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
1176#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
1177#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
1178#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
1179#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
1180#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
1181#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
1182#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
1183#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
1184#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
1185#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
1186#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
1187#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1188#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
1189#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
1190#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1191#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
1192#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
1193#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
1194#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
1195#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
1196#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1197#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
1198#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
1199#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
1200#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
1201#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
1202#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
1203#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
1204#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
1205#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
1206#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
1207#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1208#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1209#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
1210#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
1211#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1212#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
1213#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
1214#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1215#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
1216#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1217#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1218#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
1219#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
1220#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
1221#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
1222#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
1223#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
1224#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
1225#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
1226#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1227#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
1228#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
1229#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1230#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
1231#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
1232#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
1233#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
1234#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
1235#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1236#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
1237#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
1238#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
1239#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
1240#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
1241#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
1242#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
1243#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
1244#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
1245#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
1246#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1247#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1248#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
1249#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
1250#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1251#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
1252#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
1253#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1254#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
1255#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
1256#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1257#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
1258#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
1259#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
1260#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
1261#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
1262#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
1263#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
1264#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
1265#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1266#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
1267#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
1268#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1269#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
1270#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
1271#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
1272#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
1273#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
1274#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1275#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
1276#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
1277#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
1278#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
1279#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
1280#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
1281#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
1282#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
1283#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
1284#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
1285#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1286#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1287#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
1288#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
1289#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1290#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
1291#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
1292#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1293#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
1294#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1295#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1296#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
1297#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
1298#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
1299#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
1300#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
1301#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
1302#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
1303#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
1304#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1305#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
1306#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
1307#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1308#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
1309#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
1310#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
1311#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
1312#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
1313#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1314#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
1315#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
1316#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
1317#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
1318#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
1319#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
1320#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
1321#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
1322#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
1323#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
1324#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1325#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1326#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
1327#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
1328#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1329#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
1330#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
1331#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1332#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
1333#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
1334#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1335#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
1336#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
1337#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1338#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
1339#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
1340#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
1341#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
1342#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
1343#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
1344#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
1345#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
1346#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
1347#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
1348#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
1349#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
1350#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
1351#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
1352#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1353#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1354#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
1355#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1356#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
1357#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
1358#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1359#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
1360#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
1361#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
1362#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
1363#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
1364#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
1365#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
1366#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
1367#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1368#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1369#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
1370#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1371#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
1372#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
1373#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
1374#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
1375#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
1376#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
1377#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
1378#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
1379#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
1380#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
1381#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
1382#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
1383#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
1384#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
1385#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
1386#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
1387#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
1388#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
1389#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
1390#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
1391#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
1392#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
1393#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
1394#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
1395#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
1396#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
1397#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
1398#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
1399#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
1400#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
1401#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
1402#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
1403#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
1404#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
1405#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
1406#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
1407#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
1408#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
1409#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
1410#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
1411#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
1412#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
1413#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
1414#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
1415#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
1416#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
1417#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
1418#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
1419#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
1420#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
1421#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
1422#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
1423#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
1424#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
1425#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
1426#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
1427#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
1428#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
1429#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
1430#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
1431#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
1432#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
1433#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
1434#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
1435#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
1436#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
1437#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
1438#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
1439#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
1440#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
1441#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
1442#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
1443#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
1444#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
1445#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
1446#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
1447#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
1448#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
1449#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
1450#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
1451#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
1452#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
1453#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
1454#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
1455#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
1456#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
1457#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
1458#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
1459#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
1460#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
1461#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
1462#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
1463#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
1464#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
1465#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
1466#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
1467#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
1468#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
1469#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
1470#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
1471#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
1472#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
1473#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
1474#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
1475#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
1476#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
1477#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
1478#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
1479#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
1480#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
1481#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
1482#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
1483#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
1484#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
1485#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
1486#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
1487#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
1488#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
1489#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
1490#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
1491#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
1492#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
1493#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
1494#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
1495#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
1496#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
1497#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
1498#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
1499#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
1500#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
1501#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
1502#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
1503#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
1504#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
1505#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
1506#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
1507#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
1508#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
1509#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
1510#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
1511#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
1512#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
1513#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
1514#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
1515#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
1516#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
1517#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
1518#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
1519#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
1520#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
1521#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
1522#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
1523#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
1524#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
1525#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
1526#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
1527#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
1528#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
1529#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
1530#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
1531#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
1532#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
1533#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
1534#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
1535#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
1536#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
1537#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
1538#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
1539#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
1540#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
1541#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
1542#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
1543#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
1544#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
1545#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
1546#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
1547#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
1548#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
1549#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
1550#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
1551#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
1552#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
1553#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
1554#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
1555#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
1556#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
1557#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
1558#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
1559#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
1560#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
1561#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
1562#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
1563#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
1564#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
1565#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
1566#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
1567#define bfin_read_PORTA()              bfin_read16(PORTA)
1568#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
1569#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
1570#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
1571#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
1572#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
1573#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
1574#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
1575#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
1576#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
1577#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
1578#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
1579#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
1580#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
1581#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
1582#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
1583#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
1584#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
1585#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
1586#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
1587#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
1588#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
1589#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
1590#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
1591#define bfin_read_PORTB()              bfin_read16(PORTB)
1592#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
1593#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
1594#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
1595#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
1596#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
1597#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
1598#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
1599#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
1600#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
1601#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
1602#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
1603#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
1604#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
1605#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
1606#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
1607#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
1608#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
1609#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
1610#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
1611#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
1612#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
1613#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
1614#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
1615#define bfin_read_PORTC()              bfin_read16(PORTC)
1616#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
1617#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
1618#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
1619#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
1620#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
1621#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
1622#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
1623#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
1624#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
1625#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
1626#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
1627#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
1628#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
1629#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
1630#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
1631#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
1632#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
1633#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
1634#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
1635#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
1636#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
1637#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
1638#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
1639#define bfin_read_PORTD()              bfin_read16(PORTD)
1640#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
1641#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
1642#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
1643#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
1644#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
1645#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
1646#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
1647#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
1648#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
1649#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
1650#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
1651#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
1652#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
1653#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
1654#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
1655#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
1656#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
1657#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
1658#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
1659#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
1660#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
1661#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
1662#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
1663#define bfin_read_PORTE()              bfin_read16(PORTE)
1664#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
1665#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
1666#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
1667#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
1668#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
1669#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
1670#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
1671#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
1672#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
1673#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
1674#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
1675#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
1676#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
1677#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
1678#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
1679#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
1680#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
1681#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
1682#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
1683#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
1684#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
1685#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
1686#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
1687#define bfin_read_PORTF()              bfin_read16(PORTF)
1688#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
1689#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
1690#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
1691#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
1692#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
1693#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
1694#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
1695#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
1696#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
1697#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
1698#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
1699#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
1700#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
1701#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
1702#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
1703#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
1704#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
1705#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
1706#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
1707#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
1708#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
1709#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
1710#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
1711#define bfin_read_PORTG()              bfin_read16(PORTG)
1712#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
1713#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
1714#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
1715#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
1716#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
1717#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
1718#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
1719#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
1720#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
1721#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
1722#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
1723#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
1724#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
1725#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
1726#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
1727#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
1728#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
1729#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
1730#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
1731#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
1732#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
1733#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
1734#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
1735#define bfin_read_PORTH()              bfin_read16(PORTH)
1736#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
1737#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
1738#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
1739#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
1740#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
1741#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
1742#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
1743#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
1744#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
1745#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
1746#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
1747#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
1748#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
1749#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
1750#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
1751#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
1752#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
1753#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
1754#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
1755#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
1756#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
1757#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
1758#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
1759#define bfin_read_PORTI()              bfin_read16(PORTI)
1760#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
1761#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
1762#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
1763#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
1764#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
1765#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
1766#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
1767#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
1768#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
1769#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
1770#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
1771#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
1772#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
1773#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
1774#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
1775#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
1776#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
1777#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
1778#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
1779#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
1780#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
1781#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
1782#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
1783#define bfin_read_PORTJ()              bfin_read16(PORTJ)
1784#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
1785#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
1786#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
1787#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
1788#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
1789#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
1790#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
1791#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
1792#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
1793#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
1794#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
1795#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
1796#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
1797#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
1798#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
1799#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
1800#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
1801#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
1802#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
1803#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
1804#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
1805#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
1806#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
1807#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
1808#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
1809#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
1810#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
1811#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
1812#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
1813#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
1814#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
1815#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
1816#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
1817#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
1818#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
1819#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
1820#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
1821#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
1822#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
1823#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
1824#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
1825#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
1826#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
1827#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
1828#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
1829#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
1830#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
1831#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
1832#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
1833#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
1834#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
1835#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
1836#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
1837#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
1838#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
1839#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
1840#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
1841#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
1842#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
1843#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
1844#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
1845#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
1846#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
1847#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
1848#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
1849#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
1850#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
1851#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
1852#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
1853#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
1854#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
1855#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
1856#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
1857#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
1858#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
1859#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
1860#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
1861#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
1862#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
1863#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
1864#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
1865#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
1866#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
1867#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
1868#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
1869#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
1870#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
1871#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
1872#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
1873#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
1874#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
1875#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
1876#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
1877#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
1878#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
1879#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
1880#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
1881#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
1882#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
1883#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
1884#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
1885#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
1886#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
1887#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
1888#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
1889#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
1890#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
1891#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
1892#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
1893#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
1894#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
1895#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
1896#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
1897#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
1898#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
1899#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
1900#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
1901#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
1902#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
1903#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
1904#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
1905#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
1906#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
1907#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
1908#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
1909#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
1910#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
1911#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
1912#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
1913#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
1914#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
1915#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
1916#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
1917#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
1918#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
1919#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
1920#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
1921#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
1922#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
1923#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
1924#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
1925#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
1926#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
1927#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
1928#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
1929#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
1930#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
1931#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
1932#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
1933#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
1934#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
1935#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
1936#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
1937#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
1938#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
1939#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
1940#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
1941#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
1942#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
1943#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
1944#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
1945#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
1946#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
1947#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
1948#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
1949#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
1950#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
1951#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
1952#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
1953#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
1954#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
1955#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
1956#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
1957#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
1958#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
1959#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
1960#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
1961#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
1962#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
1963#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
1964#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
1965#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
1966#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
1967#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
1968#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
1969#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
1970#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
1971#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
1972#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
1973#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
1974#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
1975#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
1976#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
1977#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
1978#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
1979#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
1980#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
1981#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
1982#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
1983#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
1984#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
1985#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
1986#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
1987#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
1988#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
1989#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
1990#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
1991#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
1992#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
1993#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
1994#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
1995#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
1996#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
1997#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
1998#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
1999#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
2000#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)

2001#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
2002#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
2003#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
2004#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
2005#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
2006#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
2007#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
2008#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
2009#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
2010#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
2011#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
2012#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
2013#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
2014#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
2015#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
2016#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
2017#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
2018#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
2019#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
2020#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
2021#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
2022#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
2023#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
2024#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
2025#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
2026#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
2027#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
2028#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
2029#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
2030#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
2031#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
2032#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
2033#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
2034#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
2035#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
2036#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
2037#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
2038#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
2039#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
2040#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
2041#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
2042#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
2043#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
2044#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
2045#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
2046#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
2047#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
2048#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
2049#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
2050#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
2051#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
2052#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
2053#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
2054#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
2055#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
2056#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
2057#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
2058#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
2059#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
2060#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
2061#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
2062#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
2063#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
2064#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
2065#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
2066#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
2067#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
2068#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
2069#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
2070#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
2071#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
2072#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
2073#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
2074#define bfin_read_TCNTL()              bfin_read32(TCNTL)
2075#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
2076#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
2077#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
2078#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
2079#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
2080#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
2081#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
2082#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
2083#define bfin_read_TSCALE()             bfin_read32(TSCALE)
2084#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
2085#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
2086#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
2087#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
2088#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
2089#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
2090#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
2091#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
2092#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
2093#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
2094#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
2095#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
2096#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
2097#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
2098#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
2099#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
2100#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
2101#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
2102#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
2103#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
2104#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
2105#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
2106#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
2107#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
2108#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
2109#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
2110#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
2111#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
2112#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
2113#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
2114#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
2115#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
2116#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
2117#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
2118#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
2119#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
2120#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
2121#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
2122#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
2123#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
2124#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
2125#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
2126#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
2127#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
2128#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
2129#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
2130#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
2131#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
2132#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
2133#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
2134#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
2135#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
2136#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
2137#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
2138#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
2139#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
2140#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
2141#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
2142#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
2143#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
2144#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
2145#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
2146#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
2147#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
2148#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
2149#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
2150#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
2151#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
2152#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
2153#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
2154#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
2155#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
2156#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
2157#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
2158#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
2159#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
2160#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
2161#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
2162#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
2163#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
2164#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
2165#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
2166#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
2167#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
2168#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
2169#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
2170#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
2171#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
2172#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
2173#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
2174#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
2175#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
2176#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
2177#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
2178#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
2179#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
2180#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
2181#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
2182#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
2183#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
2184#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
2185#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
2186#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
2187#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
2188#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
2189#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
2190#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
2191#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
2192#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
2193#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
2194#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
2195#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
2196#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
2197#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
2198#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
2199#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
2200#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
2201#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
2202#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
2203#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
2204#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
2205#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
2206#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
2207#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
2208#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
2209#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
2210#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
2211#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
2212#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
2213#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
2214#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
2215#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
2216#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
2217#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
2218#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
2219#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
2220#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
2221#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
2222#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
2223#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
2224#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
2225#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
2226#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
2227#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
2228#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
2229#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
2230#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
2231#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
2232#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
2233#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
2234#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
2235#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
2236#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
2237#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
2238#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
2239#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
2240#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
2241#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
2242#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
2243#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
2244#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
2245#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
2246#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
2247#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
2248#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
2249#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
2250#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
2251#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
2252#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
2253#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
2254#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
2255#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
2256#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
2257#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
2258#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
2259#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
2260#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
2261#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
2262#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
2263#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
2264#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
2265#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
2266#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
2267#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
2268#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
2269#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
2270#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
2271#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
2272#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
2273#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
2274#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
2275#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
2276#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
2277#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
2278#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
2279#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
2280#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
2281#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
2282#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
2283#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
2284#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
2285#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
2286#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
2287#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
2288#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
2289#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
2290#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
2291#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
2292#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
2293#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
2294#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
2295#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
2296#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
2297#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
2298#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
2299#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
2300#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
2301#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
2302#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
2303#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
2304#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
2305#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
2306#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
2307#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
2308#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
2309#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
2310#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
2311#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
2312#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
2313#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
2314#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
2315#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
2316#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
2317#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
2318#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
2319#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
2320#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
2321#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
2322#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
2323#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
2324#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
2325#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
2326#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
2327#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
2328#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
2329#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
2330#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
2331#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
2332#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
2333#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
2334#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
2335#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
2336#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
2337#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
2338#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
2339#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
2340#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
2341#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
2342#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
2343#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
2344#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
2345#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
2346#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
2347#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
2348#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
2349#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
2350#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
2351#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
2352#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
2353#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
2354#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
2355#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
2356#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
2357#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
2358#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
2359#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
2360#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
2361#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
2362#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
2363#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
2364#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
2365#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
2366#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
2367#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
2368#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
2369#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
2370#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
2371#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
2372#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
2373#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
2374#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
2375#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
2376#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
2377#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
2378#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
2379#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
2380#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
2381#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
2382#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
2383#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
2384#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
2385#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
2386#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
2387#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
2388#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
2389#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
2390#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
2391#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
2392#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
2393#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
2394#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
2395#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
2396#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
2397#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
2398#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
2399#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
2400#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
2401#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
2402#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
2403#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
2404#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
2405#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
2406#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
2407#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
2408#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
2409#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
2410#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
2411#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
2412#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
2413#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
2414#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
2415#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
2416#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
2417#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
2418#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
2419#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
2420#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
2421#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
2422#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
2423#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
2424#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
2425#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
2426#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
2427#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
2428#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
2429#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
2430#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
2431#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
2432#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
2433#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
2434#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
2435#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
2436#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
2437#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
2438#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
2439#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
2440#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
2441#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
2442#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
2443#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
2444#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
2445#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
2446#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
2447#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
2448#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
2449#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
2450#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
2451#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
2452#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
2453#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
2454#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
2455#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
2456#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
2457#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
2458#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
2459#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
2460#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
2461#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
2462#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
2463#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
2464#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
2465#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
2466#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
2467#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
2468#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
2469#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
2470#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
2471#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
2472#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
2473#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
2474#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
2475#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
2476#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
2477#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
2478#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
2479#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
2480#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
2481#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
2482#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
2483#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
2484#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
2485#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
2486#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
2487#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
2488#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
2489#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
2490#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
2491#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
2492#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
2493#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
2494#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
2495#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
2496#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
2497#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
2498#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
2499#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
2500#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
2501#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
2502#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
2503#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
2504#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
2505#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
2506#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
2507#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
2508#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
2509#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
2510#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
2511#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
2512#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
2513#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
2514#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
2515#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
2516#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
2517#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
2518#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
2519#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
2520#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
2521#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
2522#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
2523#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
2524#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
2525#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
2526#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
2527#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
2528#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
2529#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
2530#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
2531#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
2532#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
2533#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
2534#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
2535#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
2536#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
2537#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
2538#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
2539#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
2540#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
2541#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
2542#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
2543#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
2544#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
2545#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
2546#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
2547#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
2548#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
2549#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
2550#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
2551#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
2552#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
2553#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
2554#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
2555#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
2556#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
2557#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
2558#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
2559#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
2560#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
2561#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
2562#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
2563#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
2564#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
2565#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
2566#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
2567#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
2568#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
2569#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
2570#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
2571#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
2572#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
2573#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
2574#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
2575#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
2576#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
2577#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
2578#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
2579#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
2580#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
2581#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
2582#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
2583#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
2584#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
2585#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
2586#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
2587#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
2588#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
2589#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
2590#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
2591#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
2592#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
2593#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
2594#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
2595#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
2596#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
2597#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
2598#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
2599#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
2600#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
2601#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
2602#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
2603#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
2604#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
2605#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
2606#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
2607#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
2608#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
2609#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
2610#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
2611#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
2612#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
2613#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
2614#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
2615#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
2616#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
2617#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
2618#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
2619#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
2620#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
2621#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
2622#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
2623#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
2624#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
2625#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
2626#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
2627#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
2628#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
2629#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
2630#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
2631#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
2632#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
2633#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
2634#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
2635#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
2636#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
2637#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
2638#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
2639#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
2640#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
2641#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
2642#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
2643#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
2644#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
2645#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
2646#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
2647#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
2648#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
2649#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
2650#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
2651#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
2652#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
2653#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
2654#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
2655#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
2656#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
2657#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
2658#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
2659#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
2660#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
2661#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
2662#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
2663#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
2664#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
2665#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
2666#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
2667#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
2668#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
2669#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
2670#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
2671#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
2672#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
2673#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
2674#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
2675#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
2676#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
2677#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
2678#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2679#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
2680#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
2681#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2682#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
2683#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
2684#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2685#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
2686#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
2687#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2688#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
2689#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
2690#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2691#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
2692#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
2693#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2694#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
2695#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
2696#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
2697#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
2698#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
2699#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
2700#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
2701#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
2702#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2703#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
2704#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
2705#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2706#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
2707#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
2708#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2709#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
2710#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
2711#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2712#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
2713#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
2714#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2715#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
2716#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
2717#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2718#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
2719#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
2720#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
2721#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
2722#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
2723#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
2724#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
2725#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
2726#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2727#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
2728#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
2729#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2730#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
2731#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
2732#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2733#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
2734#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
2735#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2736#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
2737#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
2738#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2739#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
2740#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
2741#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2742#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
2743#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
2744#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
2745#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
2746#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
2747#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
2748#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
2749#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
2750#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2751#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
2752#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
2753#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2754#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
2755#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
2756#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2757#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
2758#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
2759#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2760#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
2761#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
2762#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2763#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
2764#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
2765#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2766#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
2767#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
2768#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
2769#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
2770#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
2771#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
2772#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
2773#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
2774#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2775#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
2776#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
2777#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2778#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
2779#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
2780#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2781#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
2782#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
2783#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2784#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
2785#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
2786#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2787#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
2788#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
2789#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2790#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
2791#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
2792#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
2793#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
2794#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
2795#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
2796#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
2797#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
2798#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2799#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
2800#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
2801#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2802#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
2803#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
2804#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2805#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
2806#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
2807#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2808#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
2809#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
2810#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2811#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
2812#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
2813#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2814#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
2815#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
2816#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
2817#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
2818#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
2819#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
2820#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
2821#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
2822#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2823#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
2824#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
2825#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2826#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
2827#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
2828#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2829#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
2830#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
2831#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2832#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
2833#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
2834#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2835#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
2836#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
2837#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2838#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
2839#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
2840#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
2841#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
2842#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
2843#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
2844#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
2845#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
2846#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2847#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
2848#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
2849#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2850#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
2851#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
2852#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2853#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
2854#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
2855#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2856#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
2857#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
2858#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2859#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
2860#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
2861#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2862#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
2863#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
2864#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
2865#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
2866#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
2867#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
2868#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
2869#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
2870#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2871#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
2872#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
2873#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2874#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
2875#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
2876#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2877#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
2878#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
2879#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2880#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
2881#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
2882#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2883#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
2884#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
2885#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2886#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
2887#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
2888#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
2889#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
2890#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
2891#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
2892#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
2893#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
2894#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2895#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
2896#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
2897#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2898#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
2899#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
2900#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2901#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
2902#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
2903#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2904#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
2905#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
2906#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2907#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
2908#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
2909#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2910#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
2911#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
2912#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
2913#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
2914#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
2915#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
2916#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
2917#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
2918#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2919#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
2920#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
2921#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2922#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
2923#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
2924#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2925#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
2926#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
2927#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2928#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
2929#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
2930#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2931#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
2932#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
2933#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2934#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
2935#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
2936#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
2937#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
2938#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
2939#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
2940#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
2941#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
2942#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2943#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
2944#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
2945#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2946#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
2947#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
2948#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2949#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
2950#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
2951#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2952#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
2953#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
2954#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2955#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
2956#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
2957#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2958#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
2959#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
2960#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
2961#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
2962#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
2963#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
2964#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
2965#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
2966#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2967#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
2968#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
2969#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2970#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
2971#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
2972#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2973#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
2974#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
2975#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2976#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
2977#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
2978#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2979#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
2980#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
2981#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2982#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
2983#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
2984#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
2985#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
2986#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
2987#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
2988#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
2989#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
2990#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2991#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
2992#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
2993#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2994#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
2995#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
2996#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2997#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
2998#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
2999#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
3000#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */

3001#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
3002#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
3003#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
3004#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
3005#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
3006#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
3007#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
3008#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
3009#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
3010#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
3011#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
3012#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
3013#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
3014#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
3015#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
3016#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
3017#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
3018#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
3019#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
3020#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
3021#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
3022#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
3023#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
3024#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
3025#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
3026#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
3027#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
3028#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
3029#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
3030#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
3031#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
3032#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
3033#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
3034#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
3035#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
3036#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
3037#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
3038#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
3039#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
3040#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
3041#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
3042#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
3043#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
3044#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
3045#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
3046#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
3047#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
3048#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
3049#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
3050#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
3051#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
3052#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
3053#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
3054#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
3055#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
3056#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
3057#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
3058#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
3059#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
3060#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
3061#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
3062#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
3063#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
3064#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
3065#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
3066#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
3067#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
3068#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
3069#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
3070#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
3071#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
3072#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
3073#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
3074#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
3075#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
3076#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
3077#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
3078#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
3079#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
3080#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
3081#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
3082#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
3083#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
3084#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
3085#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
3086#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
3087#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
3088#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
3089#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
3090#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
3091#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
3092#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
3093#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
3094#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
3095#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
3096#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
3097#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
3098#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
3099#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
3100#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
3101#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
3102#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
3103#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
3104#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
3105#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
3106#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
3107#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
3108#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
3109#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
3110#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
3111#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
3112#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
3113#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
3114#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
3115#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
3116#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
3117#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
3118#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
3119#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
3120#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
3121#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
3122#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
3123#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
3124#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
3125#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
3126#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
3127#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
3128#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
3129#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
3130#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
3131#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
3132#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
3133#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
3134#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
3135#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
3136#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
3137#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
3138#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
3139#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
3140#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
3141#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
3142#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
3143#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
3144#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
3145#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
3146#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
3147#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
3148#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
3149#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
3150#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
3151#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
3152#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
3153#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
3154#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
3155#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
3156#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
3157#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
3158#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
3159#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
3160#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
3161#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
3162#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
3163#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
3164#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
3165#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
3166#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
3167#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
3168#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
3169#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
3170#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
3171#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
3172#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
3173#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
3174#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
3175#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
3176#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
3177#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
3178#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
3179#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
3180#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
3181#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
3182#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
3183#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
3184#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
3185#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
3186#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
3187#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
3188#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
3189#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
3190#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
3191#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
3192#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
3193#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
3194#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
3195#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
3196#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
3197#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
3198#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
3199#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
3200#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
3201#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
3202#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
3203#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
3204#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
3205#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
3206#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
3207#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
3208#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
3209#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
3210#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
3211#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
3212#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
3213#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
3214#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
3215#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
3216#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
3217#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
3218#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
3219#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
3220#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
3221#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
3222#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
3223#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
3224#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
3225#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
3226#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
3227#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
3228#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
3229#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
3230#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
3231#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
3232#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
3233#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
3234#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
3235#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
3236#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
3237#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
3238#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
3239#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
3240#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
3241#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
3242#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
3243#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
3244#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
3245#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
3246#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
3247#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
3248#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
3249#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
3250#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
3251#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
3252#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
3253#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
3254#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
3255#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
3256#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
3257#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
3258#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
3259#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
3260#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
3261#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
3262#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
3263#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
3264#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
3265#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
3266#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
3267#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
3268#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
3269#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
3270#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
3271#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
3272#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
3273#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
3274#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
3275#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
3276#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
3277#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
3278#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
3279#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
3280#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
3281#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
3282#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
3283#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
3284#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
3285#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
3286#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
3287#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
3288#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
3289#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
3290#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
3291#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
3292#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
3293#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
3294#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
3295#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
3296#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
3297#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
3298#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
3299#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
3300#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
3301#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
3302#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
3303#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
3304#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
3305#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
3306#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
3307#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
3308#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
3309#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
3310#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
3311#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
3312#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
3313#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
3314#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
3315#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
3316#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
3317#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
3318#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
3319#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
3320#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
3321#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
3322#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
3323#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
3324#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
3325#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
3326#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
3327#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
3328#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
3329#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
3330#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
3331#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
3332#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
3333#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
3334#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
3335#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
3336#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
3337#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
3338#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
3339#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
3340#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
3341#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
3342#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
3343#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
3344#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
3345#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
3346#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
3347#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
3348#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
3349#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
3350#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
3351#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
3352#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
3353#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
3354#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
3355#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
3356#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
3357#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
3358#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
3359#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
3360#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
3361#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
3362#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
3363#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
3364#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
3365#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
3366#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
3367#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
3368#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
3369#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
3370#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
3371#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
3372#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
3373#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
3374#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
3375#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
3376#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
3377#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
3378#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
3379#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
3380#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
3381#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
3382#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
3383#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
3384#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
3385#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
3386#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
3387#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
3388#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
3389#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
3390#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
3391#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
3392#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
3393#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
3394#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
3395#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
3396#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
3397#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
3398#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
3399#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
3400#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
3401#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
3402#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
3403#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
3404#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
3405#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
3406#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
3407#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
3408#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
3409#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
3410#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
3411#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
3412#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
3413#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
3414#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
3415#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
3416#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
3417#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
3418#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
3419#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
3420#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
3421#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
3422#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
3423#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
3424#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
3425#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
3426#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
3427#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
3428#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
3429#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
3430#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
3431#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
3432#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
3433#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
3434#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
3435#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
3436#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
3437#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
3438#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
3439#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
3440#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
3441#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
3442#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
3443#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
3444#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
3445#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
3446#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
3447#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
3448#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
3449#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
3450#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
3451#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
3452#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
3453#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
3454#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
3455#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
3456#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
3457#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
3458#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
3459#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
3460#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
3461#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
3462#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
3463#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
3464#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
3465#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
3466#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
3467#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
3468#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
3469#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
3470#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
3471#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
3472#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
3473#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
3474#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
3475#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
3476#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
3477#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
3478#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
3479#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
3480#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
3481#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
3482#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
3483#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
3484#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
3485#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
3486#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
3487#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
3488#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
3489#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
3490#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
3491#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
3492#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
3493#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
3494#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
3495#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
3496#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
3497#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
3498#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
3499#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
3500#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
3501#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
3502#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
3503#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
3504#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
3505#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
3506#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
3507#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
3508#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
3509#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
3510#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
3511#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
3512#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
3513#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
3514#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
3515#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
3516#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
3517#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
3518#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
3519#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
3520#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
3521#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
3522#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
3523#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
3524#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
3525#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
3526#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
3527#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
3528#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
3529#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
3530#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
3531#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
3532#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
3533#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
3534#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
3535#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
3536#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
3537#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
3538#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
3539#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
3540#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
3541#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
3542#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
3543#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
3544#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
3545#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
3546#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
3547#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
3548#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
3549#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
3550#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
3551#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
3552#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
3553#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
3554#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
3555#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
3556#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
3557#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
3558#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
3559#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
3560#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
3561#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
3562#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
3563#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
3564#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
3565#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
3566#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
3567#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
3568#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
3569#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
3570#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
3571#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
3572#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
3573#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
3574#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
3575#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
3576#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
3577#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
3578#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
3579#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
3580#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
3581#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
3582#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
3583#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
3584#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
3585#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
3586#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
3587#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
3588#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
3589#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
3590#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
3591#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
3592#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
3593#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
3594#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
3595#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
3596#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
3597#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
3598#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
3599#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
3600#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
3601#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
3602#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
3603#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
3604#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
3605#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
3606#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
3607#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
3608#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
3609#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
3610#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
3611#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
3612#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
3613#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
3614#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
3615#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
3616#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
3617#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
3618#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
3619#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
3620#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
3621#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
3622#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
3623#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
3624#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
3625#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
3626#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
3627#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
3628#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
3629#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
3630#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
3631#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
3632#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
3633#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
3634#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
3635#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
3636#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
3637#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
3638#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
3639#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
3640#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
3641#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
3642#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
3643#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
3644#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
3645#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
3646#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
3647#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
3648#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
3649#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
3650#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
3651#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
3652#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
3653#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
3654#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
3655#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
3656#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
3657#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
3658#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
3659#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
3660#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
3661#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
3662#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
3663#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
3664#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
3665#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
3666#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
3667#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
3668#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
3669#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
3670#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
3671#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
3672#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
3673#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
3674#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
3675#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
3676#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
3677#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
3678#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
3679#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
3680#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
3681#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
3682#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
3683#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
3684#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
3685#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
3686#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
3687#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
3688#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
3689#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
3690#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
3691#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
3692#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
3693#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
3694#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
3695#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
3696#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
3697#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
3698#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
3699#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
3700#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
3701#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
3702#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
3703#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
3704#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
3705#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
3706#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
3707#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
3708#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
3709#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
3710#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
3711#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
3712#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
3713#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
3714#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
3715#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
3716#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
3717#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
3718#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
3719#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
3720#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
3721#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
3722#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
3723#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
3724#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
3725#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
3726#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
3727#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
3728#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
3729#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
3730#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
3731#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
3732#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
3733#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
3734#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
3735#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
3736#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
3737#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
3738#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
3739#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
3740#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
3741#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
3742#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
3743#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
3744#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
3745#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
3746#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
3747#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
3748#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
3749#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
3750#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
3751#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
3752#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
3753#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
3754#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
3755#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
3756#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
3757#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
3758#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
3759#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
3760#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
3761#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
3762#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
3763#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
3764#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
3765#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
3766#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
3767#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
3768#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
3769#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
3770#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
3771#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
3772#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
3773#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
3774#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
3775#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
3776#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
3777#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
3778#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
3779#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
3780#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
3781#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
3782#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
3783#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
3784#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
3785#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
3786#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
3787#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
3788#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
3789#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
3790#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
3791#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
3792#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
3793#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
3794#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
3795#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
3796#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
3797#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
3798#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
3799#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
3800#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
3801#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
3802#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
3803#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
3804#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
3805#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
3806#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
3807#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
3808#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
3809#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
3810#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
3811#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
3812#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
3813#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
3814#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
3815#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
3816#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
3817#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
3818#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
3819#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
3820#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
3821#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
3822#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
3823#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
3824#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
3825#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
3826#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
3827#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
3828#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
3829#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
3830#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
3831#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
3832#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
3833#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
3834#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
3835#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
3836#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
3837#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
3838#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
3839#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
3840#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
3841#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
3842#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
3843#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
3844#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
3845#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
3846#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
3847#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
3848#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
3849#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
3850#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
3851#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
3852#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
3853#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
3854#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
3855#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
3856#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
3857#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
3858#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
3859#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
3860#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
3861#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
3862#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
3863#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
3864#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
3865#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
3866#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
3867#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
3868#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
3869#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
3870#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
3871#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
3872#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
3873#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
3874#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
3875#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
3876#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
3877#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
3878#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
3879#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
3880#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
3881#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
3882#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
3883#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
3884#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
3885#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
3886#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
3887#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
3888#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
3889#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
3890#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
3891#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
3892#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
3893#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
3894#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
3895#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
3896#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
3897#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
3898#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
3899#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
3900#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
3901#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
3902#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
3903#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
3904#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
3905#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
3906#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
3907#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
3908#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
3909#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
3910#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
3911#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
3912#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
3913#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
3914#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
3915#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
3916#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
3917#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
3918#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
3919#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
3920#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
3921#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
3922#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
3923#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
3924#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
3925#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
3926#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
3927#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
3928#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
3929#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
3930#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
3931#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
3932#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
3933#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
3934#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
3935#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
3936#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
3937#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
3938#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
3939#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
3940#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
3941#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
3942#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
3943#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
3944#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
3945#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
3946#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
3947#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
3948#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
3949#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
3950#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
3951#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
3952#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
3953#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
3954#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
3955#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
3956#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
3957#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
3958#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
3959#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
3960#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
3961#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
3962#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
3963#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
3964#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
3965#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
3966#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
3967#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
3968#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
3969#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
3970#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
3971#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
3972#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
3973#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
3974#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
3975#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
3976#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
3977#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
3978#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
3979#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
3980#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
3981#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
3982#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
3983#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
3984#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
3985#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
3986#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
3987#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
3988#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
3989#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
3990#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
3991#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
3992#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
3993#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
3994#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
3995#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
3996#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
3997#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
3998#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
3999#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
4000#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)

4001#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
4002#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
4003#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
4004#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
4005#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
4006#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
4007#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
4008#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
4009#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
4010#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
4011#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
4012#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
4013#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
4014#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
4015#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
4016#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
4017#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
4018#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
4019#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
4020#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
4021#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
4022#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
4023#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
4024#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
4025#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
4026#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
4027#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
4028#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
4029#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
4030#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
4031#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
4032#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
4033#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
4034#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
4035#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
4036#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
4037#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
4038#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
4039#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
4040#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
4041#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
4042#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
4043#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
4044#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
4045#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
4046#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
4047#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
4048#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
4049#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
4050#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
4051#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
4052#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
4053#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
4054#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
4055#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
4056#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
4057#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
4058#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
4059#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
4060#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
4061#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
4062#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
4063#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
4064#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
4065#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
4066#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
4067#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
4068#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
4069#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
4070#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
4071#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
4072#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
4073#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
4074#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
4075#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
4076#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
4077#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
4078#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
4079#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
4080#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
4081#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
4082#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
4083#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
4084#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
4085#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
4086#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
4087#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
4088#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
4089#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
4090#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
4091#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
4092#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
4093#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
4094#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
4095#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
4096#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
4097#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
4098#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
4099#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
4100#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
4101#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
4102#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
4103#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
4104#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
4105#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
4106#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
4107#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
4108#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
4109#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
4110#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
4111#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
4112#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
4113#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
4114#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
4115#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
4116#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
4117#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
4118#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
4119#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
4120#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
4121#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
4122#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
4123#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
4124#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
4125#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
4126#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
4127#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
4128#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
4129#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
4130#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
4131#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
4132#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
4133#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
4134#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
4135#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
4136#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
4137#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
4138#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
4139#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
4140#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
4141#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
4142#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
4143#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
4144#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
4145#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
4146#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
4147#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
4148#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
4149#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
4150#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
4151#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
4152#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
4153#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
4154#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
4155#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
4156#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
4157#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
4158#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
4159#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
4160#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
4161#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
4162#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
4163#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
4164#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
4165#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
4166#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
4167#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
4168#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
4169#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
4170#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
4171#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
4172#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
4173#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
4174#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
4175#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
4176#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
4177#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
4178#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
4179#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
4180#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
4181#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
4182#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
4183#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
4184#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
4185#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
4186#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
4187#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
4188#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
4189#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
4190#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
4191#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
4192#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
4193#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
4194#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
4195#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
4196#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
4197#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
4198#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
4199#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
4200#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
4201#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
4202#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
4203#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
4204#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
4205#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
4206#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
4207#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
4208#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
4209#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
4210#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
4211#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
4212#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
4213#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
4214#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
4215#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
4216#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
4217#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
4218#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
4219#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
4220#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
4221#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
4222#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
4223#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
4224#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
4225#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
4226#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
4227#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
4228#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
4229#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
4230#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
4231#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
4232#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
4233#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
4234#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
4235#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
4236#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
4237#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
4238#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
4239#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
4240#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
4241#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
4242#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
4243#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
4244#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
4245#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
4246#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
4247#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
4248#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
4249#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
4250#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
4251#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
4252#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
4253#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
4254#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
4255#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
4256#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
4257#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
4258#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
4259#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
4260#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
4261#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
4262#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
4263#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
4264#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
4265#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
4266#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
4267#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
4268#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
4269#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
4270#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
4271#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
4272#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
4273#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
4274#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
4275#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
4276#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
4277#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
4278#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
4279#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
4280#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
4281#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
4282#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
4283#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
4284#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
4285#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
4286#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
4287#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
4288#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
4289#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
4290#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
4291#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
4292#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
4293#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
4294#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
4295#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
4296#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
4297#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
4298#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
4299#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
4300#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
4301#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
4302#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
4303#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
4304#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
4305#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
4306#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
4307#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
4308#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
4309#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
4310#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
4311#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
4312#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
4313#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
4314#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
4315#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
4316#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
4317#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
4318#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
4319#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
4320#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
4321#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
4322#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
4323#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
4324#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
4325#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
4326#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
4327#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
4328#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
4329#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
4330#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
4331#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
4332#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
4333#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
4334#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
4335#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
4336#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
4337#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
4338#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
4339#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
4340#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
4341#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
4342#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
4343#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
4344#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
4345#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
4346#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
4347#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
4348#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
4349#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
4350#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
4351#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
4352#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
4353#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
4354#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
4355#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
4356#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
4357#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
4358#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
4359#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
4360#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
4361#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
4362#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
4363#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
4364#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
4365#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
4366#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
4367#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
4368#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
4369#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
4370#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
4371#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
4372#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
4373#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
4374#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
4375#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
4376#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
4377#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
4378#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
4379#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
4380#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
4381#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
4382#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
4383#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
4384#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
4385#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
4386#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
4387#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
4388#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
4389#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
4390#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
4391#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
4392#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
4393#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
4394#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
4395#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
4396#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
4397#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
4398#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
4399#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
4400#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
4401#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
4402#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
4403#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
4404#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
4405#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
4406#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
4407#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
4408#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
4409#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
4410#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
4411#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
4412#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
4413#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
4414#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
4415#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
4416#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
4417#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
4418#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
4419#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
4420#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
4421#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
4422#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
4423#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
4424#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
4425#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
4426#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
4427#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
4428#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
4429#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
4430#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
4431#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
4432#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
4433#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
4434#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
4435#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
4436#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
4437#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
4438#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
4439#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
4440#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
4441#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
4442#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
4443#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
4444#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
4445#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
4446#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
4447#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
4448#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
4449#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
4450#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
4451#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
4452#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
4453#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
4454#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
4455#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
4456#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
4457#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
4458#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
4459#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
4460#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
4461#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
4462#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
4463#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
4464#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
4465#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
4466#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
4467#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
4468#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
4469#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
4470#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
4471#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
4472#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
4473#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
4474#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
4475#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
4476#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
4477#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
4478#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
4479#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
4480#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
4481#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
4482#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
4483#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
4484#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
4485#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
4486#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
4487#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
4488#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
4489#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
4490#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
4491#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
4492#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
4493#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
4494#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
4495#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
4496#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
4497#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
4498#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
4499#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
4500#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
4501#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
4502#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
4503#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
4504#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
4505#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
4506#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
4507#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
4508#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
4509#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
4510#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
4511#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
4512#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
4513#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
4514#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
4515#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
4516#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
4517#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
4518#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
4519#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
4520#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
4521#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
4522#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
4523#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
4524#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
4525#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
4526#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
4527#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
4528#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
4529#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
4530#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
4531#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
4532#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
4533#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
4534#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
4535#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
4536#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
4537#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
4538#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
4539#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
4540#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
4541#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
4542#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
4543#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
4544#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
4545#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
4546#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
4547#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
4548#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
4549#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
4550#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
4551#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
4552#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
4553#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
4554#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
4555#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
4556#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
4557#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
4558#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
4559#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
4560#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
4561#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
4562#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
4563#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
4564#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
4565#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
4566#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
4567#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
4568#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
4569#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
4570#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
4571#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
4572#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
4573#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
4574#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
4575#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
4576#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
4577#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
4578#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
4579#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
4580#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
4581#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
4582#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
4583#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
4584#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
4585#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
4586#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
4587#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
4588#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
4589#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
4590#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
4591#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
4592#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
4593#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
4594#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
4595#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
4596#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
4597#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
4598#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
4599#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
4600#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
4601#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
4602#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
4603#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
4604#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
4605#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
4606#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
4607#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
4608#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
4609#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
4610#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
4611#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
4612#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
4613#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
4614#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
4615#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
4616#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
4617#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
4618#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
4619#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
4620#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
4621#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
4622#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
4623#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
4624#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
4625#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
4626#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
4627#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
4628#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
4629#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
4630#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
4631#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
4632#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
4633#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
4634#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
4635#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
4636#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
4637#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
4638#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
4639#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
4640#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
4641#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
4642#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
4643#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
4644#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
4645#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
4646#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
4647#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
4648#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
4649#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
4650#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
4651#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
4652#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
4653#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
4654#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
4655#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
4656#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
4657#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
4658#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
4659#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
4660#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
4661#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
4662#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
4663#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
4664#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
4665#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
4666#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
4667#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
4668#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
4669#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
4670#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
4671#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
4672#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
4673#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
4674#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
4675#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
4676#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
4677#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
4678#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
4679#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
4680#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
4681#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
4682#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
4683#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
4684#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
4685#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
4686#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
4687#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
4688#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
4689#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
4690#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
4691#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
4692#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
4693#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
4694#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
4695#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
4696#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
4697#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
4698#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
4699#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
4700#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
4701#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
4702#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
4703#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
4704#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
4705#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
4706#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
4707#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
4708#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
4709#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
4710#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
4711#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
4712#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
4713#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
4714#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
4715#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
4716#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
4717#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
4718#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
4719#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
4720#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
4721#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
4722#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
4723#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
4724#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
4725#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
4726#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
4727#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
4728#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
4729#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
4730#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
4731#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
4732#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
4733#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
4734#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
4735#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
4736#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
4737#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
4738#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
4739#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
4740#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
4741#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
4742#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
4743#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
4744#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
4745#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
4746#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
4747#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
4748#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
4749#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
4750#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
4751#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
4752#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
4753#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
4754#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
4755#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
4756#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
4757#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
4758#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
4759#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
4760#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
4761#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
4762#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
4763#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
4764#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
4765#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
4766#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
4767#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
4768#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
4769#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
4770#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
4771#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
4772#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
4773#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
4774#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
4775#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
4776#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
4777#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
4778#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
4779#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
4780#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
4781#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
4782#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
4783#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
4784#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
4785#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
4786#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
4787#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
4788#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
4789#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
4790#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
4791#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
4792#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
4793#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
4794#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
4795#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
4796#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
4797#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
4798#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
4799#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
4800#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
4801#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
4802#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
4803#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
4804#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
4805#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
4806#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
4807#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
4808#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
4809#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
4810#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
4811#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
4812#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
4813#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
4814#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
4815#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
4816#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
4817#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
4818#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
4819#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
4820#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
4821#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
4822#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
4823#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
4824#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
4825#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
4826#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
4827#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
4828#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
4829#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
4830#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
4831#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
4832#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
4833#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
4834#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
4835#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
4836#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
4837#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
4838#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
4839#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
4840#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
4841#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
4842#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
4843#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
4844#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
4845#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
4846#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
4847#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
4848#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
4849#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
4850#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
4851#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
4852#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
4853#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
4854#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
4855#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
4856#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
4857#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
4858#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
4859#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
4860#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
4861#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
4862#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
4863#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
4864#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
4865#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
4866#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
4867#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
4868#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
4869#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
4870#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
4871#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
4872#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
4873#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
4874#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
4875#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
4876#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
4877#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
4878#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
4879#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
4880#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
4881#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
4882#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
4883#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
4884#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
4885#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
4886#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
4887#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
4888#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
4889#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
4890#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
4891#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
4892#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
4893#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
4894#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
4895#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
4896#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
4897#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
4898#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
4899#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
4900#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
4901#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
4902#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
4903#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
4904#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
4905#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
4906#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
4907#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
4908#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
4909#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
4910#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
4911#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
4912#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
4913#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
4914#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
4915#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
4916#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
4917#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
4918#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
4919#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
4920#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
4921#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
4922#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
4923#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
4924#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
4925#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
4926#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
4927#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
4928#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
4929#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
4930#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
4931#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
4932#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
4933#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
4934#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
4935#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
4936#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
4937#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
4938#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
4939#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
4940#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
4941#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
4942#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
4943#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
4944#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
4945#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
4946#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
4947#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
4948#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
4949#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
4950#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
4951#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
4952#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
4953#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
4954#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
4955#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
4956#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
4957#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
4958#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
4959#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
4960#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
4961#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
4962#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
4963#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
4964#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
4965#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
4966#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
4967#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
4968#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
4969#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
4970#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
4971
4972#endif /* __BFIN_CDEF_ADSP_EDN_BF544_extended__ */
4973