LXR uboot/include/configs/AR405.h

   1/*
   2 * (C) Copyright 2001-2004
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * board/config.h - configuration options, board specific
  26 */
  27
  28#ifndef __CONFIG_H
  29#define __CONFIG_H
  30
  31/*
  32 * High Level Configuration Options
  33 * (easy to change)
  34 */
  35
  36#define CONFIG_405GP            1       /* This is a PPC405GP CPU       */
  37#define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38#define CONFIG_AR405            1       /* ...on a AR405 board          */
  39
  40#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41
  42#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  43
  44#define CONFIG_BOARD_TYPES      1       /* support board types          */
  45
  46#define CONFIG_BAUDRATE         9600
  47#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  48
  49#if 1
  50#define CONFIG_BOOTCOMMAND      "bootm fff00000" /* autoboot command    */
  51#else
  52#define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  53#endif
  54
  55#if 0
  56#define CONFIG_BOOTARGS         "root=/dev/nfs "                        \
  57    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "        \
  58    "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
  59#else
  60#define CONFIG_BOOTARGS         "root=/dev/hda1 "                       \
  61    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
  62
  63#endif
  64
  65#define CONFIG_PREBOOT                  /* enable preboot variable      */
  66
  67#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  68#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  69
  70#define CONFIG_PPC4xx_EMAC
  71#define CONFIG_MII              1       /* MII PHY management           */
  72#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  73#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  74#define CONFIG_NET_MULTI
  75
  76
  77/*
  78 * BOOTP options
  79 */
  80#define CONFIG_BOOTP_BOOTFILESIZE
  81#define CONFIG_BOOTP_BOOTPATH
  82#define CONFIG_BOOTP_GATEWAY
  83#define CONFIG_BOOTP_HOSTNAME
  84
  85
  86/*
  87 * Command line configuration.
  88 */
  89#include <config_cmd_default.h>
  90
  91#define CONFIG_CMD_DHCP
  92#define CONFIG_CMD_PCI
  93#define CONFIG_CMD_IRQ
  94#define CONFIG_CMD_ELF
  95#define CONFIG_CMD_MII
  96#define CONFIG_CMD_PING
  97#define CONFIG_CMD_BSP
  98
  99
 100#undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 101
 102#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 103
 104/*
 105 * Miscellaneous configurable options
 106 */
 107#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 108#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 109#if defined(CONFIG_CMD_KGDB)
 110#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 111#else
 112#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 113#endif
 114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 115#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 116#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 117
 118#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 119
 120#define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 121
 122#define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 123#define CONFIG_LOOPW            1       /* enable loopw command         */
 124#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 125
 126#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 127#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 128
 129#define CONFIG_SYS_EXT_SERIAL_CLOCK     14745600 /* use external serial clock   */
 130
 131/* The following table includes the supported baudrates */
 132#define CONFIG_SYS_BAUDRATE_TABLE       \
 133        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 134         57600, 115200, 230400, 460800, 921600 }
 135
 136#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 137#define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 138
 139#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 140
 141#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 142
 143/*-----------------------------------------------------------------------
 144 * PCI stuff
 145 *-----------------------------------------------------------------------
 146 */
 147#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 148#define PCI_HOST_FORCE  1               /* configure as pci host        */
 149#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 150
 151#define CONFIG_PCI                      /* include pci support          */
 152#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 153#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 154                                        /* resource configuration       */
 155
 156#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 157
 158#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 159
 160#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 161
 162#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 163#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403   /* PCI Device ID: ARISTO405     */
 164#define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 165#define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 166#define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 167#define CONFIG_SYS_PCI_PTM2LA   0xfff00000      /* point to flash               */
 168#define CONFIG_SYS_PCI_PTM2MS   0xfff00001      /* 1MB, enable                  */
 169#define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 170
 171/*-----------------------------------------------------------------------
 172 * Start addresses for the final memory configuration
 173 * (Set up by the startup code)
 174 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 175 */
 176#define CONFIG_SYS_SDRAM_BASE           0x00000000
 177#define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 178#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 179#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 180#define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 181
 182/*
 183 * For booting Linux, the board info and command line data
 184 * have to be in the first 8 MB of memory, since this is
 185 * the maximum mapped by the Linux kernel during initialization.
 186 */
 187#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 188/*-----------------------------------------------------------------------
 189 * FLASH organization
 190 */
 191#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 192#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 193
 194#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 195#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 196
 197#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 198#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 199#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 200/*
 201 * The following defines are added for buggy IOP480 byte interface.
 202 * All other boards should use the standard values (CPCI405 etc.)
 203 */
 204#define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 205#define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 206#define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 207
 208#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 209
 210#define CONFIG_ENV_IS_IN_FLASH  1
 211#define CONFIG_ENV_ADDR         0xFFFB0000      /* Address of Environment Sector*/
 212#define CONFIG_ENV_SECT_SIZE    0x10000 /* see README - env sector total size   */
 213#define CONFIG_ENV_SIZE         0x04000         /* Size of Environment          */
 214
 215#define CONFIG_ENV_ADDR_REDUND     0xFFFA0000
 216#define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 217
 218/*
 219 * Init Memory Controller:
 220 *
 221 * BR0/1 and OR0/1 (FLASH)
 222 */
 223
 224#define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 225
 226/*-----------------------------------------------------------------------
 227 * External Bus Controller (EBC) Setup
 228 */
 229
 230/* Memory Bank 0 (Flash Bank 0) initialization                                  */
 231#define CONFIG_SYS_EBC_PB0AP            0x92015480
 232#define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 233
 234/* Memory Bank 1 (CAN0, 1, 2, 3) initialization                                 */
 235#define CONFIG_SYS_EBC_PB1AP            0x01000380  /* enable Ready, BEM=0              */
 236#define CONFIG_SYS_EBC_PB1CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 237
 238/* Memory Bank 2 (Expension Bus) initialization                                 */
 239#define CONFIG_SYS_EBC_PB2AP            0x01000280  /* disable Ready, BEM=0             */
 240#define CONFIG_SYS_EBC_PB2CR            0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
 241
 242/* Memory Bank 3 (16552) initialization                                         */
 243#define CONFIG_SYS_EBC_PB3AP            0x01000380  /* enable Ready, BEM=0              */
 244#define CONFIG_SYS_EBC_PB3CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 245
 246/* Memory Bank 4 (FPGA regs) initialization                                     */
 247#define CONFIG_SYS_EBC_PB4AP            0x01005380  /* enable Ready, BEM=0              */
 248#define CONFIG_SYS_EBC_PB4CR            0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
 249
 250/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization                            */
 251#define CONFIG_SYS_EBC_PB5AP            0x92015480
 252#define CONFIG_SYS_EBC_PB5CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 253
 254/*-----------------------------------------------------------------------
 255 * Definitions for initial stack pointer and data area (in data cache)
 256 */
 257#define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 258
 259#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 260#define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in RAM             */
 261#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 262#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 263#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 264
 265/*
 266 * Internal Definitions
 267 *
 268 * Boot Flags
 269 */
 270#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 271#define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 272
 273#endif  /* __CONFIG_H */
 274