1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * configuration options, board specific, for Siemens Card Controller Module 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#undef CCM_80MHz /* define for 80 MHz CPU only */ 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ 39#define CONFIG_CCM 1 /* on a Card Controller Module */ 40#define CONFIG_MISC_INIT_R /* Call misc_init_r() */ 41#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 42 43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 44#undef CONFIG_8xx_CONS_SMC2 45#undef CONFIG_8xx_CONS_NONE 46 47/* ENVIRONMENT */ 48 49#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */ 50#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 51 52#define CONFIG_IPADDR 192.168.0.42 53#define CONFIG_NETMASK 255.255.255.0 54#define CONFIG_GATEWAYIP 0.0.0.0 55#define CONFIG_SERVERIP 192.168.0.254 56 57#define CONFIG_HOSTNAME CCM 58 59#define CONFIG_LOADADDR 40180000 60 61#undef CONFIG_BOOTARGS 62 63#define CONFIG_BOOTCOMMAND "setenv bootargs " \ 64 "mem=${mem} " \ 65 "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 66 "wt_8xx=timeout:3600; " \ 67 "bootm" 68 69#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 70#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 71 72#define CONFIG_WATCHDOG 1 /* watchdog enabled */ 73 74#undef CONFIG_STATUS_LED /* Status LED disabled */ 75 76#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/ 77 78#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 79 80#define CONFIG_SPI /* enable SPI driver */ 81#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ 82 83/* ---------------------------------------------------------------- 84 * Offset to initial SPI buffers in DPRAM (used if the environment 85 * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to 86 * use at an early stage. It is used between the two initialization 87 * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it 88 * far enough from the start of the data area (as well as from the 89 * stack pointer). 90 * ---------------------------------------------------------------- */ 91#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 92 93#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */ 94 95 96#define CONFIG_MAC_PARTITION /* nod used yet */ 97#define CONFIG_DOS_PARTITION 98 99/* 100 * BOOTP options 101 */ 102#define CONFIG_BOOTP_SUBNETMASK 103#define CONFIG_BOOTP_GATEWAY 104#define CONFIG_BOOTP_HOSTNAME 105#define CONFIG_BOOTP_BOOTPATH 106#define CONFIG_BOOTP_BOOTFILESIZE 107 108 109/* 110 * Command line configuration. 111 */ 112#include <config_cmd_default.h> 113 114#define CONFIG_CMD_BSP 115#define CONFIG_CMD_DHCP 116#define CONFIG_CMD_DATE 117#define CONFIG_CMD_EEPROM 118#define CONFIG_CMD_NFS 119#define CONFIG_CMD_SNTP 120 121 122/* 123 * Miscellaneous configurable options 124 */ 125#define CONFIG_SYS_LONGHELP /* undef to save memory */ 126#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 127#if defined(CONFIG_CMD_KGDB) 128#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 129#else 130#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 131#endif 132#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 133#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 135 136#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 137#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ 138 139#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 140 141/* Ethernet hardware configuration done using port pins */ 142#define CONFIG_SYS_PA_ETH_RESET 0x0200 /* PA 6 */ 143#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */ 144#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ 145#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */ 146#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */ 147#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */ 148 149/* Ethernet settings: 150 * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex 151 */ 152#define CONFIG_SYS_ETH_MDDIS_VALUE 0 153#define CONFIG_SYS_ETH_CFG1_VALUE 1 154#define CONFIG_SYS_ETH_CFG2_VALUE 1 155#define CONFIG_SYS_ETH_CFG3_VALUE 1 156 157/* PUMA configuration */ 158#define CONFIG_SYS_PC_PUMA_PROG 0x0200 /* PC 6 */ 159#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */ 160#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */ 161 162#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 163 164#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 165 166/* 167 * Low Level Configuration Settings 168 * (address mappings, register initial values, etc.) 169 * You should know what you are doing if you make changes here. 170 */ 171/*----------------------------------------------------------------------- 172 * Internal Memory Mapped Register 173 */ 174#define CONFIG_SYS_IMMR 0xF0000000 175 176/*----------------------------------------------------------------------- 177 * Definitions for initial stack pointer and data area (in DPRAM) 178 */ 179#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 180#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 181#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 182#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 183#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 184 185/*----------------------------------------------------------------------- 186 * Address accessed to reset the board - must not be mapped/assigned 187 */ 188#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF 189 190/*----------------------------------------------------------------------- 191 * Start addresses for the final memory configuration 192 * (Set up by the startup code) 193 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 194 */ 195#define CONFIG_SYS_SDRAM_BASE 0x00000000 196#define CONFIG_SYS_FLASH_BASE 0x40000000 197#if defined(DEBUG) 198#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 199#else 200#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 201#endif 202#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 203#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 204 205/* 206 * For booting Linux, the board info and command line data 207 * have to be in the first 8 MB of memory, since this is 208 * the maximum mapped by the Linux kernel during initialization. 209 */ 210#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 211 212/*----------------------------------------------------------------------- 213 * FLASH organization 214 */ 215#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 216#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 217 218#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 219#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 220 221#if 1 222/* Start port with environment in flash; switch to SPI EEPROM later */ 223#define CONFIG_ENV_IS_IN_FLASH 1 224#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 225#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 226 227/* Address and size of Redundant Environment Sector */ 228#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 229#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 230#else 231/* Final version: environment in EEPROM */ 232#define CONFIG_ENV_IS_IN_EEPROM 1 233#define CONFIG_ENV_OFFSET 2048 234#define CONFIG_ENV_SIZE 2048 235#endif 236 237/*----------------------------------------------------------------------- 238 * Hardware Information Block 239 */ 240#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 241#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 242#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 243 244/*----------------------------------------------------------------------- 245 * Cache Configuration 246 */ 247#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 248#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 249 250/*----------------------------------------------------------------------- 251 * SYPCR - System Protection Control 11-9 252 * SYPCR can only be written once after reset! 253 *----------------------------------------------------------------------- 254 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 255 */ 256#if defined(CONFIG_WATCHDOG) 257#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 258 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 259#else 260#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 261 SYPCR_SWP) 262#endif 263 264/*----------------------------------------------------------------------- 265 * SIUMCR - SIU Module Configuration 11-6 266 *----------------------------------------------------------------------- 267 * we must activate GPL5 in the SIUMCR for CAN 268 */ 269#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 270 271/*----------------------------------------------------------------------- 272 * TBSCR - Time Base Status and Control 11-26 273 *----------------------------------------------------------------------- 274 * Clear Reference Interrupt Status, Timebase freezing enabled 275 */ 276#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 277 278/*----------------------------------------------------------------------- 279 * RTCSC - Real-Time Clock Status and Control Register 11-27 280 *----------------------------------------------------------------------- 281 */ 282#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 283 284/*----------------------------------------------------------------------- 285 * PISCR - Periodic Interrupt Status and Control 11-31 286 *----------------------------------------------------------------------- 287 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 288 */ 289#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 290 291/*----------------------------------------------------------------------- 292 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 293 *----------------------------------------------------------------------- 294 * Reset PLL lock status sticky bit, timer expired status bit and timer 295 * interrupt status bit 296 * 297 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! 298 */ 299#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ 300#define CONFIG_SYS_PLPRCR \ 301 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) 302#else /* up to 50 MHz we use a 1:1 clock */ 303#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 304#endif /* CCM_80MHz */ 305 306/*----------------------------------------------------------------------- 307 * SCCR - System Clock and reset Control Register 15-27 308 *----------------------------------------------------------------------- 309 * Set clock output, timebase and RTC source and divider, 310 * power management and some other internal clocks 311 */ 312#define SCCR_MASK SCCR_EBDF11 313#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ 314#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \ 315 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 316 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 317 SCCR_DFALCD00) 318#else /* up to 50 MHz we use a 1:1 clock */ 319#define CONFIG_SYS_SCCR (SCCR_TBS | \ 320 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 321 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 322 SCCR_DFALCD00) 323#endif /* CCM_80MHz */ 324 325/*----------------------------------------------------------------------- 326 * 327 * Interrupt Levels 328 *----------------------------------------------------------------------- 329 */ 330#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ 331 332/*----------------------------------------------------------------------- 333 * 334 *----------------------------------------------------------------------- 335 * 336 */ 337#define CONFIG_SYS_DER 0 338 339/* 340 * Init Memory Controller: 341 * 342 * BR0/1 and OR0/1 (FLASH) 343 */ 344 345#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 346#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 347 348/* used to re-map FLASH both when starting from SRAM or FLASH: 349 * restrict access enough to keep SRAM working (if any) 350 * but not too much to meddle with FLASH accesses 351 */ 352#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 353#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 354 355/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 356#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ 357 OR_SCY_5_CLK | OR_EHTR) 358 359#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 360#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 361#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 362 363#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 364#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 365#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 366 367/* 368 * BR2 and OR2 (SDRAM) 369 * 370 */ 371#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 372#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 373#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 374 375/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 376#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 377 378#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 379#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 380 381/* 382 * BR3 and OR3 (CAN Controller) 383 */ 384#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 385#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 386#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 387#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 388 BR_PS_8 | BR_MS_UPMB | BR_V ) 389 390/* 391 * BR4/OR4: PUMA Config 392 * 393 * Memory controller will be used in 2 modes: 394 * 395 * - "read" mode: 396 * BR4: 0x10100801 OR4: 0xffff8520 397 * - "load" mode (chip select on UPM B): 398 * BR4: 0x101004c1 OR4: 0xffff8600 399 * 400 * Default initialization is in "read" mode 401 */ 402#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ 403#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ 404#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK) 405#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK) 406 407#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ 408 BR_PS_8 | BR_MS_UPMB | BR_V) 409#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) 410 411#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) 412#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) 413 414#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ 415#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ 416 417/* 418 * BR5/OR5: PUMA: SMA Bus 8 Bit 419 * BR5: 0x10200401 OR5: 0xffe0010a 420 */ 421#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ 422#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ 423#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) 424 425#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) 426#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) 427 428/* 429 * BR6/OR6: PUMA: SMA Bus 16 Bit 430 * BR6: 0x10600801 OR6: 0xffe0010a 431 */ 432#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ 433#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ 434#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) 435 436#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) 437#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) 438 439/* 440 * BR7/OR7: PUMA: external Flash 441 * BR7: 0x10a00801 OR7: 0xfe00010a 442 */ 443#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ 444#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ 445#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) 446 447#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) 448#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) 449 450 451/* 452 * Memory Periodic Timer Prescaler 453 */ 454 455/* periodic timer for refresh */ 456#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 457 458/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 459#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 460#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 461 462/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 463#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 464#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 465 466/* 467 * MAMR settings for SDRAM 468 */ 469 470/* 8 column SDRAM */ 471#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 472 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 474/* 9 column SDRAM */ 475#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 476 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 477 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 478 479 480/* 481 * Internal Definitions 482 * 483 * Boot Flags 484 */ 485#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 486#define BOOTFLAG_WARM 0x02 /* Software reboot */ 487 488#endif /* __CONFIG_H */ 489