1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * 26 * Configuration settings for the CPC45 board. 27 * 28 */ 29 30/* ------------------------------------------------------------------------- */ 31 32/* 33 * board/config.h - configuration options, board specific 34 */ 35 36#ifndef __CONFIG_H 37#define __CONFIG_H 38 39/* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43 44#define CONFIG_MPC824X 1 45#define CONFIG_MPC8245 1 46#define CONFIG_CPC45 1 47 48 49#define CONFIG_CONS_INDEX 1 50#define CONFIG_BAUDRATE 9600 51#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 52 53#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 54 55#define CONFIG_BOOTDELAY 5 56 57/* 58 * BOOTP options 59 */ 60#define CONFIG_BOOTP_SUBNETMASK 61#define CONFIG_BOOTP_GATEWAY 62#define CONFIG_BOOTP_HOSTNAME 63#define CONFIG_BOOTP_BOOTPATH 64 65#define CONFIG_BOOTP_BOOTFILESIZE 66 67 68/* 69 * Command line configuration. 70 */ 71#include <config_cmd_default.h> 72 73#define CONFIG_CMD_BEDBUG 74#define CONFIG_CMD_DATE 75#define CONFIG_CMD_DHCP 76#define CONFIG_CMD_EEPROM 77#define CONFIG_CMD_EXT2 78#define CONFIG_CMD_FAT 79#define CONFIG_CMD_FLASH 80#define CONFIG_CMD_I2C 81#define CONFIG_CMD_IDE 82#define CONFIG_CMD_NFS 83#define CONFIG_CMD_PCI 84#define CONFIG_CMD_PING 85#define CONFIG_CMD_SDRAM 86#define CONFIG_CMD_SNTP 87 88 89/* 90 * Miscellaneous configurable options 91 */ 92#define CONFIG_SYS_LONGHELP /* undef to save memory */ 93#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 94#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 95 96#if 1 97#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 98#endif 99#ifdef CONFIG_SYS_HUSH_PARSER 100#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 101#endif 102 103/* Print Buffer Size 104 */ 105#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 106 107#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 108#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 109#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ 110 111/*----------------------------------------------------------------------- 112 * Start addresses for the final memory configuration 113 * (Set up by the startup code) 114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 115 */ 116 117#define CONFIG_SYS_SDRAM_BASE 0x00000000 118 119#if defined(CONFIG_BOOT_ROM) 120#define CONFIG_SYS_FLASH_BASE 0xFF000000 121#else 122#define CONFIG_SYS_FLASH_BASE 0xFF800000 123#endif 124 125#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 126 127#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 128 129#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 130 131#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 132#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 133 134#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 135#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 136 137/* Maximum amount of RAM. 138 */ 139#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 140 141 142#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE 143#undef CONFIG_SYS_RAMBOOT 144#else 145#define CONFIG_SYS_RAMBOOT 146#endif 147 148 149/*----------------------------------------------------------------------- 150 * Definitions for initial stack pointer and data area 151 */ 152 153/* Size in bytes reserved for initial data 154 */ 155#define CONFIG_SYS_GBL_DATA_SIZE 128 156 157#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 158#define CONFIG_SYS_INIT_RAM_END 0x1000 159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 160 161/* 162 * NS16550 Configuration 163 */ 164#define CONFIG_SYS_NS16550 165#define CONFIG_SYS_NS16550_SERIAL 166 167#define CONFIG_SYS_NS16550_REG_SIZE 1 168 169#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 170 171#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) 172#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) 173#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511) 174 175/* 176 * I2C configuration 177 */ 178#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 179 180#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 181#define CONFIG_SYS_I2C_SLAVE 0x7F 182 183/* 184 * RTC configuration 185 */ 186#define CONFIG_RTC_PCF8563 187#define CONFIG_SYS_I2C_RTC_ADDR 0x51 188 189/* 190 * EEPROM configuration 191 */ 192#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 193#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 194#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 195#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 196#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 197 198/* 199 * Low Level Configuration Settings 200 * (address mappings, register initial values, etc.) 201 * You should know what you are doing if you make changes here. 202 * For the detail description refer to the MPC8240 user's manual. 203 */ 204 205#define CONFIG_SYS_CLK_FREQ 33000000 206#define CONFIG_SYS_HZ 1000 207 208 209/* Bit-field values for MCCR1. 210 */ 211#define CONFIG_SYS_ROMNAL 0 212#define CONFIG_SYS_ROMFAL 8 213 214#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ 215#define CONFIG_SYS_BANK1_ROW 0 216#define CONFIG_SYS_BANK2_ROW 0 217#define CONFIG_SYS_BANK3_ROW 0 218#define CONFIG_SYS_BANK4_ROW 0 219#define CONFIG_SYS_BANK5_ROW 0 220#define CONFIG_SYS_BANK6_ROW 0 221#define CONFIG_SYS_BANK7_ROW 0 222 223/* Bit-field values for MCCR2. 224 */ 225 226#define CONFIG_SYS_REFINT 0x2ec 227 228/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. 229 */ 230#define CONFIG_SYS_BSTOPRE 160 231 232/* Bit-field values for MCCR3. 233 */ 234#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ 235#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */ 236 237/* Bit-field values for MCCR4. 238 */ 239#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */ 240#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */ 241#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ 242#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 243#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ 244#define CONFIG_SYS_ACTORW 2 245#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 246#define CONFIG_SYS_EXTROM 0 247#define CONFIG_SYS_REGDIMM 0 248 249/* Memory bank settings. 250 * Only bits 20-29 are actually used from these vales to set the 251 * start/end addresses. The upper two bits will always be 0, and the lower 252 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end 253 * address. Refer to the MPC8240 book. 254 */ 255 256#define CONFIG_SYS_BANK0_START 0x00000000 257#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 258#define CONFIG_SYS_BANK0_ENABLE 1 259#define CONFIG_SYS_BANK1_START 0x3ff00000 260#define CONFIG_SYS_BANK1_END 0x3fffffff 261#define CONFIG_SYS_BANK1_ENABLE 0 262#define CONFIG_SYS_BANK2_START 0x3ff00000 263#define CONFIG_SYS_BANK2_END 0x3fffffff 264#define CONFIG_SYS_BANK2_ENABLE 0 265#define CONFIG_SYS_BANK3_START 0x3ff00000 266#define CONFIG_SYS_BANK3_END 0x3fffffff 267#define CONFIG_SYS_BANK3_ENABLE 0 268#define CONFIG_SYS_BANK4_START 0x3ff00000 269#define CONFIG_SYS_BANK4_END 0x3fffffff 270#define CONFIG_SYS_BANK4_ENABLE 0 271#define CONFIG_SYS_BANK5_START 0x3ff00000 272#define CONFIG_SYS_BANK5_END 0x3fffffff 273#define CONFIG_SYS_BANK5_ENABLE 0 274#define CONFIG_SYS_BANK6_START 0x3ff00000 275#define CONFIG_SYS_BANK6_END 0x3fffffff 276#define CONFIG_SYS_BANK6_ENABLE 0 277#define CONFIG_SYS_BANK7_START 0x3ff00000 278#define CONFIG_SYS_BANK7_END 0x3fffffff 279#define CONFIG_SYS_BANK7_ENABLE 0 280 281#define CONFIG_SYS_ODCR 0xff 282#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ 283 /* currently accessed page in memory */ 284 /* see 8240 book for details */ 285 286#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 287#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 288 289#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 290#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 291 292#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 293#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 294 295#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 296#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) 297 298#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 299#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 300#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 301#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 302#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 303#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 304#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 305#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 306 307/* 308 * For booting Linux, the board info and command line data 309 * have to be in the first 8 MB of memory, since this is 310 * the maximum mapped by the Linux kernel during initialization. 311 */ 312#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 313 314/*----------------------------------------------------------------------- 315 * FLASH organization 316 */ 317#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 318#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ 319#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ 320#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 321#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 322 323 /* Warining: environment is not EMBEDDED in the ppcboot code. 324 * It's stored in flash separately. 325 */ 326#define CONFIG_ENV_IS_IN_FLASH 1 327 328#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000) 329#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */ 330#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */ 331#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ 332 333/*----------------------------------------------------------------------- 334 * Cache Configuration 335 */ 336#define CONFIG_SYS_CACHELINE_SIZE 32 337#if defined(CONFIG_CMD_KGDB) 338# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 339#endif 340 341/* 342 * Internal Definitions 343 * 344 * Boot Flags 345 */ 346#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 347#define BOOTFLAG_WARM 0x02 /* Software reboot */ 348 349 350#define SRAM_BASE 0x80000000 /* SRAM base address */ 351#define SRAM_END 0x801FFFFF 352 353/*----------------------------------------------------------------------*/ 354/* CPC45 Memory Map */ 355/*----------------------------------------------------------------------*/ 356#define SRAM_BASE 0x80000000 /* SRAM base address */ 357#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ 358#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ 359#define BCSR_BASE 0x80600000 /* board control / status registers */ 360#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ 361#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ 362#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ 363 364 365/*---------------------------------------------------------------------*/ 366/* CPC45 Control/Status Registers */ 367/*---------------------------------------------------------------------*/ 368#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) 369#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) 370#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) 371#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) 372#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) 373#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) 374#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) 375#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) 376#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) 377#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) 378 379/* IRQ_ENA_1 bit definitions */ 380#define I_ENA_1_IERA 0x80 /* INTA enable */ 381#define I_ENA_1_IERB 0x40 /* INTB enable */ 382#define I_ENA_1_IERC 0x20 /* INTC enable */ 383#define I_ENA_1_IERD 0x10 /* INTD enable */ 384 385/* IRQ_STAT_1 bit definitions */ 386#define I_STAT_1_INTA 0x80 /* INTA status */ 387#define I_STAT_1_INTB 0x40 /* INTB status */ 388#define I_STAT_1_INTC 0x20 /* INTC status */ 389#define I_STAT_1_INTD 0x10 /* INTD status */ 390 391/* IRQ_ENA_2 bit definitions */ 392#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ 393#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ 394#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ 395#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ 396#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ 397#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ 398#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ 399#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ 400 401/* IRQ_STAT_2 bit definitions */ 402#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ 403#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ 404#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ 405#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ 406#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ 407#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ 408#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ 409#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ 410 411/* BOARD_CTRL bit definitions */ 412#define USER_LEDS 2 /* 2 user LEDs */ 413 414#if (USER_LEDS == 4) 415#define B_CTRL_WRSE 0x80 416#define B_CTRL_KRSE 0x40 417#define B_CTRL_FWRE 0x20 /* Flash write enable */ 418#define B_CTRL_FWPT 0x10 /* Flash write protect */ 419#define B_CTRL_LED3 0x08 /* LED 3 control */ 420#define B_CTRL_LED2 0x04 /* LED 2 control */ 421#define B_CTRL_LED1 0x02 /* LED 1 control */ 422#define B_CTRL_LED0 0x01 /* LED 0 control */ 423#else 424#define B_CTRL_WRSE 0x80 425#define B_CTRL_KRSE 0x40 426#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ 427#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ 428#define B_CTRL_LED1 0x08 /* LED 1 control */ 429#define B_CTRL_LED0 0x04 /* LED 0 control */ 430#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ 431#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ 432#endif 433 434/* BOARD_STAT bit definitions */ 435#define B_STAT_WDGE 0x80 436#define B_STAT_WDGS 0x40 437#define B_STAT_WRST 0x20 438#define B_STAT_KRST 0x10 439#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ 440#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ 441#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ 442#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ 443 444/*---------------------------------------------------------------------*/ 445/* Display addresses */ 446/*---------------------------------------------------------------------*/ 447#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ 448#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ 449#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ 450 451#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ 452#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ 453 454#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ 455#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ 456#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ 457#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ 458#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ 459#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ 460#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ 461#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ 462 463 464/*----------------------------------------------------------------------- 465 * PCI stuff 466 *----------------------------------------------------------------------- 467 */ 468#define CONFIG_PCI /* include pci support */ 469#undef CONFIG_PCI_PNP 470#undef CONFIG_PCI_SCAN_SHOW 471 472#define CONFIG_NET_MULTI /* Multi ethernet cards support */ 473 474#define CONFIG_EEPRO100 475#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 476 477#define PCI_ENET0_IOADDR 0x82000000 478#define PCI_ENET0_MEMADDR 0x82000000 479#define PCI_PLX9030_IOADDR 0x82100000 480#define PCI_PLX9030_MEMADDR 0x82100000 481 482/*----------------------------------------------------------------------- 483 * PCMCIA stuff 484 *----------------------------------------------------------------------- 485 */ 486 487#define CONFIG_I82365 488 489#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE 490#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000 491 492#define CONFIG_PCMCIA_SLOT_A 493 494/*----------------------------------------------------------------------- 495 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 496 *----------------------------------------------------------------------- 497 */ 498 499#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 500 501#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 502#undef CONFIG_IDE_RESET /* reset for IDE not supported */ 503#define CONFIG_IDE_LED /* LED for IDE is supported */ 504 505#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 506#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 507 508#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 509 510#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 511 512#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE 513 514/* Offset for normal register accesses */ 515#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 516 517/* Offset for alternate registers */ 518#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400) 519 520#define CONFIG_DOS_PARTITION 521 522#endif /* __CONFIG_H */ 523