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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37
38
39
40
41
42#define CONFIG_405EP 1
43#define CONFIG_4xx 1
44#define CONFIG_HH405 1
45
46#define CONFIG_BOARD_EARLY_INIT_F 1
47#define CONFIG_MISC_INIT_R 1
48
49#define CONFIG_SYS_CLK_FREQ 33333400
50
51#define CONFIG_BOARD_TYPES 1
52
53#define CONFIG_BAUDRATE 9600
54#define CONFIG_BOOTDELAY 3
55
56#undef CONFIG_BOOTARGS
57#undef CONFIG_BOOTCOMMAND
58
59#define CONFIG_PREBOOT "autoupd"
60
61#define CONFIG_EXTRA_ENV_SETTINGS \
62 "pciconfighost=1\0" \
63 ""
64
65#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
66
67#define CONFIG_PPC4xx_EMAC
68#define CONFIG_NET_MULTI 1
69#undef CONFIG_HAS_ETH1
70
71#define CONFIG_MII 1
72#define CONFIG_PHY_ADDR 0
73#define CONFIG_LXT971_NO_SLEEP 1
74#define CONFIG_RESET_PHY_R 1
75
76#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
77
78
79
80
81#define CONFIG_VIDEO
82
83#ifdef CONFIG_VIDEO
84#define CONFIG_VIDEO_SM501
85#if 0
86#define CONFIG_VIDEO_SM501_32BPP
87#else
88#define CONFIG_VIDEO_SM501_16BPP
89#endif
90#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
91#define CONFIG_CFB_CONSOLE
92#define CONFIG_VIDEO_LOGO
93#define CONFIG_VGA_AS_SINGLE_DEVICE
94#define CONFIG_CONSOLE_EXTRA_INFO
95#define CONFIG_VIDEO_SW_CURSOR
96#define CONFIG_SPLASH_SCREEN
97#define CONFIG_SYS_CONSOLE_IS_IN_ENV
98#define CONFIG_SPLASH_SCREEN
99#define CONFIG_VIDEO_BMP_GZIP
100#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
101
102#endif
103
104
105
106
107
108#define CONFIG_BOOTP_BOOTFILESIZE
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
112
113
114
115
116
117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_PCI
121#define CONFIG_CMD_IRQ
122#define CONFIG_CMD_IDE
123#define CONFIG_CMD_FAT
124#define CONFIG_CMD_EXT2
125#define CONFIG_CMD_ELF
126#define CONFIG_CMD_NAND
127#define CONFIG_CMD_I2C
128#define CONFIG_CMD_DATE
129#define CONFIG_CMD_MII
130#define CONFIG_CMD_PING
131#define CONFIG_CMD_EEPROM
132
133#ifdef CONFIG_VIDEO
134#define CONFIG_CMD_BMP
135#endif
136
137#define CONFIG_MAC_PARTITION
138#define CONFIG_DOS_PARTITION
139
140#define CONFIG_SUPPORT_VFAT
141
142#define CONFIG_AUTO_UPDATE 1
143#undef CONFIG_AUTO_UPDATE_SHOW
144
145#undef CONFIG_BZIP2
146#undef CONFIG_WATCHDOG
147
148#define CONFIG_SDRAM_BANK0 1
149
150
151
152
153#define CONFIG_SYS_LONGHELP
154#define CONFIG_SYS_PROMPT "=> "
155
156#undef CONFIG_SYS_HUSH_PARSER
157#ifdef CONFIG_SYS_HUSH_PARSER
158#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
159#endif
160
161#if defined(CONFIG_CMD_KGDB)
162#define CONFIG_SYS_CBSIZE 1024
163#else
164#define CONFIG_SYS_CBSIZE 256
165#endif
166#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
167#define CONFIG_SYS_MAXARGS 16
168#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
169
170#define CONFIG_SYS_DEVICE_NULLDEV 1
171
172#undef CONFIG_SYS_CONSOLE_INFO_QUIET
173
174#define CONFIG_AUTO_COMPLETE 1
175
176#define CONFIG_SYS_MEMTEST_START 0x0400000
177#define CONFIG_SYS_MEMTEST_END 0x0C00000
178
179#undef CONFIG_SYS_EXT_SERIAL_CLOCK
180#define CONFIG_SYS_BASE_BAUD 691200
181#define CONFIG_UART1_CONSOLE
182
183
184#define CONFIG_SYS_BAUDRATE_TABLE \
185 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
186 57600, 115200, 230400, 460800, 921600 }
187
188#define CONFIG_SYS_LOAD_ADDR 0x100000
189#define CONFIG_SYS_EXTBDINFO 1
190
191#define CONFIG_SYS_HZ 1000
192
193#define CONFIG_ZERO_BOOTDELAY_CHECK
194
195#define CONFIG_VERSION_VARIABLE 1
196
197#define CONFIG_SYS_RX_ETH_BUFFER 16
198
199
200
201
202
203#define CONFIG_RTC_DS1338
204#define CONFIG_SYS_I2C_RTC_ADDR 0x68
205
206
207
208
209
210#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
211#define CONFIG_SYS_MAX_NAND_DEVICE 1
212#define NAND_BIG_DELAY_US 25
213
214#define CONFIG_SYS_NAND_CE (0x80000000 >> 1)
215#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)
216#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)
217#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)
218
219#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1
220#define CONFIG_SYS_NAND_QUIET 1
221
222#define CONFIG_SYS_64BIT_VSPRINTF
223
224
225
226
227
228#define PCI_HOST_ADAPTER 0
229#define PCI_HOST_FORCE 1
230#define PCI_HOST_AUTO 2
231
232#define CONFIG_PCI
233#define CONFIG_PCI_HOST PCI_HOST_HOST
234#define CONFIG_PCI_PNP
235
236
237#define CONFIG_PCI_SCAN_SHOW
238
239#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
240
241#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
242#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
243#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
244#define CONFIG_SYS_PCI_PTM1LA 0x00000000
245#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
246#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
247#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
248#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
249#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
250
251
252
253
254
255#undef CONFIG_IDE_8xx_DIRECT
256#undef CONFIG_IDE_LED
257#define CONFIG_IDE_RESET 1
258
259#define CONFIG_SYS_IDE_MAXBUS 1
260#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
261
262#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
263#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
264
265#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
266#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
267#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
268
269
270
271
272
273
274#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
275
276
277
278#define FLASH_BASE0_PRELIM 0xFFC00000
279
280#define CONFIG_SYS_MAX_FLASH_BANKS 1
281#define CONFIG_SYS_MAX_FLASH_SECT 256
282
283#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
284#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
285
286#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
287#define CONFIG_SYS_FLASH_ADDR0 0x5555
288#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
289
290
291
292
293#define CONFIG_SYS_FLASH_READ0 0x0000
294#define CONFIG_SYS_FLASH_READ1 0x0001
295#define CONFIG_SYS_FLASH_READ2 0x0002
296
297#define CONFIG_SYS_FLASH_EMPTY_INFO
298
299#if 0
300#define CONFIG_SYS_JFFS2_FIRST_BANK 0
301#define CONFIG_SYS_JFFS2_NUM_BANKS 1
302#endif
303
304
305
306
307
308
309#define CONFIG_SYS_SDRAM_BASE 0x00000000
310#define CONFIG_SYS_FLASH_BASE 0xFFF80000
311#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
312#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
313#define CONFIG_SYS_MALLOC_LEN (4 << 20)
314
315#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
316# define CONFIG_SYS_RAMBOOT 1
317#else
318# undef CONFIG_SYS_RAMBOOT
319#endif
320
321
322
323
324#define CONFIG_ENV_IS_IN_EEPROM 1
325#define CONFIG_ENV_OFFSET 0x100
326#define CONFIG_ENV_SIZE 0x700
327
328
329#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000
330#define CONFIG_SYS_NVRAM_SIZE 0x8000
331
332
333
334
335#define CONFIG_HARD_I2C
336#if 0
337#define CONFIG_SYS_I2C_SPEED 400000
338#else
339#define CONFIG_SYS_I2C_SPEED 100000
340#endif
341#define CONFIG_SYS_I2C_SLAVE 0x7F
342
343#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
344#define CONFIG_SYS_EEPROM_WREN 1
345
346#if 1
347
348#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
349
350#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
351#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
352
353
354#else
355
356#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
357
358#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
359#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
360
361
362#endif
363#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
364
365
366
367
368
369#define CAN_BA 0xF0000000
370#define LCD_BA 0xF1000000
371#define CONFIG_SYS_NAND_BASE 0xF4000000
372#define CONFIG_SYS_NVRAM_BASE 0xF4080000
373
374
375#define CONFIG_SYS_EBC_PB0AP 0x92015480
376#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
377
378
379#define CONFIG_SYS_EBC_PB1AP 0x92015480
380#define CONFIG_SYS_EBC_PB1CR 0xF4018000
381
382
383#define CONFIG_SYS_EBC_PB2AP 0x010053C0
384#define CONFIG_SYS_EBC_PB2CR 0xF0018000
385
386
387#define CONFIG_SYS_EBC_PB3AP 0x010053C0
388#define CONFIG_SYS_EBC_PB3CR 0xF011A000
389
390
391#define CONFIG_SYS_EBC_PB4AP 0x03805380
392#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000
393
394
395
396
397
398#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000
399#define CONFIG_SYS_LCD_BIG_REG 0xF1000000
400#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000
401#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0
402
403
404
405
406
407
408
409
410#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
411
412
413
414
415
416#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100
417
418#define LCD_CLK_OFF 0x0000
419#define LCD_CLK_02083 0x1000
420#define LCD_CLK_03135 0x2000
421#define LCD_CLK_04165 0x3000
422#define LCD_CLK_06250 0x4000
423#define LCD_CLK_08330 0x5000
424#define LCD_CLK_12500 0x6000
425#define LCD_CLK_25000 0x7000
426
427#define CONFIG_SYS_FPGA_SPARTAN2 1
428#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
429
430
431#define CONFIG_SYS_FPGA_PRG 0x04000000
432#define CONFIG_SYS_FPGA_CLK 0x02000000
433#define CONFIG_SYS_FPGA_DATA 0x01000000
434#define CONFIG_SYS_FPGA_INIT 0x00010000
435#define CONFIG_SYS_FPGA_DONE 0x00008000
436
437
438
439
440
441#define CONFIG_SYS_TEMP_STACK_OCM 1
442
443
444#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
445#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
446#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
447#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
448
449#define CONFIG_SYS_GBL_DATA_SIZE 128
450#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
451#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
452
453
454
455
456
457
458
459
460
461
462
463
464
465#define CONFIG_SYS_GPIO0_OSRH 0x40000550
466#define CONFIG_SYS_GPIO0_OSRL 0x00000110
467#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
468#define CONFIG_SYS_GPIO0_ISR1L 0x15555440
469#define CONFIG_SYS_GPIO0_TSRH 0x00000000
470#define CONFIG_SYS_GPIO0_TSRL 0x00000000
471#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
472
473#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
474#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8)
475#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9)
476#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
477#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
478
479
480
481
482
483
484#define BOOTFLAG_COLD 0x01
485#define BOOTFLAG_WARM 0x02
486
487
488
489
490
491#if 0
492#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
493#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
494#endif
495#if 0
496#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
497#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
498#endif
499#if 1
500#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
501#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
502#endif
503
504#endif
505