1/* 2 * Copyright (C) 2004 Arabella Software Ltd. 3 * Yuli Barcohen <yuli@arabellasw.com> 4 * 5 * Support for Interphase iSPAN Communications Controllers 6 * (453x and others). Tested on 4532. 7 * 8 * Derived from iSPAN 4539 port (iphase4539) by 9 * Wolfgang Grandegger <wg@denx.de> 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29#ifndef __CONFIG_H 30#define __CONFIG_H 31 32#define CONFIG_MPC8260 /* This is an MPC8260 CPU */ 33#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */ 34#define CONFIG_CPM2 1 /* Has a CPM2 */ 35 36/*----------------------------------------------------------------------- 37 * Select serial console configuration 38 * 39 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 40 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 41 * for SCC). 42 * 43 * If CONFIG_CONS_NONE is defined, then the serial console routines must be 44 * defined elsewhere (for example, on the cogent platform, there are serial 45 * ports on the motherboard which are used for the serial console - see 46 * cogent/cma101/serial.[ch]). 47 */ 48#define CONFIG_CONS_ON_SMC /* Define if console on SMC */ 49#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */ 50#undef CONFIG_CONS_NONE /* Define if console on something else */ 51#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */ 52 53/*----------------------------------------------------------------------- 54 * Select Ethernet configuration 55 * 56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 57 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 58 * for FCC). 59 * 60 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must 61 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 62 */ 63#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ 64#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ 65#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */ 66#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */ 67 68#ifdef CONFIG_ETHER_ON_FCC 69 70#if CONFIG_ETHER_INDEX == 3 71 72#define CONFIG_SYS_PHY_ADDR 0 73#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) 74#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) 75 76#endif /* CONFIG_ETHER_INDEX == 3 */ 77 78#define CONFIG_SYS_CPMFCR_RAMTYPE 0 79#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) 80 81#define CONFIG_MII /* MII PHY management */ 82#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */ 83/* 84 * GPIO pins used for bit-banged MII communications 85 */ 86#define MDIO_PORT 3 /* Port D */ 87#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 88 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 89#define MDC_DECLARE MDIO_DECLARE 90 91 92#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */ 93#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */ 94 95#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) 96#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) 97#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) 98 99#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ 100 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN 101 102#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ 103 else iop->pdat &= ~CONFIG_SYS_MDC_PIN 104 105#define MIIDELAY udelay(1) 106 107#endif /* CONFIG_ETHER_ON_FCC */ 108 109#define CONFIG_8260_CLKIN 65536000 /* in Hz */ 110#define CONFIG_BAUDRATE 38400 111 112 113/* 114 * BOOTP options 115 */ 116#define CONFIG_BOOTP_BOOTFILESIZE 117#define CONFIG_BOOTP_BOOTPATH 118#define CONFIG_BOOTP_GATEWAY 119#define CONFIG_BOOTP_HOSTNAME 120 121 122/* 123 * Command line configuration. 124 */ 125#include <config_cmd_default.h> 126 127#define CONFIG_CMD_ASKENV 128#define CONFIG_CMD_DHCP 129#define CONFIG_CMD_IMMAP 130#define CONFIG_CMD_MII 131#define CONFIG_CMD_PING 132#define CONFIG_CMD_REGINFO 133 134 135#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 136#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ 137#define CONFIG_BOOTARGS "root=/dev/ram rw" 138 139#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ 140#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ 141 142/*----------------------------------------------------------------------- 143 * Miscellaneous configurable options 144 */ 145#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 146#define CONFIG_SYS_HUSH_PARSER 147#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 148#define CONFIG_SYS_LONGHELP /* #undef to save memory */ 149#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 150#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 151#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ 152#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 153 154#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 155#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */ 156 157#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */ 158 159#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ 160 161#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 162 163#define CONFIG_SYS_RESET_ADDRESS 0x09900000 164 165#define CONFIG_MISC_INIT_R /* We need misc_init_r() */ 166 167/*----------------------------------------------------------------------- 168 * For booting Linux, the board info and command line data 169 * have to be in the first 8 MB of memory, since this is 170 * the maximum mapped by the Linux kernel during initialization. 171 */ 172#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 173 174#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 175#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 176#ifdef CONFIG_BZIP2 177#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 178#else 179#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ 180#endif /* CONFIG_BZIP2 */ 181 182/*----------------------------------------------------------------------- 183 * FLASH organization 184 */ 185#define CONFIG_SYS_FLASH_BASE 0xFE000000 186#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 187#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 188#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */ 189#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */ 190 191/* Environment is in flash, there is little space left in Serial EEPROM */ 192#define CONFIG_ENV_IS_IN_FLASH 193#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ 194#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 195#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 196#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 197#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 198 199/*----------------------------------------------------------------------- 200 * Hard Reset Configuration Words 201 * 202 * If you change bits in the HRCW, you must also change the CONFIG_SYS_* 203 * defines for the various registers affected by the HRCW e.g. changing 204 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 205 */ 206/* 0x1686B245 */ 207#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\ 208 HRCW_L2CPC10 | HRCW_ISB110 |\ 209 HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\ 210 HRCW_CS10PC01 | HRCW_MODCK_H0101 \ 211 ) 212/* No slaves */ 213#define CONFIG_SYS_HRCW_SLAVE1 0 214#define CONFIG_SYS_HRCW_SLAVE2 0 215#define CONFIG_SYS_HRCW_SLAVE3 0 216#define CONFIG_SYS_HRCW_SLAVE4 0 217#define CONFIG_SYS_HRCW_SLAVE5 0 218#define CONFIG_SYS_HRCW_SLAVE6 0 219#define CONFIG_SYS_HRCW_SLAVE7 0 220 221/*----------------------------------------------------------------------- 222 * Internal Memory Mapped Register 223 */ 224#define CONFIG_SYS_IMMR 0xF0F00000 225#ifdef CONFIG_SYS_REV_B 226#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000 227#endif /* CONFIG_SYS_REV_B */ 228/*----------------------------------------------------------------------- 229 * Definitions for initial stack pointer and data area (in DPRAM) 230 */ 231#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 232#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ 233#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ 234#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 235#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 236 237/*----------------------------------------------------------------------- 238 * Internal Definitions 239 * 240 * Boot Flags 241 */ 242#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ 243#define BOOTFLAG_WARM 0x02 /* Software reboot */ 244 245/*----------------------------------------------------------------------- 246 * Cache Configuration 247 */ 248#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 249 250/*----------------------------------------------------------------------- 251 * HIDx - Hardware Implementation-dependent Registers 2-11 252 *----------------------------------------------------------------------- 253 * HID0 also contains cache control. 254 * 255 * HID1 has only read-only information - nothing to set. 256 */ 257#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 258 HID0_IFEM|HID0_ABE) 259#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 260#define CONFIG_SYS_HID2 0 261 262/*----------------------------------------------------------------------- 263 * RMR - Reset Mode Register 5-5 264 *----------------------------------------------------------------------- 265 * turn on Checkstop Reset Enable 266 */ 267#define CONFIG_SYS_RMR RMR_CSRE 268 269/*----------------------------------------------------------------------- 270 * BCR - Bus Configuration 4-25 271 *----------------------------------------------------------------------- 272 */ 273#define CONFIG_SYS_BCR 0xA01C0000 274 275/*----------------------------------------------------------------------- 276 * SIUMCR - SIU Module Configuration 4-31 277 *----------------------------------------------------------------------- 278 */ 279#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */ 280 281/*----------------------------------------------------------------------- 282 * SYPCR - System Protection Control 4-35 283 * SYPCR can only be written once after reset! 284 *----------------------------------------------------------------------- 285 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 286 */ 287#if defined (CONFIG_WATCHDOG) 288#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 289 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 290#else 291#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 292 SYPCR_SWRI|SYPCR_SWP) 293#endif /* CONFIG_WATCHDOG */ 294 295/*----------------------------------------------------------------------- 296 * TMCNTSC - Time Counter Status and Control 4-40 297 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 298 * and enable Time Counter 299 *----------------------------------------------------------------------- 300 */ 301#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 302 303/*----------------------------------------------------------------------- 304 * PISCR - Periodic Interrupt Status and Control 4-42 305 *----------------------------------------------------------------------- 306 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 307 * Periodic timer 308 */ 309#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 310 311/*----------------------------------------------------------------------- 312 * SCCR - System Clock Control 9-8 313 *----------------------------------------------------------------------- 314 * Ensure DFBRG is Divide by 16 315 */ 316#define CONFIG_SYS_SCCR SCCR_DFBRG01 317 318/*----------------------------------------------------------------------- 319 * RCCR - RISC Controller Configuration 13-7 320 *----------------------------------------------------------------------- 321 */ 322#define CONFIG_SYS_RCCR 0 323 324/*----------------------------------------------------------------------- 325 * Init Memory Controller: 326 * 327 * Bank Bus Machine PortSize Device 328 * ---- --- ------- ----------------------------- ------ 329 * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash 330 * 1 60x SDRAM 64 bit SDRAM 331 * 2 Local SDRAM 32 bit SDRAM 332 */ 333#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory 334 controller, rely on initialisation 335 performed by the Interphase boot firmware. 336 */ 337 338#define CONFIG_SYS_OR0_PRELIM 0xFE000882 339#ifdef CONFIG_SYS_REV_B 340#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V) 341#else /* Rev. D */ 342#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V) 343#endif /* CONFIG_SYS_REV_B */ 344 345#define CONFIG_SYS_MPTPR 0x7F00 346 347/* Please note that 60x SDRAM MUST start at 0 */ 348#define CONFIG_SYS_SDRAM_BASE 0x00000000 349#define CONFIG_SYS_60x_BR 0x00000041 350#define CONFIG_SYS_60x_OR 0xF0002CD0 351#define CONFIG_SYS_PSDMR 0x0049929A 352#define CONFIG_SYS_PSRT 0x07 353 354#define CONFIG_SYS_LSDRAM_BASE 0xF7000000 355#define CONFIG_SYS_LOC_BR 0x00001861 356#define CONFIG_SYS_LOC_OR 0xFF803280 357#define CONFIG_SYS_LSDMR 0x8285A552 358#define CONFIG_SYS_LSRT 0x07 359 360#endif /* __CONFIG_H */ 361