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27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#ifdef CONFIG_MK_36BIT
31#define CONFIG_PHYS_64BIT 1
32#endif
33
34#ifdef CONFIG_MK_NAND
35#define CONFIG_NAND_U_BOOT 1
36#define CONFIG_RAMBOOT_NAND 1
37#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
38#endif
39
40#ifdef CONFIG_MK_SDCARD
41#define CONFIG_RAMBOOT_SDCARD 1
42#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
43#endif
44
45#ifdef CONFIG_MK_SPIFLASH
46#define CONFIG_RAMBOOT_SPIFLASH 1
47#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
48#endif
49
50
51#define CONFIG_BOOKE 1
52#define CONFIG_E500 1
53#define CONFIG_MPC85xx 1
54#define CONFIG_MPC8536 1
55#define CONFIG_MPC8536DS 1
56
57#define CONFIG_FSL_ELBC 1
58#define CONFIG_PCI 1
59#define CONFIG_PCI1 1
60#define CONFIG_PCIE1 1
61#define CONFIG_PCIE2 1
62#define CONFIG_PCIE3 1
63#define CONFIG_FSL_PCI_INIT 1
64#define CONFIG_FSL_PCIE_RESET 1
65#define CONFIG_SYS_PCI_64BIT 1
66
67#define CONFIG_FSL_LAW 1
68#define CONFIG_E1000 1
69
70#define CONFIG_TSEC_ENET
71#define CONFIG_ENV_OVERWRITE
72
73#ifndef __ASSEMBLY__
74extern unsigned long get_board_sys_clk(unsigned long dummy);
75extern unsigned long get_board_ddr_clk(unsigned long dummy);
76#endif
77#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
78#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
79#define CONFIG_ICS307_REFCLK_HZ 33333000
80#define CONFIG_GET_CLK_FROM_ICS307
81
82
83
84
85
86#define CONFIG_L2_CACHE
87#define CONFIG_BTB
88
89#define CONFIG_BOARD_EARLY_INIT_F 1
90
91#define CONFIG_ENABLE_36BIT_PHYS 1
92
93#ifdef CONFIG_PHYS_64BIT
94#define CONFIG_ADDR_MAP 1
95#define CONFIG_SYS_NUM_ADDR_MAP 16
96#endif
97
98#define CONFIG_SYS_MEMTEST_START 0x00010000
99#define CONFIG_SYS_MEMTEST_END 0x1f000000
100#define CONFIG_PANIC_HANG
101
102
103
104
105#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
106#ifdef CONFIG_PHYS_64BIT
107#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
108#else
109#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
110#endif
111#define CONFIG_SYS_L2_SIZE (512 << 10)
112#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
113
114
115
116
117
118#define CONFIG_SYS_CCSRBAR 0xffe00000
119#ifdef CONFIG_PHYS_64BIT
120#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
121#else
122#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
123#endif
124#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
125
126#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
127#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
128#else
129#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
130#endif
131
132#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
133#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
134#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
135#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000)
136
137
138#define CONFIG_VERY_BIG_RAM
139#define CONFIG_FSL_DDR2
140#undef CONFIG_FSL_DDR_INTERACTIVE
141#define CONFIG_SPD_EEPROM
142#define CONFIG_DDR_SPD
143#undef CONFIG_DDR_DLL
144
145#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
146#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
147
148#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
149#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
150
151#define CONFIG_NUM_DDR_CONTROLLERS 1
152#define CONFIG_DIMM_SLOTS_PER_CTLR 1
153#define CONFIG_CHIP_SELECTS_PER_CTRL 2
154
155
156#define SPD_EEPROM_ADDRESS 0x51
157#define CONFIG_SYS_SPD_BUS_NUM 1
158
159
160#define CONFIG_SYS_SDRAM_SIZE 256
161#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
162#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
163#define CONFIG_SYS_DDR_TIMING_3 0x00000000
164#define CONFIG_SYS_DDR_TIMING_0 0x00260802
165#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
166#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
167#define CONFIG_SYS_DDR_MODE_1 0x00480432
168#define CONFIG_SYS_DDR_MODE_2 0x00000000
169#define CONFIG_SYS_DDR_INTERVAL 0x06180100
170#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
171#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
172#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
173#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
174#define CONFIG_SYS_DDR_CONTROL 0xC3008000
175#define CONFIG_SYS_DDR_CONTROL2 0x04400010
176
177#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
178#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
179#define CONFIG_SYS_DDR_SBE 0x00010000
180
181
182#ifndef CONFIG_SPD_EEPROM
183#error ("CONFIG_SPD_EEPROM is required")
184#endif
185
186#undef CONFIG_CLOCKS_IN_MHZ
187
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210
211
212#define CONFIG_SYS_FLASH_BASE 0xe0000000
213#ifdef CONFIG_PHYS_64BIT
214#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
215#else
216#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
217#endif
218
219#define CONFIG_FLASH_BR_PRELIM \
220 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
221 | BR_PS_16 | BR_V)
222#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
223
224#define CONFIG_SYS_BR1_PRELIM \
225 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
226 | BR_PS_16 | BR_V)
227#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
228
229#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
230 CONFIG_SYS_FLASH_BASE_PHYS }
231#define CONFIG_SYS_FLASH_QUIET_TEST
232#define CONFIG_FLASH_SHOW_PROGRESS 45
233
234#define CONFIG_SYS_MAX_FLASH_BANKS 2
235#define CONFIG_SYS_MAX_FLASH_SECT 1024
236#undef CONFIG_SYS_FLASH_CHECKSUM
237#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
238#define CONFIG_SYS_FLASH_WRITE_TOUT 500
239
240#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
241
242#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
243 || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
244#define CONFIG_SYS_RAMBOOT
245#else
246#undef CONFIG_SYS_RAMBOOT
247#endif
248
249#define CONFIG_FLASH_CFI_DRIVER
250#define CONFIG_SYS_FLASH_CFI
251#define CONFIG_SYS_FLASH_EMPTY_INFO
252#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
253
254#define CONFIG_BOARD_EARLY_INIT_R
255
256#define CONFIG_FSL_PIXIS 1
257#define PIXIS_BASE 0xffdf0000
258#ifdef CONFIG_PHYS_64BIT
259#define PIXIS_BASE_PHYS 0xfffdf0000ull
260#else
261#define PIXIS_BASE_PHYS PIXIS_BASE
262#endif
263
264#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
265#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
266
267#define PIXIS_ID 0x0
268#define PIXIS_VER 0x1
269#define PIXIS_PVER 0x2
270#define PIXIS_CSR 0x3
271#define PIXIS_RST 0x4
272#define PIXIS_PWR 0x5
273#define PIXIS_AUX 0x6
274#define PIXIS_SPD 0x7
275#define PIXIS_AUX2 0x8
276#define PIXIS_VCTL 0x10
277#define PIXIS_VSTAT 0x11
278#define PIXIS_VCFGEN0 0x12
279#define PIXIS_VCFGEN1 0x13
280#define PIXIS_VCORE0 0x14
281#define PIXIS_VBOOT 0x16
282#define PIXIS_VBOOT_LBMAP 0xe0
283#define PIXIS_VBOOT_LBMAP_NOR0 0x00
284#define PIXIS_VBOOT_LBMAP_NOR1 0x01
285#define PIXIS_VBOOT_LBMAP_NOR2 0x02
286#define PIXIS_VBOOT_LBMAP_NOR3 0x03
287#define PIXIS_VBOOT_LBMAP_PJET 0x04
288#define PIXIS_VBOOT_LBMAP_NAND 0x05
289#define PIXIS_VSPEED0 0x17
290#define PIXIS_VSPEED1 0x18
291#define PIXIS_VSPEED2 0x19
292#define PIXIS_VSYSCLK0 0x1A
293#define PIXIS_VSYSCLK1 0x1B
294#define PIXIS_VSYSCLK2 0x1C
295#define PIXIS_VDDRCLK0 0x1D
296#define PIXIS_VDDRCLK1 0x1E
297#define PIXIS_VDDRCLK2 0x1F
298#define PIXIS_VWATCH 0x24
299#define PIXIS_LED 0x25
300
301#define PIXIS_SPD_SYSCLK 0x7
302
303
304#define PIXIS_VCLKH 0x19
305#define PIXIS_VCLKL 0x1A
306#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
307
308#define CONFIG_SYS_INIT_RAM_LOCK 1
309#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
310#define CONFIG_SYS_INIT_RAM_END 0x00004000
311
312#define CONFIG_SYS_GBL_DATA_SIZE 128
313#define CONFIG_SYS_GBL_DATA_OFFSET \
314 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
315#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
316
317#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
318#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
319
320#ifndef CONFIG_NAND_SPL
321#define CONFIG_SYS_NAND_BASE 0xffa00000
322#ifdef CONFIG_PHYS_64BIT
323#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
324#else
325#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
326#endif
327#else
328#define CONFIG_SYS_NAND_BASE 0xfff00000
329#ifdef CONFIG_PHYS_64BIT
330#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
331#else
332#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
333#endif
334#endif
335#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
336 CONFIG_SYS_NAND_BASE + 0x40000, \
337 CONFIG_SYS_NAND_BASE + 0x80000, \
338 CONFIG_SYS_NAND_BASE + 0xC0000}
339#define CONFIG_SYS_MAX_NAND_DEVICE 4
340#define CONFIG_MTD_NAND_VERIFY_WRITE
341#define CONFIG_CMD_NAND 1
342#define CONFIG_NAND_FSL_ELBC 1
343#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
344
345
346#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
347#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
348#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
349#define CONFIG_SYS_NAND_U_BOOT_START \
350 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
351#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
352#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
353#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
354
355
356#define CONFIG_NAND_BR_PRELIM \
357 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
358 | (2<<BR_DECC_SHIFT) \
359 | BR_PS_8 \
360 | BR_MS_FCM \
361 | BR_V)
362#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 \
363 | OR_FCM_PGS \
364 | OR_FCM_CSCT \
365 | OR_FCM_CST \
366 | OR_FCM_CHT \
367 | OR_FCM_SCY_1 \
368 | OR_FCM_TRLX \
369 | OR_FCM_EHTR)
370
371#ifdef CONFIG_RAMBOOT_NAND
372#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM
373#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM
374#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM
375#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM
376#else
377#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
378#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
379#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM
380#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM
381#endif
382
383#define CONFIG_SYS_BR4_PRELIM \
384 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
385 | (2<<BR_DECC_SHIFT) \
386 | BR_PS_8 \
387 | BR_MS_FCM \
388 | BR_V)
389#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM
390#define CONFIG_SYS_BR5_PRELIM \
391 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
392 | (2<<BR_DECC_SHIFT) \
393 | BR_PS_8 \
394 | BR_MS_FCM \
395 | BR_V)
396#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM
397
398#define CONFIG_SYS_BR6_PRELIM \
399 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
400 | (2<<BR_DECC_SHIFT) \
401 | BR_PS_8 \
402 | BR_MS_FCM \
403 | BR_V)
404#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM
405
406
407
408
409
410#define CONFIG_CONS_INDEX 1
411#undef CONFIG_SERIAL_SOFTWARE_FIFO
412#define CONFIG_SYS_NS16550
413#define CONFIG_SYS_NS16550_SERIAL
414#define CONFIG_SYS_NS16550_REG_SIZE 1
415#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
416
417#define CONFIG_SYS_BAUDRATE_TABLE \
418 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
419
420#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
421#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
422
423
424#define CONFIG_SYS_HUSH_PARSER
425#ifdef CONFIG_SYS_HUSH_PARSER
426#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
427#endif
428
429
430
431
432#define CONFIG_OF_LIBFDT 1
433#define CONFIG_OF_BOARD_SETUP 1
434#define CONFIG_OF_STDOUT_VIA_ALIAS 1
435
436#define CONFIG_SYS_64BIT_STRTOUL 1
437#define CONFIG_SYS_64BIT_VSPRINTF 1
438
439
440
441
442
443#define CONFIG_FSL_I2C
444#define CONFIG_HARD_I2C
445#undef CONFIG_SOFT_I2C
446#define CONFIG_I2C_MULTI_BUS
447#define CONFIG_SYS_I2C_SPEED 400000
448#define CONFIG_SYS_I2C_SLAVE 0x7F
449#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
450#define CONFIG_SYS_I2C_OFFSET 0x3000
451#define CONFIG_SYS_I2C2_OFFSET 0x3100
452
453
454
455
456#define CONFIG_ID_EEPROM
457#ifdef CONFIG_ID_EEPROM
458#define CONFIG_SYS_I2C_EEPROM_NXID
459#endif
460#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
461#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
462#define CONFIG_SYS_EEPROM_BUS_NUM 1
463
464
465
466
467
468
469#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
470#ifdef CONFIG_PHYS_64BIT
471#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
472#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
473#else
474#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
475#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
476#endif
477#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
478#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
479#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
480#ifdef CONFIG_PHYS_64BIT
481#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
482#else
483#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
484#endif
485#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
486
487
488#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
489#ifdef CONFIG_PHYS_64BIT
490#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
491#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
492#else
493#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
494#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
495#endif
496#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000
497#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
498#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
499#ifdef CONFIG_PHYS_64BIT
500#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
501#else
502#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
503#endif
504#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
505
506
507#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
508#ifdef CONFIG_PHYS_64BIT
509#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
510#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
511#else
512#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
513#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
514#endif
515#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000
516#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
517#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
518#ifdef CONFIG_PHYS_64BIT
519#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
520#else
521#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
522#endif
523#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
524
525
526#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
527#ifdef CONFIG_PHYS_64BIT
528#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
529#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
530#else
531#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
532#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
533#endif
534#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
535#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
536#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
537#ifdef CONFIG_PHYS_64BIT
538#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
539#else
540#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
541#endif
542#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
543
544#if defined(CONFIG_PCI)
545
546#define CONFIG_NET_MULTI
547#define CONFIG_PCI_PNP
548
549
550#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
551
552
553
554
555
556#define CONFIG_VIDEO
557
558#if defined(CONFIG_VIDEO)
559#define CONFIG_BIOSEMU
560#define CONFIG_CFB_CONSOLE
561#define CONFIG_VIDEO_SW_CURSOR
562#define CONFIG_VGA_AS_SINGLE_DEVICE
563#define CONFIG_ATI_RADEON_FB
564#define CONFIG_VIDEO_LOGO
565
566#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
567#endif
568
569#undef CONFIG_EEPRO100
570#undef CONFIG_TULIP
571#undef CONFIG_RTL8139
572
573#ifndef CONFIG_PCI_PNP
574 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
575 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
576 #define PCI_IDSEL_NUMBER 0x11
577#endif
578
579#define CONFIG_PCI_SCAN_SHOW
580
581#endif
582
583
584#define CONFIG_LIBATA
585#define CONFIG_FSL_SATA
586
587#define CONFIG_SYS_SATA_MAX_DEVICE 2
588#define CONFIG_SATA1
589#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
590#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
591#define CONFIG_SATA2
592#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
593#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
594
595#ifdef CONFIG_FSL_SATA
596#define CONFIG_LBA48
597#define CONFIG_CMD_SATA
598#define CONFIG_DOS_PARTITION
599#define CONFIG_CMD_EXT2
600#endif
601
602#if defined(CONFIG_TSEC_ENET)
603
604#ifndef CONFIG_NET_MULTI
605#define CONFIG_NET_MULTI 1
606#endif
607
608#define CONFIG_MII 1
609#define CONFIG_MII_DEFAULT_TSEC 1
610#define CONFIG_TSEC1 1
611#define CONFIG_TSEC1_NAME "eTSEC1"
612#define CONFIG_TSEC3 1
613#define CONFIG_TSEC3_NAME "eTSEC3"
614
615#define CONFIG_FSL_SGMII_RISER 1
616#define SGMII_RISER_PHY_OFFSET 0x1c
617
618#define TSEC1_PHY_ADDR 1
619#define TSEC3_PHY_ADDR 0
620
621#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
622#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
623
624#define TSEC1_PHYIDX 0
625#define TSEC3_PHYIDX 0
626
627#define CONFIG_ETHPRIME "eTSEC1"
628
629#define CONFIG_PHY_GIGE 1
630
631#endif
632
633
634
635
636
637#if defined(CONFIG_SYS_RAMBOOT)
638#if defined(CONFIG_RAMBOOT_NAND)
639 #define CONFIG_ENV_IS_IN_NAND 1
640 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
641 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
642#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
643 #define CONFIG_ENV_IS_NOWHERE 1
644 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
645 #define CONFIG_ENV_SIZE 0x2000
646#endif
647#else
648 #define CONFIG_ENV_IS_IN_FLASH 1
649 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
650 #define CONFIG_ENV_ADDR 0xfff80000
651 #else
652 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
653 #endif
654 #define CONFIG_ENV_SIZE 0x2000
655 #define CONFIG_ENV_SECT_SIZE 0x20000
656#endif
657
658#define CONFIG_LOADS_ECHO 1
659#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
660
661
662
663
664#include <config_cmd_default.h>
665
666#define CONFIG_CMD_IRQ
667#define CONFIG_CMD_PING
668#define CONFIG_CMD_I2C
669#define CONFIG_CMD_MII
670#define CONFIG_CMD_ELF
671#define CONFIG_CMD_IRQ
672#define CONFIG_CMD_SETEXPR
673
674#if defined(CONFIG_PCI)
675#define CONFIG_CMD_PCI
676#define CONFIG_CMD_NET
677#endif
678
679#undef CONFIG_WATCHDOG
680
681#define CONFIG_MMC 1
682
683#ifdef CONFIG_MMC
684#define CONFIG_FSL_ESDHC
685#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
686#define CONFIG_CMD_MMC
687#define CONFIG_GENERIC_MMC
688#define CONFIG_CMD_EXT2
689#define CONFIG_CMD_FAT
690#define CONFIG_DOS_PARTITION
691#endif
692
693
694
695
696#define CONFIG_SYS_LONGHELP
697#define CONFIG_CMDLINE_EDITING
698#define CONFIG_SYS_LOAD_ADDR 0x2000000
699#define CONFIG_SYS_PROMPT "=> "
700#if defined(CONFIG_CMD_KGDB)
701#define CONFIG_SYS_CBSIZE 1024
702#else
703#define CONFIG_SYS_CBSIZE 256
704#endif
705#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
706 + sizeof(CONFIG_SYS_PROMPT) + 16)
707#define CONFIG_SYS_MAXARGS 16
708#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
709#define CONFIG_SYS_HZ 1000
710
711
712
713
714
715
716#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
717
718
719
720
721
722
723#define BOOTFLAG_COLD 0x01
724#define BOOTFLAG_WARM 0x02
725
726#if defined(CONFIG_CMD_KGDB)
727#define CONFIG_KGDB_BAUDRATE 230400
728#define CONFIG_KGDB_SER_INDEX 2
729#endif
730
731
732
733
734
735
736#if defined(CONFIG_TSEC_ENET)
737#define CONFIG_HAS_ETH0
738#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
739#define CONFIG_HAS_ETH1
740#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
741#define CONFIG_HAS_ETH2
742#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
743#define CONFIG_HAS_ETH3
744#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
745#endif
746
747#define CONFIG_IPADDR 192.168.1.254
748
749#define CONFIG_HOSTNAME unknown
750#define CONFIG_ROOTPATH /opt/nfsroot
751#define CONFIG_BOOTFILE uImage
752#define CONFIG_UBOOTPATH u-boot.bin
753
754#define CONFIG_SERVERIP 192.168.1.1
755#define CONFIG_GATEWAYIP 192.168.1.1
756#define CONFIG_NETMASK 255.255.255.0
757
758
759#define CONFIG_LOADADDR 1000000
760
761#define CONFIG_BOOTDELAY 10
762#undef CONFIG_BOOTARGS
763
764#define CONFIG_BAUDRATE 115200
765
766#define CONFIG_EXTRA_ENV_SETTINGS \
767 "netdev=eth0\0" \
768 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
769 "tftpflash=tftpboot $loadaddr $uboot; " \
770 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
771 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
772 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
773 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
774 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
775 "consoledev=ttyS0\0" \
776 "ramdiskaddr=2000000\0" \
777 "ramdiskfile=8536ds/ramdisk.uboot\0" \
778 "fdtaddr=c00000\0" \
779 "fdtfile=8536ds/mpc8536ds.dtb\0" \
780 "bdev=sda3\0" \
781 "usb_phy_type=ulpi\0"
782
783#define CONFIG_HDBOOT \
784 "setenv bootargs root=/dev/$bdev rw " \
785 "console=$consoledev,$baudrate $othbootargs;" \
786 "tftp $loadaddr $bootfile;" \
787 "tftp $fdtaddr $fdtfile;" \
788 "bootm $loadaddr - $fdtaddr"
789
790#define CONFIG_NFSBOOTCOMMAND \
791 "setenv bootargs root=/dev/nfs rw " \
792 "nfsroot=$serverip:$rootpath " \
793 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
794 "console=$consoledev,$baudrate $othbootargs;" \
795 "tftp $loadaddr $bootfile;" \
796 "tftp $fdtaddr $fdtfile;" \
797 "bootm $loadaddr - $fdtaddr"
798
799#define CONFIG_RAMBOOTCOMMAND \
800 "setenv bootargs root=/dev/ram rw " \
801 "console=$consoledev,$baudrate $othbootargs;" \
802 "tftp $ramdiskaddr $ramdiskfile;" \
803 "tftp $loadaddr $bootfile;" \
804 "tftp $fdtaddr $fdtfile;" \
805 "bootm $loadaddr $ramdiskaddr $fdtaddr"
806
807#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
808
809#endif
810