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26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#ifdef CONFIG_MK_36BIT
31#define CONFIG_PHYS_64BIT
32#endif
33
34
35#define CONFIG_BOOKE 1
36#define CONFIG_E500 1
37#define CONFIG_MPC85xx 1
38#define CONFIG_P2020 1
39#define CONFIG_P2020DS 1
40#define CONFIG_MP 1
41
42#define CONFIG_FSL_ELBC 1
43#define CONFIG_PCI 1
44#define CONFIG_PCIE1 1
45#define CONFIG_PCIE2 1
46#define CONFIG_PCIE3 1
47#define CONFIG_FSL_PCI_INIT 1
48#define CONFIG_FSL_PCIE_RESET 1
49#define CONFIG_SYS_PCI_64BIT 1
50
51#define CONFIG_FSL_LAW 1
52#define CONFIG_E1000 1
53
54#define CONFIG_TSEC_ENET
55#define CONFIG_ENV_OVERWRITE
56
57#ifndef __ASSEMBLY__
58extern unsigned long calculate_board_sys_clk(unsigned long dummy);
59extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
60
61
62#endif
63#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0)
64#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0)
65#define CONFIG_ICS307_REFCLK_HZ 33333000
66#define CONFIG_GET_CLK_FROM_ICS307
67
68
69
70
71
72#define CONFIG_L2_CACHE
73#define CONFIG_BTB
74
75#define CONFIG_ENABLE_36BIT_PHYS 1
76
77#ifdef CONFIG_PHYS_64BIT
78#define CONFIG_ADDR_MAP 1
79#define CONFIG_SYS_NUM_ADDR_MAP 16
80#endif
81
82#define CONFIG_SYS_MEMTEST_START 0x00000000
83#define CONFIG_SYS_MEMTEST_END 0x7fffffff
84#define CONFIG_PANIC_HANG
85
86
87
88
89
90#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
91#define CONFIG_SYS_CCSRBAR 0xffe00000
92#ifdef CONFIG_PHYS_64BIT
93#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
94#else
95#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
96#endif
97#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
98
99#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
100#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
101#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
102
103
104#define CONFIG_SYS_DDR_TLB_START 9
105#define CONFIG_VERY_BIG_RAM
106#define CONFIG_FSL_DDR3 1
107#undef CONFIG_FSL_DDR_INTERACTIVE
108
109
110
111
112#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
114
115#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
116#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
117
118#define CONFIG_NUM_DDR_CONTROLLERS 1
119#define CONFIG_DIMM_SLOTS_PER_CTLR 1
120#define CONFIG_CHIP_SELECTS_PER_CTRL 2
121
122
123#define CONFIG_SYS_SPD_BUS_NUM 0
124#define SPD_EEPROM_ADDRESS1 0x51
125
126
127#define CONFIG_SYS_SDRAM_SIZE 1024
128
129
130#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
131#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
132#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
133#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
134#define CONFIG_SYS_DDR_TIMING_3 0x00020000
135#define CONFIG_SYS_DDR_TIMING_0 0x00330804
136#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
137#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
138#define CONFIG_SYS_DDR_MODE_1 0x00421422
139#define CONFIG_SYS_DDR_MODE_2 0x00000000
140#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
141#define CONFIG_SYS_DDR_INTERVAL 0x61800100
142#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
143#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
144#define CONFIG_SYS_DDR_TIMING_4 0x00220001
145#define CONFIG_SYS_DDR_TIMING_5 0x03402400
146#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
147#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
148#define CONFIG_SYS_DDR_CONTROL 0xE7000000
149#define CONFIG_SYS_DDR_CONTROL2 0x24400011
150#define CONFIG_SYS_DDR_CDR1 0x00040000
151#define CONFIG_SYS_DDR_CDR2 0x00000000
152
153#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
154#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
155#define CONFIG_SYS_DDR_SBE 0x00010000
156
157
158#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F
159#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000
160#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
161#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
162#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
163#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000
164
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183
184
185#undef CONFIG_CLOCKS_IN_MHZ
186
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209
210#define CONFIG_SYS_FLASH_BASE 0xe0000000
211#ifdef CONFIG_PHYS_64BIT
212#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
213#else
214#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
215#endif
216
217#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
218#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
219
220#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
221#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
222
223#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
224#define CONFIG_SYS_FLASH_QUIET_TEST
225#define CONFIG_FLASH_SHOW_PROGRESS 45
226
227#define CONFIG_SYS_MAX_FLASH_BANKS 2
228#define CONFIG_SYS_MAX_FLASH_SECT 1024
229#undef CONFIG_SYS_FLASH_CHECKSUM
230#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
231#define CONFIG_SYS_FLASH_WRITE_TOUT 500
232
233#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
234
235#define CONFIG_FLASH_CFI_DRIVER
236#define CONFIG_SYS_FLASH_CFI
237#define CONFIG_SYS_FLASH_EMPTY_INFO
238#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
239
240#define CONFIG_BOARD_EARLY_INIT_R
241
242#define CONFIG_FSL_PIXIS 1
243#define PIXIS_BASE 0xffdf0000
244#ifdef CONFIG_PHYS_64BIT
245#define PIXIS_BASE_PHYS 0xfffdf0000ull
246#else
247#define PIXIS_BASE_PHYS PIXIS_BASE
248#endif
249
250#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
251#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
252
253#define PIXIS_ID 0x0
254#define PIXIS_VER 0x1
255#define PIXIS_PVER 0x2
256#define PIXIS_CSR 0x3
257#define PIXIS_RST 0x4
258#define PIXIS_PWR 0x5
259#define PIXIS_AUX 0x6
260#define PIXIS_SPD 0x7
261#define PIXIS_AUX2 0x8
262#define PIXIS_VCTL 0x10
263#define PIXIS_VSTAT 0x11
264#define PIXIS_VCFGEN0 0x12
265#define PIXIS_VCFGEN1 0x13
266#define PIXIS_VCORE0 0x14
267#define PIXIS_VBOOT 0x16
268#define PIXIS_VSPEED0 0x17
269#define PIXIS_VSPEED1 0x18
270#define PIXIS_VSPEED2 0x19
271#define PIXIS_VSYSCLK0 0x19
272#define PIXIS_VSYSCLK1 0x1A
273#define PIXIS_VSYSCLK2 0x1B
274#define PIXIS_VDDRCLK0 0x1C
275#define PIXIS_VDDRCLK1 0x1D
276#define PIXIS_VDDRCLK2 0x1E
277
278#define PIXIS_VWATCH 0x24
279#define PIXIS_LED 0x25
280
281#define PIXIS_SW(x) 0x20 + (x - 1) * 2
282#define PIXIS_EN(x) 0x21 + (x - 1) * 2
283#define PIXIS_SW7_LBMAP 0xc0
284#define PIXIS_SW7_VBANK 0x30
285
286
287#define PIXIS_VCLKH 0x19
288#define PIXIS_VCLKL 0x1A
289#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
290#define PIXIS_VSPEED2_TSEC1SER 0x8
291#define PIXIS_VSPEED2_TSEC2SER 0x4
292#define PIXIS_VSPEED2_TSEC3SER 0x2
293#define PIXIS_VSPEED2_TSEC4SER 0x1
294#define PIXIS_VCFGEN1_TSEC1SER 0x20
295#define PIXIS_VCFGEN1_TSEC2SER 0x20
296#define PIXIS_VCFGEN1_TSEC3SER 0x20
297#define PIXIS_VCFGEN1_TSEC4SER 0x20
298#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
299 | PIXIS_VSPEED2_TSEC2SER \
300 | PIXIS_VSPEED2_TSEC3SER \
301 | PIXIS_VSPEED2_TSEC4SER)
302#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
303 | PIXIS_VCFGEN1_TSEC2SER \
304 | PIXIS_VCFGEN1_TSEC3SER \
305 | PIXIS_VCFGEN1_TSEC4SER)
306
307#define CONFIG_SYS_INIT_RAM_LOCK 1
308#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
309#define CONFIG_SYS_INIT_RAM_END 0x00004000
310
311#define CONFIG_SYS_GBL_DATA_SIZE 128
312#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
313#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
314
315#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
316#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
317
318#define CONFIG_SYS_NAND_BASE 0xffa00000
319#ifdef CONFIG_PHYS_64BIT
320#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
321#else
322#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
323#endif
324#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
325 CONFIG_SYS_NAND_BASE + 0x40000, \
326 CONFIG_SYS_NAND_BASE + 0x80000,\
327 CONFIG_SYS_NAND_BASE + 0xC0000}
328#define CONFIG_SYS_MAX_NAND_DEVICE 4
329#define CONFIG_MTD_NAND_VERIFY_WRITE
330#define CONFIG_CMD_NAND 1
331#define CONFIG_NAND_FSL_ELBC 1
332#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
333
334
335#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
336 | (2<<BR_DECC_SHIFT) \
337 | BR_PS_8 \
338 | BR_MS_FCM \
339 | BR_V)
340#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 \
341 | OR_FCM_PGS \
342 | OR_FCM_CSCT \
343 | OR_FCM_CST \
344 | OR_FCM_CHT \
345 | OR_FCM_SCY_1 \
346 | OR_FCM_TRLX \
347 | OR_FCM_EHTR)
348
349#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
350#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
351#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM
352#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM
353
354#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
355 | (2<<BR_DECC_SHIFT) \
356 | BR_PS_8 \
357 | BR_MS_FCM \
358 | BR_V)
359#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM
360#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
361 | (2<<BR_DECC_SHIFT) \
362 | BR_PS_8 \
363 | BR_MS_FCM \
364 | BR_V)
365#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM
366
367#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
368 | (2<<BR_DECC_SHIFT) \
369 | BR_PS_8 \
370 | BR_MS_FCM \
371 | BR_V)
372#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM
373
374
375
376
377
378#define CONFIG_CONS_INDEX 1
379#undef CONFIG_SERIAL_SOFTWARE_FIFO
380#define CONFIG_SYS_NS16550
381#define CONFIG_SYS_NS16550_SERIAL
382#define CONFIG_SYS_NS16550_REG_SIZE 1
383#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
384
385#define CONFIG_SYS_BAUDRATE_TABLE \
386 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
387
388#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
389#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
390
391
392#define CONFIG_SYS_HUSH_PARSER
393#ifdef CONFIG_SYS_HUSH_PARSER
394#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
395#endif
396
397
398
399
400#define CONFIG_OF_LIBFDT 1
401#define CONFIG_OF_BOARD_SETUP 1
402#define CONFIG_OF_STDOUT_VIA_ALIAS 1
403
404#define CONFIG_SYS_64BIT_VSPRINTF 1
405#define CONFIG_SYS_64BIT_STRTOUL 1
406
407
408#define CONFIG_FIT 1
409#define CONFIG_FIT_VERBOSE 1
410
411
412#define CONFIG_FSL_I2C
413#define CONFIG_HARD_I2C
414#undef CONFIG_SOFT_I2C
415#define CONFIG_I2C_MULTI_BUS
416#define CONFIG_SYS_I2C_SPEED 400000
417#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
418#define CONFIG_SYS_I2C_SLAVE 0x7F
419#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}
420#define CONFIG_SYS_I2C_OFFSET 0x3000
421#define CONFIG_SYS_I2C2_OFFSET 0x3100
422
423
424
425
426#define CONFIG_ID_EEPROM
427#ifdef CONFIG_ID_EEPROM
428#define CONFIG_SYS_I2C_EEPROM_NXID
429#endif
430#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
431#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
432#define CONFIG_SYS_EEPROM_BUS_NUM 0
433
434
435
436
437
438
439
440#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
441#ifdef CONFIG_PHYS_64BIT
442#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
443#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
444#else
445#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
446#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
447#endif
448#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
449#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
450#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
451#ifdef CONFIG_PHYS_64BIT
452#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
453#else
454#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
455#endif
456#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
457
458
459#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
460#ifdef CONFIG_PHYS_64BIT
461#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
462#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
463#else
464#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
465#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
466#endif
467#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
468#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
469#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
470#ifdef CONFIG_PHYS_64BIT
471#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
472#else
473#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
474#endif
475#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
476
477
478#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
479#ifdef CONFIG_PHYS_64BIT
480#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
481#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
482#else
483#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
484#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
485#endif
486#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
487#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
488#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
489#ifdef CONFIG_PHYS_64BIT
490#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
491#else
492#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
493#endif
494#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
495
496#if defined(CONFIG_PCI)
497
498
499#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
500
501
502#define CONFIG_VIDEO
503
504#if defined(CONFIG_VIDEO)
505#define CONFIG_BIOSEMU
506#define CONFIG_CFB_CONSOLE
507#define CONFIG_VIDEO_SW_CURSOR
508#define CONFIG_VGA_AS_SINGLE_DEVICE
509#define CONFIG_ATI_RADEON_FB
510#define CONFIG_VIDEO_LOGO
511
512#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
513#endif
514
515#define CONFIG_NET_MULTI
516#define CONFIG_PCI_PNP
517
518#undef CONFIG_EEPRO100
519#undef CONFIG_TULIP
520#define CONFIG_RTL8139
521
522#ifndef CONFIG_PCI_PNP
523 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
524 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
525 #define PCI_IDSEL_NUMBER 0x11
526#endif
527
528#define CONFIG_PCI_SCAN_SHOW
529#define CONFIG_DOS_PARTITION
530#define CONFIG_SCSI_AHCI
531
532#ifdef CONFIG_SCSI_AHCI
533#define CONFIG_SATA_ULI5288
534#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
535#define CONFIG_SYS_SCSI_MAX_LUN 1
536#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
537#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
538#endif
539
540#endif
541
542
543#if defined(CONFIG_TSEC_ENET)
544
545#ifndef CONFIG_NET_MULTI
546#define CONFIG_NET_MULTI 1
547#endif
548
549#define CONFIG_MII 1
550#define CONFIG_MII_DEFAULT_TSEC 1
551#define CONFIG_TSEC1 1
552#define CONFIG_TSEC1_NAME "eTSEC1"
553#define CONFIG_TSEC2 1
554#define CONFIG_TSEC2_NAME "eTSEC2"
555#define CONFIG_TSEC3 1
556#define CONFIG_TSEC3_NAME "eTSEC3"
557
558#define CONFIG_PIXIS_SGMII_CMD
559#define CONFIG_FSL_SGMII_RISER 1
560#define SGMII_RISER_PHY_OFFSET 0x1b
561
562#ifdef CONFIG_FSL_SGMII_RISER
563#define CONFIG_SYS_TBIPA_VALUE 0x10
564#endif
565
566#define TSEC1_PHY_ADDR 0
567#define TSEC2_PHY_ADDR 1
568#define TSEC3_PHY_ADDR 2
569
570#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
571#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
572#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
573
574#define TSEC1_PHYIDX 0
575#define TSEC2_PHYIDX 0
576#define TSEC3_PHYIDX 0
577
578#define CONFIG_ETHPRIME "eTSEC1"
579
580#define CONFIG_PHY_GIGE 1
581#endif
582
583
584
585
586#define CONFIG_ENV_IS_IN_FLASH 1
587#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
588#define CONFIG_ENV_ADDR 0xfff80000
589#else
590#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
591#endif
592#define CONFIG_ENV_SIZE 0x2000
593#define CONFIG_ENV_SECT_SIZE 0x20000
594
595#define CONFIG_LOADS_ECHO 1
596#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
597
598
599
600
601#include <config_cmd_default.h>
602
603#define CONFIG_CMD_IRQ
604#define CONFIG_CMD_PING
605#define CONFIG_CMD_I2C
606#define CONFIG_CMD_MII
607#define CONFIG_CMD_ELF
608#define CONFIG_CMD_IRQ
609#define CONFIG_CMD_SETEXPR
610
611#if defined(CONFIG_PCI)
612#define CONFIG_CMD_PCI
613#define CONFIG_CMD_NET
614#define CONFIG_CMD_SCSI
615#define CONFIG_CMD_EXT2
616#endif
617
618
619
620
621#define CONFIG_CMD_USB
622#define CONFIG_USB_STORAGE
623#define CONFIG_USB_EHCI
624#define CONFIG_USB_EHCI_FSL
625#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
626
627#undef CONFIG_WATCHDOG
628
629
630
631
632#define CONFIG_SYS_LONGHELP
633#define CONFIG_CMDLINE_EDITING
634#define CONFIG_SYS_LOAD_ADDR 0x2000000
635#define CONFIG_SYS_PROMPT "=> "
636#if defined(CONFIG_CMD_KGDB)
637#define CONFIG_SYS_CBSIZE 1024
638#else
639#define CONFIG_SYS_CBSIZE 256
640#endif
641#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
642#define CONFIG_SYS_MAXARGS 16
643#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
644#define CONFIG_SYS_HZ 1000
645
646
647
648
649
650
651#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
652
653
654
655
656
657
658#define BOOTFLAG_COLD 0x01
659#define BOOTFLAG_WARM 0x02
660
661#if defined(CONFIG_CMD_KGDB)
662#define CONFIG_KGDB_BAUDRATE 230400
663#define CONFIG_KGDB_SER_INDEX 2
664#endif
665
666
667
668
669
670
671#if defined(CONFIG_TSEC_ENET)
672#define CONFIG_HAS_ETH0
673#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
674#define CONFIG_HAS_ETH1
675#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
676#define CONFIG_HAS_ETH2
677#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
678#define CONFIG_HAS_ETH3
679#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
680#endif
681
682#define CONFIG_IPADDR 192.168.1.254
683
684#define CONFIG_HOSTNAME unknown
685#define CONFIG_ROOTPATH /opt/nfsroot
686#define CONFIG_BOOTFILE uImage
687#define CONFIG_UBOOTPATH u-boot.bin
688
689#define CONFIG_SERVERIP 192.168.1.1
690#define CONFIG_GATEWAYIP 192.168.1.1
691#define CONFIG_NETMASK 255.255.255.0
692
693
694#define CONFIG_LOADADDR 1000000
695
696#define CONFIG_BOOTDELAY 10
697#undef CONFIG_BOOTARGS
698
699#define CONFIG_BAUDRATE 115200
700
701#define CONFIG_EXTRA_ENV_SETTINGS \
702 "perf_mode=stable\0" \
703 "memctl_intlv_ctl=2\0" \
704 "netdev=eth0\0" \
705 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
706 "tftpflash=tftpboot $loadaddr $uboot; " \
707 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
708 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
709 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
710 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
711 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
712 "consoledev=ttyS0\0" \
713 "ramdiskaddr=2000000\0" \
714 "ramdiskfile=p2020ds/ramdisk.uboot\0" \
715 "fdtaddr=c00000\0" \
716 "fdtfile=p2020ds/p2020ds.dtb\0" \
717 "bdev=sda3\0"
718
719#define CONFIG_HDBOOT \
720 "setenv bootargs root=/dev/$bdev rw " \
721 "console=$consoledev,$baudrate $othbootargs;" \
722 "tftp $loadaddr $bootfile;" \
723 "tftp $fdtaddr $fdtfile;" \
724 "bootm $loadaddr - $fdtaddr"
725
726#define CONFIG_NFSBOOTCOMMAND \
727 "setenv bootargs root=/dev/nfs rw " \
728 "nfsroot=$serverip:$rootpath " \
729 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
730 "console=$consoledev,$baudrate $othbootargs;" \
731 "tftp $loadaddr $bootfile;" \
732 "tftp $fdtaddr $fdtfile;" \
733 "bootm $loadaddr - $fdtaddr"
734
735#define CONFIG_RAMBOOTCOMMAND \
736 "setenv bootargs root=/dev/ram rw " \
737 "console=$consoledev,$baudrate $othbootargs;" \
738 "tftp $ramdiskaddr $ramdiskfile;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr $ramdiskaddr $fdtaddr"
742
743#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
744
745#endif
746