1/* 2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com> 3 * 4 * (C) Copyright 2004 5 * Texas Instruments. 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * Kshitij Gupta <kshitij@ti.com> 8 * 9 * Configuration settings for the Freescale i.MX31 PDK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* High Level Configuration Options */ 34#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ 35#define CONFIG_MX31 1 /* in a mx31 */ 36#define CONFIG_MX31_HCLK_FREQ 26000000 37#define CONFIG_MX31_CLK32 32768 38 39#define CONFIG_DISPLAY_CPUINFO 40#define CONFIG_DISPLAY_BOARDINFO 41 42#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 43#define CONFIG_SETUP_MEMORY_TAGS 1 44#define CONFIG_INITRD_TAG 1 45 46#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) 47#define CONFIG_SKIP_LOWLEVEL_INIT 48#define CONFIG_SKIP_RELOCATE_UBOOT 49#endif 50 51/* 52 * Size of malloc() pool 53 */ 54#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 55/* Bytes reserved for initial data */ 56#define CONFIG_SYS_GBL_DATA_SIZE 128 57 58/* 59 * Hardware drivers 60 */ 61 62#define CONFIG_MXC_UART 1 63#define CONFIG_SYS_MX31_UART1 1 64 65#define CONFIG_HARD_SPI 1 66#define CONFIG_MXC_SPI 1 67#define CONFIG_DEFAULT_SPI_BUS 1 68#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) 69 70#define CONFIG_RTC_MC13783 1 71 72/* MC13783 connected to CSPI2 and SS2 */ 73#define CONFIG_MC13783_SPI_BUS 1 74#define CONFIG_MC13783_SPI_CS 2 75 76/* allow to overwrite serial and ethaddr */ 77#define CONFIG_ENV_OVERWRITE 78#define CONFIG_CONS_INDEX 1 79#define CONFIG_BAUDRATE 115200 80#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} 81 82/*********************************************************** 83 * Command definition 84 ***********************************************************/ 85 86#include <config_cmd_default.h> 87 88#define CONFIG_CMD_MII 89#define CONFIG_CMD_PING 90#define CONFIG_CMD_SPI 91#define CONFIG_CMD_DATE 92 93/* 94 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require 95 * that CFG_NO_FLASH is undefined). 96 */ 97#undef CONFIG_CMD_IMLS 98 99#define CONFIG_BOOTDELAY 3 100 101#define CONFIG_EXTRA_ENV_SETTINGS \ 102 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 103 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 104 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 105 "bootcmd=run bootcmd_net\0" \ 106 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ 107 "tftpboot 0x81000000 uImage-mx31; bootm\0" 108 109#define CONFIG_NET_MULTI 110#define CONFIG_SMC911X 1 111#define CONFIG_SMC911X_BASE 0xB6000000 112#define CONFIG_SMC911X_32_BIT 1 113 114/* 115 * Miscellaneous configurable options 116 */ 117#define CONFIG_SYS_LONGHELP /* undef to save memory */ 118#define CONFIG_SYS_PROMPT "uboot> " 119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 120/* Print Buffer Size */ 121#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 122 sizeof(CONFIG_SYS_PROMPT)+16) 123/* max number of command args */ 124#define CONFIG_SYS_MAXARGS 16 125/* Boot Argument Buffer Size */ 126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 127 128/* memtest works on */ 129#define CONFIG_SYS_MEMTEST_START 0x80000000 130#define CONFIG_SYS_MEMTEST_END 0x10000 131 132/* default load address */ 133#define CONFIG_SYS_LOAD_ADDR 0x81000000 134 135#define CONFIG_SYS_HZ 1000 136 137#define CONFIG_CMDLINE_EDITING 1 138 139/*----------------------------------------------------------------------- 140 * Stack sizes 141 * 142 * The stack sizes are set up in start.S using the settings below 143 */ 144#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ 145 146/*----------------------------------------------------------------------- 147 * Physical Memory Map 148 */ 149#define CONFIG_NR_DRAM_BANKS 1 150#define PHYS_SDRAM_1 CSD0_BASE 151#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 152 153/*----------------------------------------------------------------------- 154 * FLASH and environment organization 155 */ 156/* No NOR flash present */ 157#define CONFIG_SYS_NO_FLASH 1 158 159#define CONFIG_ENV_IS_NOWHERE 1 160 161#define CONFIG_ENV_SIZE (128 * 1024) 162 163/* NAND configuration for the NAND_SPL */ 164 165/* Start copying real U-boot from the second page */ 166#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 167#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 168/* Load U-Boot to this address */ 169#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 170#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 171 172#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 173#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 174#define CONFIG_SYS_NAND_PAGE_COUNT 64 175#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 176#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 177 178 179/* Configuration of lowlevel_init.S (clocks and SDRAM) */ 180#define CCM_CCMR_SETUP 0x074B0BF5 181#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ 182 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ 183 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ 184 PDR0_MCU_PODF(0)) 185#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ 186 PLL_MFN(12)) 187 188#define ESDMISC_MDDR_SETUP 0x00000004 189#define ESDMISC_MDDR_RESET_DL 0x0000000c 190#define ESDCFG0_MDDR_SETUP 0x006ac73a 191 192#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) 193#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ 194 ESDCTL_DSIZ(2) | ESDCTL_BL(1)) 195#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) 196#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) 197#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) 198#define ESDCTL_RW ESDCTL_SETTINGS 199 200#endif /* __CONFIG_H */ 201