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24#ifndef __PPC4XX_H__
25#define __PPC4XX_H__
26
27
28
29
30#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
31 defined(CONFIG_AP1000) || defined(CONFIG_ML2)
32#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM
33#endif
34
35#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
36 defined(CONFIG_440EP) || defined(CONFIG_440GR)
37#define CONFIG_SDRAM_PPC4xx_IBM_DDR
38#endif
39
40#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
41#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2
42#endif
43
44#if defined(CONFIG_405EX) || \
45 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
46 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
47 defined(CONFIG_460SX)
48#define CONFIG_SDRAM_PPC4xx_IBM_DDR2
49#endif
50
51#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
52 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
53 defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
54 defined(CONFIG_460EX) || defined(CONFIG_460GT)
55#define CONFIG_NAND_NDFC
56#endif
57
58
59#if defined(CONFIG_405EX) || \
60 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
61 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
62 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
63 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
64 defined(CONFIG_460SX)
65
66#define PLB_ARBITER_BASE 0x80
67
68#define PLB0_ACR (PLB_ARBITER_BASE + 0x01)
69#define PLB0_ACR_PPM_MASK 0xF0000000
70#define PLB0_ACR_PPM_FIXED 0x00000000
71#define PLB0_ACR_PPM_FAIR 0xD0000000
72#define PLB0_ACR_HBU_MASK 0x08000000
73#define PLB0_ACR_HBU_DISABLED 0x00000000
74#define PLB0_ACR_HBU_ENABLED 0x08000000
75#define PLB0_ACR_RDP_MASK 0x06000000
76#define PLB0_ACR_RDP_DISABLED 0x00000000
77#define PLB0_ACR_RDP_2DEEP 0x02000000
78#define PLB0_ACR_RDP_3DEEP 0x04000000
79#define PLB0_ACR_RDP_4DEEP 0x06000000
80#define PLB0_ACR_WRP_MASK 0x01000000
81#define PLB0_ACR_WRP_DISABLED 0x00000000
82#define PLB0_ACR_WRP_2DEEP 0x01000000
83
84#define PLB1_ACR (PLB_ARBITER_BASE + 0x09)
85#define PLB1_ACR_PPM_MASK 0xF0000000
86#define PLB1_ACR_PPM_FIXED 0x00000000
87#define PLB1_ACR_PPM_FAIR 0xD0000000
88#define PLB1_ACR_HBU_MASK 0x08000000
89#define PLB1_ACR_HBU_DISABLED 0x00000000
90#define PLB1_ACR_HBU_ENABLED 0x08000000
91#define PLB1_ACR_RDP_MASK 0x06000000
92#define PLB1_ACR_RDP_DISABLED 0x00000000
93#define PLB1_ACR_RDP_2DEEP 0x02000000
94#define PLB1_ACR_RDP_3DEEP 0x04000000
95#define PLB1_ACR_RDP_4DEEP 0x06000000
96#define PLB1_ACR_WRP_MASK 0x01000000
97#define PLB1_ACR_WRP_DISABLED 0x00000000
98#define PLB1_ACR_WRP_2DEEP 0x01000000
99
100#endif
101
102#if defined(CONFIG_440)
103
104
105
106
107#define CONFIG_SYS_64BIT_VSPRINTF
108#define CONFIG_SYS_64BIT_STRTOUL
109#include <ppc440.h>
110#else
111#include <ppc405.h>
112#endif
113
114#include <asm/ppc4xx-sdram.h>
115#include <asm/ppc4xx-ebc.h>
116#if !defined(CONFIG_XILINX_440)
117#include <asm/ppc4xx-uic.h>
118#endif
119
120
121
122
123#define PPC_REG_BITS 32
124#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
125
126
127
128
129#ifndef __ASSEMBLY__
130#define static_cast(type, val) (type)(val)
131#else
132#define static_cast(type, val) (val)
133#endif
134
135
136
137
138
139#define EXC_OFF_SYS_RESET 0x0100
140#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
141
142#define RESET_VECTOR 0xfffffffc
143#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1)
144
145
146#define CPR0_DCR_BASE 0x0C
147#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
148#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
149
150#define SDR_DCR_BASE 0x0E
151#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
152#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
153
154#define SDRAM_DCR_BASE 0x10
155#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
156#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
157
158#define EBC_DCR_BASE 0x12
159#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
160#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
161
162
163
164
165#define mtcpr(reg, d) \
166 do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
167#define mfcpr(reg, d) \
168 do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
169
170#define mtebc(reg, d) \
171 do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
172#define mfebc(reg, d) \
173 do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
174
175#define mtsdram(reg, d) \
176 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
177#define mfsdram(reg, d) \
178 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
179
180#define mtsdr(reg, d) \
181 do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
182#define mfsdr(reg, d) \
183 do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
184
185#ifndef __ASSEMBLY__
186
187typedef struct
188{
189 unsigned long freqDDR;
190 unsigned long freqEBC;
191 unsigned long freqOPB;
192 unsigned long freqPCI;
193 unsigned long freqPLB;
194 unsigned long freqTmrClk;
195 unsigned long freqUART;
196 unsigned long freqProcessor;
197 unsigned long freqVCOHz;
198 unsigned long freqVCOMhz;
199 unsigned long pciClkSync;
200 unsigned long pciIntArbEn;
201 unsigned long pllExtBusDiv;
202 unsigned long pllFbkDiv;
203 unsigned long pllFwdDiv;
204 unsigned long pllFwdDivA;
205 unsigned long pllFwdDivB;
206 unsigned long pllOpbDiv;
207 unsigned long pllPciDiv;
208 unsigned long pllPlbDiv;
209} PPC4xx_SYS_INFO;
210
211static inline u32 get_mcsr(void)
212{
213 u32 val;
214
215 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
216 return val;
217}
218
219static inline void set_mcsr(u32 val)
220{
221 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
222}
223
224int ppc4xx_pci_sync_clock_config(u32 async);
225
226#endif
227
228
229#define NA_OR_UNKNOWN_CPU -1
230
231#endif
232