LXR uboot/board/esd/cpci750/mv

   1/*
   2 * (C) Copyright 2003
   3 * Ingo Assmus <ingo.assmus@keymile.com>
   4 *
   5 * based on - Driver for MV64360X ethernet ports
   6 * Copyright (C) 2002 rabeeh@galileo.co.il
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27/*
  28 * mv_eth.h - header file for the polled mode GT ethernet driver
  29 */
  30
  31#ifndef __DB64360_ETH_H__
  32#define __DB64360_ETH_H__
  33
  34#include <asm/types.h>
  35#include <asm/io.h>
  36#include <asm/byteorder.h>
  37#include <common.h>
  38#include <net.h>
  39#include "mv_regs.h"
  40#include <asm/errno.h>
  41
  42
  43/*************************************************************************
  44**************************************************************************
  45**************************************************************************
  46*  The first part is the high level driver of the gigE ethernet ports.   *
  47**************************************************************************
  48**************************************************************************
  49*************************************************************************/
  50#ifndef TRUE
  51#define TRUE 1
  52#endif
  53#ifndef FALSE
  54#define FALSE 0
  55#endif
  56
  57/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
  58#ifndef MAX_SKB_FRAGS
  59#define MAX_SKB_FRAGS 0
  60#endif
  61
  62/* Port attributes */
  63/*#define MAX_RX_QUEUE_NUM      8*/
  64/*#define MAX_TX_QUEUE_NUM      8*/
  65#define MAX_RX_QUEUE_NUM        1
  66#define MAX_TX_QUEUE_NUM        1
  67
  68
  69/* Use one TX queue and one RX queue */
  70#define MV64360_TX_QUEUE_NUM 1
  71#define MV64360_RX_QUEUE_NUM 1
  72
  73/*
  74 * Number of RX / TX descriptors on RX / TX rings.
  75 * Note that allocating RX descriptors is done by allocating the RX
  76 * ring AND a preallocated RX buffers (skb's) for each descriptor.
  77 * The TX descriptors only allocates the TX descriptors ring,
  78 * with no pre allocated TX buffers (skb's are allocated by higher layers.
  79 */
  80
  81/* Default TX ring size is 10 descriptors */
  82#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
  83#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
  84#else
  85#define MV64360_TX_QUEUE_SIZE 4
  86#endif
  87
  88/* Default RX ring size is 4 descriptors */
  89#ifdef  CONFIG_MV64360_ETH_RXQUEUE_SIZE
  90#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
  91#else
  92#define MV64360_RX_QUEUE_SIZE 4
  93#endif
  94
  95#ifdef CONFIG_RX_BUFFER_SIZE
  96#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
  97#else
  98#define MV64360_RX_BUFFER_SIZE 1600
  99#endif
 100
 101#ifdef CONFIG_TX_BUFFER_SIZE
 102#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
 103#else
 104#define MV64360_TX_BUFFER_SIZE 1600
 105#endif
 106
 107
 108/*
 109 *      Network device statistics. Akin to the 2.0 ether stats but
 110 *      with byte counters.
 111 */
 112
 113struct net_device_stats
 114{
 115        unsigned long   rx_packets;             /* total packets received       */
 116        unsigned long   tx_packets;             /* total packets transmitted    */
 117        unsigned long   rx_bytes;               /* total bytes received         */
 118        unsigned long   tx_bytes;               /* total bytes transmitted      */
 119        unsigned long   rx_errors;              /* bad packets received         */
 120        unsigned long   tx_errors;              /* packet transmit problems     */
 121        unsigned long   rx_dropped;             /* no space in linux buffers    */
 122        unsigned long   tx_dropped;             /* no space available in linux  */
 123        unsigned long   multicast;              /* multicast packets received   */
 124        unsigned long   collisions;
 125
 126        /* detailed rx_errors: */
 127        unsigned long   rx_length_errors;
 128        unsigned long   rx_over_errors;         /* receiver ring buff overflow  */
 129        unsigned long   rx_crc_errors;          /* recved pkt with crc error    */
 130        unsigned long   rx_frame_errors;        /* recv'd frame alignment error */
 131        unsigned long   rx_fifo_errors;         /* recv'r fifo overrun          */
 132        unsigned long   rx_missed_errors;       /* receiver missed packet       */
 133
 134        /* detailed tx_errors */
 135        unsigned long   tx_aborted_errors;
 136        unsigned long   tx_carrier_errors;
 137        unsigned long   tx_fifo_errors;
 138        unsigned long   tx_heartbeat_errors;
 139        unsigned long   tx_window_errors;
 140
 141        /* for cslip etc */
 142        unsigned long   rx_compressed;
 143        unsigned long   tx_compressed;
 144};
 145
 146
 147/* Private data structure used for ethernet device */
 148struct mv64360_eth_priv {
 149    unsigned int port_num;
 150    struct net_device_stats *stats;
 151
 152/* to buffer area aligned */
 153    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];    /*pointers to alligned tx buffs in memory space */
 154    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];    /*pointers to allinged rx buffs in memory space */
 155
 156    /* Size of Tx Ring per queue */
 157    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
 158
 159
 160    /* Size of Rx Ring per queue */
 161    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
 162
 163    /* Magic Number for Ethernet running */
 164    unsigned int eth_running;
 165
 166};
 167
 168
 169int mv64360_eth_init (struct eth_device *dev);
 170int mv64360_eth_stop (struct eth_device *dev);
 171int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
 172/*      return db64360_eth0_poll(); */
 173
 174int mv64360_eth_open (struct eth_device *dev);
 175
 176
 177/*************************************************************************
 178**************************************************************************
 179**************************************************************************
 180*  The second part is the low level driver of the gigE ethernet ports.   *
 181**************************************************************************
 182**************************************************************************
 183*************************************************************************/
 184
 185
 186/********************************************************************************
 187 * Header File for : MV-643xx network interface header
 188 *
 189 * DESCRIPTION:
 190 *       This header file contains macros typedefs and function declaration for
 191 *       the Marvell Gig Bit Ethernet Controller.
 192 *
 193 * DEPENDENCIES:
 194 *       None.
 195 *
 196 *******************************************************************************/
 197
 198
 199#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
 200#ifdef CONFIG_MV64360_SRAM_CACHEABLE
 201/* In case SRAM is cacheable but not cache coherent */
 202#define D_CACHE_FLUSH_LINE(addr, offset)       \
 203{                   \
 204  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
 205}
 206#else
 207/* In case SRAM is cache coherent or non-cacheable */
 208#define D_CACHE_FLUSH_LINE(addr, offset) ;
 209#endif
 210#else
 211#ifdef CONFIG_NOT_COHERENT_CACHE
 212/* In case of descriptors on DDR but not cache coherent */
 213#define D_CACHE_FLUSH_LINE(addr, offset)       \
 214{                   \
 215  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
 216}
 217#else
 218/* In case of descriptors on DDR and cache coherent */
 219#define D_CACHE_FLUSH_LINE(addr, offset) ;
 220#endif /* CONFIG_NOT_COHERENT_CACHE */
 221#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
 222
 223
 224#define CPU_PIPE_FLUSH             \
 225{                 \
 226  __asm__ __volatile__ ("eieio");         \
 227}
 228
 229
 230/* defines  */
 231
 232/* Default port configuration value */
 233#define PORT_CONFIG_VALUE                       \
 234             ETH_UNICAST_NORMAL_MODE            |   \
 235             ETH_DEFAULT_RX_QUEUE_0             |   \
 236             ETH_DEFAULT_RX_ARP_QUEUE_0         |   \
 237             ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP    |   \
 238             ETH_RECEIVE_BC_IF_IP               |   \
 239             ETH_RECEIVE_BC_IF_ARP              |   \
 240             ETH_CAPTURE_TCP_FRAMES_DIS         |   \
 241             ETH_CAPTURE_UDP_FRAMES_DIS         |   \
 242             ETH_DEFAULT_RX_TCP_QUEUE_0         |   \
 243             ETH_DEFAULT_RX_UDP_QUEUE_0         |   \
 244             ETH_DEFAULT_RX_BPDU_QUEUE_0
 245
 246/* Default port extend configuration value */
 247#define PORT_CONFIG_EXTEND_VALUE                \
 248             ETH_SPAN_BPDU_PACKETS_AS_NORMAL    |   \
 249             ETH_PARTITION_DISABLE
 250
 251
 252/* Default sdma control value */
 253#ifdef CONFIG_NOT_COHERENT_CACHE
 254#define PORT_SDMA_CONFIG_VALUE                          \
 255                         ETH_RX_BURST_SIZE_16_64BIT     |       \
 256                         GT_ETH_IPG_INT_RX(0)                   |       \
 257                         ETH_TX_BURST_SIZE_16_64BIT;
 258#else
 259#define PORT_SDMA_CONFIG_VALUE                  \
 260                         ETH_RX_BURST_SIZE_4_64BIT      |       \
 261                         GT_ETH_IPG_INT_RX(0)                   |       \
 262                         ETH_TX_BURST_SIZE_4_64BIT;
 263#endif
 264
 265#define GT_ETH_IPG_INT_RX(value)                \
 266            ((value & 0x3fff) << 8)
 267
 268/* Default port serial control value */
 269#define PORT_SERIAL_CONTROL_VALUE                           \
 270                        ETH_FORCE_LINK_PASS                     |       \
 271                        ETH_ENABLE_AUTO_NEG_FOR_DUPLX           |       \
 272                        ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL      |       \
 273                        ETH_ADV_SYMMETRIC_FLOW_CTRL             |       \
 274                        ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX       |       \
 275                        ETH_FORCE_BP_MODE_NO_JAM                |       \
 276                        BIT9                                    |       \
 277                        ETH_DO_NOT_FORCE_LINK_FAIL              |       \
 278                        ETH_RETRANSMIT_16_ETTEMPTS              |       \
 279                        ETH_ENABLE_AUTO_NEG_SPEED_GMII          |       \
 280                        ETH_DTE_ADV_0                           |       \
 281                        ETH_DISABLE_AUTO_NEG_BYPASS             |       \
 282                        ETH_AUTO_NEG_NO_CHANGE                  |       \
 283                        ETH_MAX_RX_PACKET_1552BYTE              |       \
 284                        ETH_CLR_EXT_LOOPBACK                    |       \
 285                        ETH_SET_FULL_DUPLEX_MODE                |       \
 286                        ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
 287
 288#define RX_BUFFER_MAX_SIZE  0xFFFF
 289#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
 290
 291#define RX_BUFFER_MIN_SIZE  0x8
 292#define TX_BUFFER_MIN_SIZE  0x8
 293
 294/* Tx WRR confoguration macros */
 295#define PORT_MAX_TRAN_UNIT          0x24    /* MTU register (default) 9KByte */
 296#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
 297#define PORT_TOKEN_RATE             1023    /* PTTBRC register (default)     */
 298
 299/* MAC accepet/reject macros */
 300#define ACCEPT_MAC_ADDR     0
 301#define REJECT_MAC_ADDR     1
 302
 303/* Size of a Tx/Rx descriptor used in chain list data structure */
 304#define RX_DESC_ALIGNED_SIZE            0x20
 305#define TX_DESC_ALIGNED_SIZE            0x20
 306
 307/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
 308#define TX_BUF_OFFSET_IN_DESC       0x18
 309/* Buffer offset from buffer pointer */
 310#define RX_BUF_OFFSET                           0x2
 311
 312/* Gap define */
 313#define ETH_BAR_GAP                                     0x8
 314#define ETH_SIZE_REG_GAP                                0x8
 315#define ETH_HIGH_ADDR_REMAP_REG_GAP                     0x4
 316#define ETH_PORT_ACCESS_CTRL_GAP                        0x4
 317
 318/* Gigabit Ethernet Unit Global Registers */
 319
 320/* MIB Counters register definitions */
 321#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
 322#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
 323#define ETH_MIB_BAD_OCTETS_RECEIVED        0x8
 324#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
 325#define ETH_MIB_GOOD_FRAMES_RECEIVED       0x10
 326#define ETH_MIB_BAD_FRAMES_RECEIVED        0x14
 327#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
 328#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
 329#define ETH_MIB_FRAMES_64_OCTETS           0x20
 330#define ETH_MIB_FRAMES_65_TO_127_OCTETS    0x24
 331#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
 332#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
 333#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
 334#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
 335#define ETH_MIB_GOOD_OCTETS_SENT_LOW       0x38
 336#define ETH_MIB_GOOD_OCTETS_SENT_HIGH      0x3c
 337#define ETH_MIB_GOOD_FRAMES_SENT           0x40
 338#define ETH_MIB_EXCESSIVE_COLLISION        0x44
 339#define ETH_MIB_MULTICAST_FRAMES_SENT      0x48
 340#define ETH_MIB_BROADCAST_FRAMES_SENT      0x4c
 341#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
 342#define ETH_MIB_FC_SENT                    0x54
 343#define ETH_MIB_GOOD_FC_RECEIVED           0x58
 344#define ETH_MIB_BAD_FC_RECEIVED            0x5c
 345#define ETH_MIB_UNDERSIZE_RECEIVED         0x60
 346#define ETH_MIB_FRAGMENTS_RECEIVED         0x64
 347#define ETH_MIB_OVERSIZE_RECEIVED          0x68
 348#define ETH_MIB_JABBER_RECEIVED            0x6c
 349#define ETH_MIB_MAC_RECEIVE_ERROR          0x70
 350#define ETH_MIB_BAD_CRC_EVENT              0x74
 351#define ETH_MIB_COLLISION                  0x78
 352#define ETH_MIB_LATE_COLLISION             0x7c
 353
 354/* Port serial status reg (PSR) */
 355#define ETH_INTERFACE_GMII_MII                          0
 356#define ETH_INTERFACE_PCM                               BIT0
 357#define ETH_LINK_IS_DOWN                                0
 358#define ETH_LINK_IS_UP                                  BIT1
 359#define ETH_PORT_AT_HALF_DUPLEX                         0
 360#define ETH_PORT_AT_FULL_DUPLEX                         BIT2
 361#define ETH_RX_FLOW_CTRL_DISABLED                       0
 362#define ETH_RX_FLOW_CTRL_ENBALED                        BIT3
 363#define ETH_GMII_SPEED_100_10                           0
 364#define ETH_GMII_SPEED_1000                             BIT4
 365#define ETH_MII_SPEED_10                                0
 366#define ETH_MII_SPEED_100                               BIT5
 367#define ETH_NO_TX                                       0
 368#define ETH_TX_IN_PROGRESS                              BIT7
 369#define ETH_BYPASS_NO_ACTIVE                            0
 370#define ETH_BYPASS_ACTIVE                               BIT8
 371#define ETH_PORT_NOT_AT_PARTITION_STATE                 0
 372#define ETH_PORT_AT_PARTITION_STATE                     BIT9
 373#define ETH_PORT_TX_FIFO_NOT_EMPTY                      0
 374#define ETH_PORT_TX_FIFO_EMPTY                          BIT10
 375
 376
 377/* These macros describes the Port configuration reg (Px_cR) bits */
 378#define ETH_UNICAST_NORMAL_MODE                         0
 379#define ETH_UNICAST_PROMISCUOUS_MODE                    BIT0
 380#define ETH_DEFAULT_RX_QUEUE_0                          0
 381#define ETH_DEFAULT_RX_QUEUE_1                          BIT1
 382#define ETH_DEFAULT_RX_QUEUE_2                          BIT2
 383#define ETH_DEFAULT_RX_QUEUE_3                          (BIT2 | BIT1)
 384#define ETH_DEFAULT_RX_QUEUE_4                          BIT3
 385#define ETH_DEFAULT_RX_QUEUE_5                          (BIT3 | BIT1)
 386#define ETH_DEFAULT_RX_QUEUE_6                          (BIT3 | BIT2)
 387#define ETH_DEFAULT_RX_QUEUE_7                          (BIT3 | BIT2 | BIT1)
 388#define ETH_DEFAULT_RX_ARP_QUEUE_0                      0
 389#define ETH_DEFAULT_RX_ARP_QUEUE_1                      BIT4
 390#define ETH_DEFAULT_RX_ARP_QUEUE_2                      BIT5
 391#define ETH_DEFAULT_RX_ARP_QUEUE_3                      (BIT5 | BIT4)
 392#define ETH_DEFAULT_RX_ARP_QUEUE_4                      BIT6
 393#define ETH_DEFAULT_RX_ARP_QUEUE_5                      (BIT6 | BIT4)
 394#define ETH_DEFAULT_RX_ARP_QUEUE_6                      (BIT6 | BIT5)
 395#define ETH_DEFAULT_RX_ARP_QUEUE_7                      (BIT6 | BIT5 | BIT4)
 396#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP                 0
 397#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP                  BIT7
 398#define ETH_RECEIVE_BC_IF_IP                            0
 399#define ETH_REJECT_BC_IF_IP                             BIT8
 400#define ETH_RECEIVE_BC_IF_ARP                           0
 401#define ETH_REJECT_BC_IF_ARP                            BIT9
 402#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY               BIT12
 403#define ETH_CAPTURE_TCP_FRAMES_DIS                      0
 404#define ETH_CAPTURE_TCP_FRAMES_EN                       BIT14
 405#define ETH_CAPTURE_UDP_FRAMES_DIS                      0
 406#define ETH_CAPTURE_UDP_FRAMES_EN                       BIT15
 407#define ETH_DEFAULT_RX_TCP_QUEUE_0                      0
 408#define ETH_DEFAULT_RX_TCP_QUEUE_1                      BIT16
 409#define ETH_DEFAULT_RX_TCP_QUEUE_2                      BIT17
 410#define ETH_DEFAULT_RX_TCP_QUEUE_3                      (BIT17 | BIT16)
 411#define ETH_DEFAULT_RX_TCP_QUEUE_4                      BIT18
 412#define ETH_DEFAULT_RX_TCP_QUEUE_5                      (BIT18 | BIT16)
 413#define ETH_DEFAULT_RX_TCP_QUEUE_6                      (BIT18 | BIT17)
 414#define ETH_DEFAULT_RX_TCP_QUEUE_7                      (BIT18 | BIT17 | BIT16)
 415#define ETH_DEFAULT_RX_UDP_QUEUE_0                      0
 416#define ETH_DEFAULT_RX_UDP_QUEUE_1                      BIT19
 417#define ETH_DEFAULT_RX_UDP_QUEUE_2                      BIT20
 418#define ETH_DEFAULT_RX_UDP_QUEUE_3                      (BIT20 | BIT19)
 419#define ETH_DEFAULT_RX_UDP_QUEUE_4                      (BIT21
 420#define ETH_DEFAULT_RX_UDP_QUEUE_5                      (BIT21 | BIT19)
 421#define ETH_DEFAULT_RX_UDP_QUEUE_6                      (BIT21 | BIT20)
 422#define ETH_DEFAULT_RX_UDP_QUEUE_7                      (BIT21 | BIT20 | BIT19)
 423#define ETH_DEFAULT_RX_BPDU_QUEUE_0                      0
 424#define ETH_DEFAULT_RX_BPDU_QUEUE_1                     BIT22
 425#define ETH_DEFAULT_RX_BPDU_QUEUE_2                     BIT23
 426#define ETH_DEFAULT_RX_BPDU_QUEUE_3                     (BIT23 | BIT22)
 427#define ETH_DEFAULT_RX_BPDU_QUEUE_4                     BIT24
 428#define ETH_DEFAULT_RX_BPDU_QUEUE_5                     (BIT24 | BIT22)
 429#define ETH_DEFAULT_RX_BPDU_QUEUE_6                     (BIT24 | BIT23)
 430#define ETH_DEFAULT_RX_BPDU_QUEUE_7                     (BIT24 | BIT23 | BIT22)
 431
 432
 433/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
 434#define ETH_CLASSIFY_EN                                 BIT0
 435#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL                 0
 436#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7             BIT1
 437#define ETH_PARTITION_DISABLE                           0
 438#define ETH_PARTITION_ENABLE                            BIT2
 439
 440
 441/* Tx/Rx queue command reg (RQCR/TQCR)*/
 442#define ETH_QUEUE_0_ENABLE                              BIT0
 443#define ETH_QUEUE_1_ENABLE                              BIT1
 444#define ETH_QUEUE_2_ENABLE                              BIT2
 445#define ETH_QUEUE_3_ENABLE                              BIT3
 446#define ETH_QUEUE_4_ENABLE                              BIT4
 447#define ETH_QUEUE_5_ENABLE                              BIT5
 448#define ETH_QUEUE_6_ENABLE                              BIT6
 449#define ETH_QUEUE_7_ENABLE                              BIT7
 450#define ETH_QUEUE_0_DISABLE                             BIT8
 451#define ETH_QUEUE_1_DISABLE                             BIT9
 452#define ETH_QUEUE_2_DISABLE                             BIT10
 453#define ETH_QUEUE_3_DISABLE                             BIT11
 454#define ETH_QUEUE_4_DISABLE                             BIT12
 455#define ETH_QUEUE_5_DISABLE                             BIT13
 456#define ETH_QUEUE_6_DISABLE                             BIT14
 457#define ETH_QUEUE_7_DISABLE                             BIT15
 458
 459
 460/* These macros describes the Port Sdma configuration reg (SDCR) bits */
 461#define ETH_RIFB                                        BIT0
 462#define ETH_RX_BURST_SIZE_1_64BIT                       0
 463#define ETH_RX_BURST_SIZE_2_64BIT                       BIT1
 464#define ETH_RX_BURST_SIZE_4_64BIT                       BIT2
 465#define ETH_RX_BURST_SIZE_8_64BIT                       (BIT2 | BIT1)
 466#define ETH_RX_BURST_SIZE_16_64BIT                      BIT3
 467#define ETH_BLM_RX_NO_SWAP                              BIT4
 468#define ETH_BLM_RX_BYTE_SWAP                            0
 469#define ETH_BLM_TX_NO_SWAP                              BIT5
 470#define ETH_BLM_TX_BYTE_SWAP                            0
 471#define ETH_DESCRIPTORS_BYTE_SWAP                       BIT6
 472#define ETH_DESCRIPTORS_NO_SWAP                         0
 473#define ETH_TX_BURST_SIZE_1_64BIT                       0
 474#define ETH_TX_BURST_SIZE_2_64BIT                       BIT22
 475#define ETH_TX_BURST_SIZE_4_64BIT                       BIT23
 476#define ETH_TX_BURST_SIZE_8_64BIT                       (BIT23 | BIT22)
 477#define ETH_TX_BURST_SIZE_16_64BIT                      BIT24
 478
 479
 480/* These macros describes the Port serial control reg (PSCR) bits */
 481#define ETH_SERIAL_PORT_DISABLE                         0
 482#define ETH_SERIAL_PORT_ENABLE                          BIT0
 483#define ETH_FORCE_LINK_PASS                             BIT1
 484#define ETH_DO_NOT_FORCE_LINK_PASS                      0
 485#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX                   0
 486#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX                  BIT2
 487#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL               0
 488#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL              BIT3
 489#define ETH_ADV_NO_FLOW_CTRL                            0
 490#define ETH_ADV_SYMMETRIC_FLOW_CTRL                     BIT4
 491#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX               0
 492#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS                  BIT5
 493#define ETH_FORCE_BP_MODE_NO_JAM                        0
 494#define ETH_FORCE_BP_MODE_JAM_TX                        BIT7
 495#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR              BIT8
 496#define ETH_FORCE_LINK_FAIL                             0
 497#define ETH_DO_NOT_FORCE_LINK_FAIL                      BIT10
 498#define ETH_RETRANSMIT_16_ETTEMPTS                      0
 499#define ETH_RETRANSMIT_FOREVER                          BIT11
 500#define ETH_DISABLE_AUTO_NEG_SPEED_GMII                 BIT13
 501#define ETH_ENABLE_AUTO_NEG_SPEED_GMII                  0
 502#define ETH_DTE_ADV_0                                   0
 503#define ETH_DTE_ADV_1                                   BIT14
 504#define ETH_DISABLE_AUTO_NEG_BYPASS                     0
 505#define ETH_ENABLE_AUTO_NEG_BYPASS                      BIT15
 506#define ETH_AUTO_NEG_NO_CHANGE                          0
 507#define ETH_RESTART_AUTO_NEG                            BIT16
 508#define ETH_MAX_RX_PACKET_1518BYTE                      0
 509#define ETH_MAX_RX_PACKET_1522BYTE                      BIT17
 510#define ETH_MAX_RX_PACKET_1552BYTE                      BIT18
 511#define ETH_MAX_RX_PACKET_9022BYTE                      (BIT18 | BIT17)
 512#define ETH_MAX_RX_PACKET_9192BYTE                      BIT19
 513#define ETH_MAX_RX_PACKET_9700BYTE                      (BIT19 | BIT17)
 514#define ETH_SET_EXT_LOOPBACK                            BIT20
 515#define ETH_CLR_EXT_LOOPBACK                            0
 516#define ETH_SET_FULL_DUPLEX_MODE                        BIT21
 517#define ETH_SET_HALF_DUPLEX_MODE                        0
 518#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX       BIT22
 519#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX      0
 520#define ETH_SET_GMII_SPEED_TO_10_100                    0
 521#define ETH_SET_GMII_SPEED_TO_1000                      BIT23
 522#define ETH_SET_MII_SPEED_TO_10                         0
 523#define ETH_SET_MII_SPEED_TO_100                        BIT24
 524
 525
 526/* SMI reg */
 527#define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
 528#define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
 529#define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
 530#define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress             */
 531
 532/* SDMA command status fields macros */
 533
 534/* Tx & Rx descriptors status */
 535#define ETH_ERROR_SUMMARY                   (BIT0)
 536
 537/* Tx & Rx descriptors command */
 538#define ETH_BUFFER_OWNED_BY_DMA             (BIT31)
 539
 540/* Tx descriptors status */
 541#define ETH_LC_ERROR                        (0    )
 542#define ETH_UR_ERROR                        (BIT1 )
 543#define ETH_RL_ERROR                        (BIT2 )
 544#define ETH_LLC_SNAP_FORMAT                 (BIT9 )
 545
 546/* Rx descriptors status */
 547#define ETH_CRC_ERROR                       (0    )
 548#define ETH_OVERRUN_ERROR                   (BIT1 )
 549#define ETH_MAX_FRAME_LENGTH_ERROR          (BIT2 )
 550#define ETH_RESOURCE_ERROR                  ((BIT2 | BIT1))
 551#define ETH_VLAN_TAGGED                     (BIT19)
 552#define ETH_BPDU_FRAME                      (BIT20)
 553#define ETH_TCP_FRAME_OVER_IP_V_4           (0    )
 554#define ETH_UDP_FRAME_OVER_IP_V_4           (BIT21)
 555#define ETH_OTHER_FRAME_TYPE                (BIT22)
 556#define ETH_LAYER_2_IS_ETH_V_2              (BIT23)
 557#define ETH_FRAME_TYPE_IP_V_4               (BIT24)
 558#define ETH_FRAME_HEADER_OK                 (BIT25)
 559#define ETH_RX_LAST_DESC                    (BIT26)
 560#define ETH_RX_FIRST_DESC                   (BIT27)
 561#define ETH_UNKNOWN_DESTINATION_ADDR        (BIT28)
 562#define ETH_RX_ENABLE_INTERRUPT             (BIT29)
 563#define ETH_LAYER_4_CHECKSUM_OK             (BIT30)
 564
 565/* Rx descriptors byte count */
 566#define ETH_FRAME_FRAGMENTED                (BIT2)
 567
 568/* Tx descriptors command */
 569#define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
 570#define ETH_FRAME_SET_TO_VLAN               (BIT15)
 571#define ETH_TCP_FRAME                       (0    )
 572#define ETH_UDP_FRAME                       (BIT16)
 573#define ETH_GEN_TCP_UDP_CHECKSUM            (BIT17)
 574#define ETH_GEN_IP_V_4_CHECKSUM             (BIT18)
 575#define ETH_ZERO_PADDING                    (BIT19)
 576#define ETH_TX_LAST_DESC                    (BIT20)
 577#define ETH_TX_FIRST_DESC                   (BIT21)
 578#define ETH_GEN_CRC                         (BIT22)
 579#define ETH_TX_ENABLE_INTERRUPT             (BIT23)
 580#define ETH_AUTO_MODE                       (BIT30)
 581
 582/* Address decode parameters */
 583/* Ethernet Base Address Register bits */
 584#define EBAR_TARGET_DRAM                                        0x00000000
 585#define EBAR_TARGET_DEVICE                                      0x00000001
 586#define EBAR_TARGET_CBS                                         0x00000002
 587#define EBAR_TARGET_PCI0                                        0x00000003
 588#define EBAR_TARGET_PCI1                                        0x00000004
 589#define EBAR_TARGET_CUNIT                                       0x00000005
 590#define EBAR_TARGET_AUNIT                                       0x00000006
 591#define EBAR_TARGET_GUNIT                                       0x00000007
 592
 593/* Window attributes */
 594#define EBAR_ATTR_DRAM_CS0                                      0x00000E00
 595#define EBAR_ATTR_DRAM_CS1                                      0x00000D00
 596#define EBAR_ATTR_DRAM_CS2                                      0x00000B00
 597#define EBAR_ATTR_DRAM_CS3                                      0x00000700
 598
 599/* DRAM Target interface */
 600#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY       0x00000000
 601#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT       0x00001000
 602#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB       0x00002000
 603
 604/* Device Bus Target interface */
 605#define EBAR_ATTR_DEVICE_DEVCS0                         0x00001E00
 606#define EBAR_ATTR_DEVICE_DEVCS1                         0x00001D00
 607#define EBAR_ATTR_DEVICE_DEVCS2                         0x00001B00
 608#define EBAR_ATTR_DEVICE_DEVCS3                         0x00001700
 609#define EBAR_ATTR_DEVICE_BOOTCS3                        0x00000F00
 610
 611/* PCI Target interface */
 612#define EBAR_ATTR_PCI_BYTE_SWAP                         0x00000000
 613#define EBAR_ATTR_PCI_NO_SWAP                           0x00000100
 614#define EBAR_ATTR_PCI_BYTE_WORD_SWAP            0x00000200
 615#define EBAR_ATTR_PCI_WORD_SWAP                         0x00000300
 616#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT       0x00000000
 617#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT           0x00000400
 618#define EBAR_ATTR_PCI_IO_SPACE                          0x00000000
 619#define EBAR_ATTR_PCI_MEMORY_SPACE                      0x00000800
 620#define EBAR_ATTR_PCI_REQ64_FORCE                       0x00000000
 621#define EBAR_ATTR_PCI_REQ64_SIZE                        0x00001000
 622
 623/* CPU 60x bus or internal SRAM interface */
 624#define EBAR_ATTR_CBS_SRAM_BLOCK0                       0x00000000
 625#define EBAR_ATTR_CBS_SRAM_BLOCK1                       0x00000100
 626#define EBAR_ATTR_CBS_SRAM                                      0x00000000
 627#define EBAR_ATTR_CBS_CPU_BUS                           0x00000800
 628
 629/* Window access control */
 630#define EWIN_ACCESS_NOT_ALLOWED 0
 631#define EWIN_ACCESS_READ_ONLY   BIT0
 632#define EWIN_ACCESS_FULL        (BIT1 | BIT0)
 633#define EWIN0_ACCESS_MASK               0x0003
 634#define EWIN1_ACCESS_MASK               0x000C
 635#define EWIN2_ACCESS_MASK               0x0030
 636#define EWIN3_ACCESS_MASK               0x00C0
 637
 638/* typedefs */
 639
 640typedef enum _eth_port
 641{
 642    ETH_0 = 0,
 643        ETH_1 = 1,
 644        ETH_2 = 2
 645}ETH_PORT;
 646
 647typedef enum _eth_func_ret_status
 648{
 649    ETH_OK,                     /* Returned as expected.                    */
 650    ETH_ERROR,                  /* Fundamental error.                       */
 651    ETH_RETRY,                  /* Could not process request. Try later.    */
 652    ETH_END_OF_JOB,             /* Ring has nothing to process.             */
 653    ETH_QUEUE_FULL,             /* Ring resource error.                     */
 654    ETH_QUEUE_LAST_RESOURCE     /* Ring resources about to exhaust.         */
 655}ETH_FUNC_RET_STATUS;
 656
 657typedef enum _eth_queue
 658{
 659        ETH_Q0 = 0,
 660        ETH_Q1 = 1,
 661        ETH_Q2 = 2,
 662        ETH_Q3 = 3,
 663        ETH_Q4 = 4,
 664        ETH_Q5 = 5,
 665        ETH_Q6 = 6,
 666    ETH_Q7 = 7
 667} ETH_QUEUE;
 668
 669typedef enum _addr_win
 670{
 671        ETH_WIN0,
 672        ETH_WIN1,
 673        ETH_WIN2,
 674        ETH_WIN3,
 675        ETH_WIN4,
 676    ETH_WIN5
 677} ETH_ADDR_WIN;
 678
 679typedef enum _eth_target
 680{
 681        ETH_TARGET_DRAM  ,
 682        ETH_TARGET_DEVICE,
 683        ETH_TARGET_CBS   ,
 684        ETH_TARGET_PCI0  ,
 685        ETH_TARGET_PCI1
 686}ETH_TARGET;
 687
 688typedef struct _eth_rx_desc
 689{
 690        unsigned short  byte_cnt           ;    /* Descriptor buffer byte count     */
 691        unsigned short  buf_size           ;    /* Buffer size                      */
 692        unsigned int    cmd_sts    ;    /* Descriptor command status        */
 693        unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
 694        unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
 695    unsigned int    return_info ;    /* User resource return information */
 696} ETH_RX_DESC;
 697
 698
 699typedef struct _eth_tx_desc
 700{
 701    unsigned short  byte_cnt       ;    /* Descriptor buffer byte count     */
 702    unsigned short  l4i_chk        ;    /* CPU provided TCP Checksum        */
 703    unsigned int    cmd_sts        ;    /* Descriptor command status        */
 704    unsigned int    next_desc_ptr;    /* Next descriptor pointer          */
 705    unsigned int    buf_ptr        ;    /* Descriptor buffer pointer        */
 706    unsigned int    return_info ;    /* User resource return information */
 707} ETH_TX_DESC;
 708
 709/* Unified struct for Rx and Tx operations. The user is not required to */
 710/* be familier with neither Tx nor Rx descriptors.                       */
 711typedef struct _pkt_info
 712{
 713        unsigned short  byte_cnt   ;    /* Descriptor buffer byte count     */
 714        unsigned short  l4i_chk    ;    /* Tx CPU provided TCP Checksum     */
 715        unsigned int    cmd_sts    ;    /* Descriptor command status        */
 716        unsigned int    buf_ptr    ;    /* Descriptor buffer pointer        */
 717    unsigned int    return_info ;    /* User resource return information */
 718} PKT_INFO;
 719
 720
 721typedef struct _eth_win_param
 722{
 723    ETH_ADDR_WIN win;   /* Window number. See ETH_ADDR_WIN enum */
 724    ETH_TARGET  target;    /* System targets. See ETH_TARGET enum */
 725    unsigned short attributes;  /* BAR attributes. See above macros. */
 726    unsigned int base_addr; /* Window base address in unsigned int form */
 727    unsigned int high_addr; /* Window high address in unsigned int form */
 728    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
 729    bool enable; /* Enable/disable access to the window. */
 730    unsigned short access_ctrl; /* Access ctrl register. see above macros */
 731} ETH_WIN_PARAM;
 732
 733
 734/* Ethernet port specific infomation */
 735
 736typedef struct _eth_port_ctrl
 737{
 738    ETH_PORT  port_num; /* User Ethernet port number */
 739    int port_phy_addr;  /* User phy address of Ethrnet port */
 740    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
 741    unsigned int  port_config; /* User port configuration value */
 742    unsigned int  port_config_extend; /* User port config extend value */
 743    unsigned int  port_sdma_config; /* User port SDMA config value */
 744    unsigned int  port_serial_control; /* User port serial control value */
 745    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
 746    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
 747
 748    /* User function to cast virtual address to CPU bus address */
 749    unsigned int  (*port_virt_to_phys)(unsigned int addr);
 750    /* User scratch pad for user specific data structures */
 751    void *port_private;
 752
 753    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
 754    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
 755
 756    /* Tx/Rx rings managment indexes fields. For driver use */
 757
 758    /* Next available Rx resource */
 759    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
 760    /* Returning Rx resource */
 761    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
 762
 763    /* Next available Tx resource */
 764    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
 765    /* Returning Tx resource */
 766    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
 767    /* An extra Tx index to support transmit of multiple buffers per packet */
 768    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
 769
 770    /* Tx/Rx rings size and base variables fields. For driver use */
 771
 772    volatile ETH_RX_DESC        *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
 773    unsigned int                 rx_desc_area_size[MAX_RX_QUEUE_NUM];
 774    char                        *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
 775
 776    volatile ETH_TX_DESC        *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
 777    unsigned int                 tx_desc_area_size[MAX_TX_QUEUE_NUM];
 778    char                        *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
 779
 780} ETH_PORT_INFO;
 781
 782
 783/* ethernet.h API list */
 784
 785/* Port operation control routines */
 786static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
 787static void eth_port_reset(ETH_PORT     eth_port_num);
 788static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
 789
 790
 791/* Port MAC address routines */
 792static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
 793                                  unsigned char *p_addr,
 794                                  ETH_QUEUE queue);
 795#if 0   /* FIXME */
 796static void eth_port_mc_addr    (ETH_PORT eth_port_num,
 797                                 unsigned char *p_addr,
 798                                 ETH_QUEUE queue,
 799                                 int option);
 800#endif
 801
 802/* PHY and MIB routines */
 803static bool ethernet_phy_reset(ETH_PORT eth_port_num);
 804
 805static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
 806                                   unsigned int phy_reg,
 807                                   unsigned int value);
 808
 809static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
 810                                  unsigned int phy_reg,
 811                                  unsigned int* value);
 812
 813static void eth_clear_mib_counters(ETH_PORT     eth_port_num);
 814
 815/* Port data flow control routines */
 816static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
 817                                             ETH_QUEUE tx_queue,
 818                                             PKT_INFO *p_pkt_info);
 819static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
 820                                              ETH_QUEUE tx_queue,
 821                                              PKT_INFO *p_pkt_info);
 822static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
 823                                             ETH_QUEUE rx_queue,
 824                                             PKT_INFO *p_pkt_info);
 825static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
 826                                              ETH_QUEUE rx_queue,
 827                                              PKT_INFO *p_pkt_info);
 828
 829
 830static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
 831                                    ETH_QUEUE   tx_queue,
 832                                    int                         tx_desc_num,
 833                                    int                         tx_buff_size,
 834                                    unsigned int        tx_desc_base_addr,
 835                                    unsigned int        tx_buff_base_addr);
 836
 837static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
 838                                    ETH_QUEUE   rx_queue,
 839                                    int                         rx_desc_num,
 840                                    int                         rx_buff_size,
 841                                    unsigned int        rx_desc_base_addr,
 842                                    unsigned int        rx_buff_base_addr);
 843
 844#endif /* MV64360_ETH_ */
 845