LXR uboot/board/miromico/hammerhead/hammerhead.c

   1/*
   2 * Copyright (C) 2008 Miromico AG
   3 *
   4 * Mostly copied form atmel ATNGW100 sources
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <netdev.h>
  27
  28#include <asm/io.h>
  29#include <asm/sdram.h>
  30#include <asm/arch/clk.h>
  31#include <asm/arch/hmatrix.h>
  32#include <asm/arch/memory-map.h>
  33#include <asm/arch/portmux.h>
  34
  35DECLARE_GLOBAL_DATA_PTR;
  36
  37static const struct sdram_config sdram_config = {
  38        .data_bits      = SDRAM_DATA_32BIT,
  39        .row_bits       = 13,
  40        .col_bits       = 9,
  41        .bank_bits      = 2,
  42        .cas            = 3,
  43        .twr            = 2,
  44        .trc            = 7,
  45        .trp            = 2,
  46        .trcd           = 2,
  47        .tras           = 5,
  48        .txsr           = 5,
  49        /* 7.81 us */
  50        .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  51};
  52
  53#ifdef CONFIG_CMD_NET
  54int board_eth_init(bd_t *bis)
  55{
  56        return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
  57}
  58#endif
  59
  60int board_early_init_f(void)
  61{
  62        /* Enable SDRAM in the EBI mux */
  63        hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  64
  65        portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
  66        portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  67
  68#if defined(CONFIG_MACB)
  69        portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
  70#endif
  71#if defined(CONFIG_MMC)
  72        portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  73#endif
  74        return 0;
  75}
  76
  77phys_size_t initdram(int board_type)
  78{
  79        unsigned long expected_size;
  80        unsigned long actual_size;
  81        void *sdram_base;
  82
  83        sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
  84
  85        expected_size = sdram_init(sdram_base, &sdram_config);
  86        actual_size = get_ram_size(sdram_base, expected_size);
  87
  88        unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
  89
  90        if (expected_size != actual_size)
  91                printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
  92                       actual_size >> 20, expected_size >> 20);
  93
  94        return actual_size;
  95}
  96
  97int board_early_init_r(void)
  98{
  99        gd->bd->bi_phy_id[0] = 0x01;
 100        return 0;
 101}
 102
 103int board_postclk_init(void)
 104{
 105        /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
 106        gclk_enable_output(3, PORTMUX_DRIVE_LOW);
 107        gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
 108        return 0;
 109}
 110