1/* 2 * (C) Copyright 2001 3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 /**************************************************************************** 25 * Global routines used for MIP405 26 *****************************************************************************/ 27#ifndef __ASSEMBLY__ 28/*int switch_cs(unsigned char boot);*/ 29 30extern int mem_test(unsigned long start, unsigned long ramsize,int mode); 31 32void user_led0(unsigned char on); 33 34 35#endif 36/* timings */ 37/* PLD (CS7) */ 38#define PLD_BME 0 /* Burst disable */ 39#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */ 40#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 41#define PLD_OEN 1 /* Cycles from CS low to OE low */ 42#define PLD_WBN 1 /* Cycles from CS low to WE low */ 43#define PLD_WBF 1 /* Cycles from WE high to CS high */ 44#define PLD_TH 2 /* Number of hold cycles after transfer */ 45#define PLD_RE 0 /* Ready disabled */ 46#define PLD_SOR 1 /* Sample on Ready disabled */ 47#define PLD_BEM 0 /* Byte Write only active on Write cycles */ 48#define PLD_PEN 0 /* Parity disable */ 49#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \ 50 (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5)) 51 52/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 53#define PLD_BS 0 /* 1 MByte */ 54/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 55#define PLD_BU 3 /* R/W */ 56/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 57#define PLD_BW 0 /* 16Bit */ 58#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13)) 59 60 61/* timings */ 62 63#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024)) 64/* Dummy CS to get the board revision */ 65#define BOARD_BME 0 /* Burst disable */ 66#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ 67#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 68#define BOARD_OEN 1 /* Cycles from CS low to OE low */ 69#define BOARD_WBN 1 /* Cycles from CS low to WE low */ 70#define BOARD_WBF 1 /* Cycles from WE high to CS high */ 71#define BOARD_TH 2 /* Number of hold cycles after transfer */ 72#define BOARD_RE 0 /* Ready disabled */ 73#define BOARD_SOR 1 /* Sample on Ready disabled */ 74#define BOARD_BEM 0 /* Byte Write only active on Write cycles */ 75#define BOARD_PEN 0 /* Parity disable */ 76#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \ 77 (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5)) 78 79/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 80#define BOARD_BS 0 /* 1 MByte */ 81/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 82#define BOARD_BU 3 /* R/W */ 83/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 84#define BOARD_BW 0 /* 16Bit */ 85#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13)) 86 87 88/* UART0 CS2 */ 89#define UART0_BME 0 /* Burst disable */ 90#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */ 91#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 92#define UART0_OEN 1 /* Cycles from CS low to OE low */ 93#define UART0_WBN 1 /* Cycles from CS low to WE low */ 94#define UART0_WBF 1 /* Cycles from WE high to CS high */ 95#define UART0_TH 2 /* Number of hold cycles after transfer */ 96#define UART0_RE 0 /* Ready disabled */ 97#define UART0_SOR 1 /* Sample on Ready disabled */ 98#define UART0_BEM 0 /* Byte Write only active on Write cycles */ 99#define UART0_PEN 0 /* Parity disable */ 100#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \ 101 (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5)) 102 103/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 104#define UART0_BS 0 /* 1 MByte */ 105/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 106#define UART0_BU 3 /* R/W */ 107/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 108#define UART0_BW 0 /* 8Bit */ 109#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) 110 111/* UART1 CS3 */ 112#define UART1_AP UART0_AP /* same timing as UART0 */ 113#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13)) 114 115 116/* Flash CS0 or CS 1 */ 117/* 0x7F8FFE80 slowest timing at all... */ 118#define FLASH_BME_B 1 /* Burst enable */ 119#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ 120#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ 121#define FLASH_BME 0 /* Burst disable */ 122#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ 123#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 124#define FLASH_OEN 1 /* Cycles from CS low to OE low */ 125#define FLASH_WBN 1 /* Cycles from CS low to WE low */ 126#define FLASH_WBF 1 /* Cycles from WE high to CS high */ 127#define FLASH_TH 2 /* Number of hold cycles after transfer */ 128#define FLASH_RE 0 /* Ready disabled */ 129#define FLASH_SOR 1 /* Sample on Ready disabled */ 130#define FLASH_BEM 0 /* Byte Write only active on Write cycles */ 131#define FLASH_PEN 0 /* Parity disable */ 132/* Access Parameter Register for non Boot */ 133#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ 134 (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) 135/* Access Parameter Register for Boot */ 136#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ 137 (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) 138 139/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 140#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */ 141/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 142#define FLASH_BU 3 /* R/W */ 143/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 144#define FLASH_BW 1 /* 16Bit */ 145/* CR register for Boot */ 146#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) 147/* CR register for non Boot */ 148#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13)) 149 150/* MPS CS1 or CS0 */ 151/* Boot CS: */ 152#define MPS_BME_B 1 /* Burst enable */ 153#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ 154#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ 155#define MPS_BME 0 /* Burst disable */ 156#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ 157#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ 158#define MPS_OEN 1 /* Cycles from CS low to OE low */ 159#define MPS_WBN 1 /* Cycles from CS low to WE low */ 160#define MPS_WBF 1 /* Cycles from WE high to CS high */ 161#define MPS_TH 2 /* Number of hold cycles after transfer */ 162#define MPS_RE 0 /* Ready disabled */ 163#define MPS_SOR 1 /* Sample on Ready disabled */ 164#define MPS_BEM 0 /* Byte Write only active on Write cycles */ 165#define MPS_PEN 0 /* Parity disable */ 166/* Access Parameter Register for non Boot */ 167#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ 168 (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) 169/* Access Parameter Register for Boot */ 170#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ 171 (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) 172 173/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 174#define MPS_BS 2 /* 4 MByte */ 175#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */ 176/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */ 177#define MPS_BU 3 /* R/W */ 178/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */ 179#define MPS_BW 0 /* 8Bit */ 180/* CR register for Boot */ 181#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13)) 182/* CR register for non Boot */ 183#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13)) 184