LXR uboot/cpu/arm925t/start.S

   1/*
   2 *  armboot - Startup Code for ARM925 CPU-core
   3 *
   4 *  Copyright (c) 2003  Texas Instruments
   5 *
   6 *  ----- Adapted for OMAP1510 from ARM920 code ------
   7 *
   8 *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
   9 *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
  10 *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
  11 *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
  12 *  Copyright (c) 2003  Kshitij  <kshitij@ti.com>
  13 *
  14 * See file CREDITS for list of people who contributed to this
  15 * project.
  16 *
  17 * This program is free software; you can redistribute it and/or
  18 * modify it under the terms of the GNU General Public License as
  19 * published by the Free Software Foundation; either version 2 of
  20 * the License, or (at your option) any later version.
  21 *
  22 * This program is distributed in the hope that it will be useful,
  23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 * GNU General Public License for more details.
  26 *
  27 * You should have received a copy of the GNU General Public License
  28 * along with this program; if not, write to the Free Software
  29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 * MA 02111-1307 USA
  31 */
  32
  33
  34#include <config.h>
  35#include <version.h>
  36
  37#if defined(CONFIG_OMAP1510)
  38#include <./configs/omap1510.h>
  39#endif
  40
  41/*
  42 *************************************************************************
  43 *
  44 * Jump vector table as in table 3.1 in [1]
  45 *
  46 *************************************************************************
  47 */
  48
  49
  50.globl _start
  51_start: b       reset
  52        ldr     pc, _undefined_instruction
  53        ldr     pc, _software_interrupt
  54        ldr     pc, _prefetch_abort
  55        ldr     pc, _data_abort
  56        ldr     pc, _not_used
  57        ldr     pc, _irq
  58        ldr     pc, _fiq
  59
  60_undefined_instruction: .word undefined_instruction
  61_software_interrupt:    .word software_interrupt
  62_prefetch_abort:        .word prefetch_abort
  63_data_abort:            .word data_abort
  64_not_used:              .word not_used
  65_irq:                   .word irq
  66_fiq:                   .word fiq
  67
  68        .balignl 16,0xdeadbeef
  69
  70
  71/*
  72 *************************************************************************
  73 *
  74 * Startup Code (reset vector)
  75 *
  76 * do important init only if we don't start from memory!
  77 * setup Memory and board specific bits prior to relocation.
  78 * relocate armboot to ram
  79 * setup stack
  80 *
  81 *************************************************************************
  82 */
  83
  84_TEXT_BASE:
  85        .word   TEXT_BASE
  86
  87.globl _armboot_start
  88_armboot_start:
  89        .word _start
  90
  91/*
  92 * These are defined in the board-specific linker script.
  93 */
  94.globl _bss_start
  95_bss_start:
  96        .word __bss_start
  97
  98.globl _bss_end
  99_bss_end:
 100        .word _end
 101
 102#ifdef CONFIG_USE_IRQ
 103/* IRQ stack memory (calculated at run-time) */
 104.globl IRQ_STACK_START
 105IRQ_STACK_START:
 106        .word   0x0badc0de
 107
 108/* IRQ stack memory (calculated at run-time) */
 109.globl FIQ_STACK_START
 110FIQ_STACK_START:
 111        .word 0x0badc0de
 112#endif
 113
 114
 115/*
 116 * the actual reset code
 117 */
 118
 119reset:
 120        /*
 121         * set the cpu to SVC32 mode
 122         */
 123        mrs     r0,cpsr
 124        bic     r0,r0,#0x1f
 125        orr     r0,r0,#0xd3
 126        msr     cpsr,r0
 127
 128        /*
 129         * Set up 925T mode
 130         */
 131        mov r1, #0x81               /* Set ARM925T configuration. */
 132        mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
 133
 134        /*
 135         * turn off the watchdog, unlock/diable sequence
 136         */
 137        mov  r1, #0xF5
 138        ldr  r0, =WDTIM_MODE
 139        strh r1, [r0]
 140        mov  r1, #0xA0
 141        strh r1, [r0]
 142
 143        /*
 144         * mask all IRQs by setting all bits in the INTMR - default
 145         */
 146        mov r1, #0xffffffff
 147        ldr r0, =REG_IHL1_MIR
 148        str r1, [r0]
 149        ldr r0, =REG_IHL2_MIR
 150        str r1, [r0]
 151
 152        /*
 153         * wait for dpll to lock
 154         */
 155        ldr  r0, =CK_DPLL1
 156        mov  r1, #0x10
 157        strh r1, [r0]
 158poll1:
 159        ldrh r1, [r0]
 160        ands r1, r1, #0x01
 161        beq poll1
 162
 163        /*
 164         * we do sys-critical inits only at reboot,
 165         * not when booting from ram!
 166         */
 167#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 168        bl  cpu_init_crit
 169#endif
 170
 171#ifndef CONFIG_SKIP_RELOCATE_UBOOT
 172relocate:                               /* relocate U-Boot to RAM           */
 173        adr     r0, _start              /* r0 <- current position of code   */
 174        ldr     r1, _TEXT_BASE          /* test if we run from flash or RAM */
 175        cmp     r0, r1                  /* don't reloc during debug         */
 176        beq     stack_setup
 177
 178        ldr     r2, _armboot_start
 179        ldr     r3, _bss_start
 180        sub     r2, r3, r2              /* r2 <- size of armboot            */
 181        add     r2, r0, r2              /* r2 <- source end address         */
 182
 183copy_loop:
 184        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
 185        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
 186        cmp     r0, r2                  /* until source end addreee [r2]    */
 187        ble     copy_loop
 188#endif  /* CONFIG_SKIP_RELOCATE_UBOOT */
 189
 190        /* Set up the stack                                                 */
 191stack_setup:
 192        ldr     r0, _TEXT_BASE          /* upper 128 KiB: relocated uboot   */
 193        sub     r0, r0, #CONFIG_SYS_MALLOC_LEN  /* malloc area                      */
 194        sub     r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
 195#ifdef CONFIG_USE_IRQ
 196        sub     r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 197#endif
 198        sub     sp, r0, #12             /* leave 3 words for abort-stack    */
 199
 200clear_bss:
 201        ldr     r0, _bss_start          /* find start of bss segment        */
 202        ldr     r1, _bss_end            /* stop here                        */
 203        mov     r2, #0x00000000         /* clear                            */
 204
 205clbss_l:str     r2, [r0]                /* clear loop...                    */
 206        add     r0, r0, #4
 207        cmp     r0, r1
 208        ble     clbss_l
 209
 210        ldr     pc, _start_armboot
 211
 212_start_armboot: .word start_armboot
 213
 214
 215/*
 216 *************************************************************************
 217 *
 218 * CPU_init_critical registers
 219 *
 220 * setup important registers
 221 * setup memory timing
 222 *
 223 *************************************************************************
 224 */
 225
 226
 227cpu_init_crit:
 228        /*
 229         * flush v4 I/D caches
 230         */
 231        mov     r0, #0
 232        mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
 233        mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
 234
 235        /*
 236         * disable MMU stuff and caches
 237         */
 238        mrc     p15, 0, r0, c1, c0, 0
 239        bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
 240        bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
 241        orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 242        orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
 243        mcr     p15, 0, r0, c1, c0, 0
 244
 245        /*
 246         * Go setup Memory and board specific bits prior to relocation.
 247         */
 248        mov     ip, lr          /* perserve link reg across call */
 249        bl      lowlevel_init   /* go setup pll,mux,memory */
 250        mov     lr, ip          /* restore link */
 251        mov     pc, lr          /* back to my caller */
 252/*
 253 *************************************************************************
 254 *
 255 * Interrupt handling
 256 *
 257 *************************************************************************
 258 */
 259
 260@
 261@ IRQ stack frame.
 262@
 263#define S_FRAME_SIZE    72
 264
 265#define S_OLD_R0        68
 266#define S_PSR           64
 267#define S_PC            60
 268#define S_LR            56
 269#define S_SP            52
 270
 271#define S_IP            48
 272#define S_FP            44
 273#define S_R10           40
 274#define S_R9            36
 275#define S_R8            32
 276#define S_R7            28
 277#define S_R6            24
 278#define S_R5            20
 279#define S_R4            16
 280#define S_R3            12
 281#define S_R2            8
 282#define S_R1            4
 283#define S_R0            0
 284
 285#define MODE_SVC 0x13
 286#define I_BIT    0x80
 287
 288/*
 289 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 290 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 291 */
 292
 293        .macro  bad_save_user_regs
 294        sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
 295        stmia   sp, {r0 - r12}                  @ Save user registers (now in svc mode) r0-r12
 296
 297        ldr     r2, _armboot_start
 298        sub     r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 299        sub     r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
 300        ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
 301        add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
 302
 303        add     r5, sp, #S_SP
 304        mov     r1, lr
 305        stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
 306        mov     r0, sp                          @ save current stack into r0 (param register)
 307        .endm
 308
 309        .macro  irq_save_user_regs
 310        sub     sp, sp, #S_FRAME_SIZE
 311        stmia   sp, {r0 - r12}                  @ Calling r0-r12
 312        add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
 313        stmdb   r8, {sp, lr}^                   @ Calling SP, LR
 314        str     lr, [r8, #0]                    @ Save calling PC
 315        mrs     r6, spsr
 316        str     r6, [r8, #4]                    @ Save CPSR
 317        str     r0, [r8, #8]                    @ Save OLD_R0
 318        mov     r0, sp
 319        .endm
 320
 321        .macro  irq_restore_user_regs
 322        ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
 323        mov     r0, r0
 324        ldr     lr, [sp, #S_PC]                 @ Get PC
 325        add     sp, sp, #S_FRAME_SIZE
 326        subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
 327        .endm
 328
 329        .macro get_bad_stack
 330        ldr     r13, _armboot_start             @ setup our mode stack
 331        sub     r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
 332        sub     r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
 333
 334        str     lr, [r13]                       @ save caller lr in position 0 of saved stack
 335        mrs     lr, spsr                        @ get the spsr
 336        str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
 337
 338        mov     r13, #MODE_SVC                  @ prepare SVC-Mode
 339        @ msr   spsr_c, r13
 340        msr     spsr, r13                       @ switch modes, make sure moves will execute
 341        mov     lr, pc                          @ capture return pc
 342        movs    pc, lr                          @ jump to next instruction & switch modes.
 343        .endm
 344
 345        .macro get_irq_stack                    @ setup IRQ stack
 346        ldr     sp, IRQ_STACK_START
 347        .endm
 348
 349        .macro get_fiq_stack                    @ setup FIQ stack
 350        ldr     sp, FIQ_STACK_START
 351        .endm
 352
 353/*
 354 * exception handlers
 355 */
 356        .align  5
 357undefined_instruction:
 358        get_bad_stack
 359        bad_save_user_regs
 360        bl      do_undefined_instruction
 361
 362        .align  5
 363software_interrupt:
 364        get_bad_stack
 365        bad_save_user_regs
 366        bl      do_software_interrupt
 367
 368        .align  5
 369prefetch_abort:
 370        get_bad_stack
 371        bad_save_user_regs
 372        bl      do_prefetch_abort
 373
 374        .align  5
 375data_abort:
 376        get_bad_stack
 377        bad_save_user_regs
 378        bl      do_data_abort
 379
 380        .align  5
 381not_used:
 382        get_bad_stack
 383        bad_save_user_regs
 384        bl      do_not_used
 385
 386#ifdef CONFIG_USE_IRQ
 387
 388        .align  5
 389irq:
 390        get_irq_stack
 391        irq_save_user_regs
 392        bl      do_irq
 393        irq_restore_user_regs
 394
 395        .align  5
 396fiq:
 397        get_fiq_stack
 398        /* someone ought to write a more effiction fiq_save_user_regs */
 399        irq_save_user_regs
 400        bl      do_fiq
 401        irq_restore_user_regs
 402
 403#else
 404
 405        .align  5
 406irq:
 407        get_bad_stack
 408        bad_save_user_regs
 409        bl      do_irq
 410
 411        .align  5
 412fiq:
 413        get_bad_stack
 414        bad_save_user_regs
 415        bl      do_fiq
 416
 417#endif
 418
 419        .align  5
 420.globl reset_cpu
 421reset_cpu:
 422        ldr     r1, rstctl1     /* get clkm1 reset ctl */
 423        mov     r3, #0x3        /* dsp_en + arm_rst = global reset */
 424        strh    r3, [r1]        /* force reset */
 425        mov     r0, r0
 426_loop_forever:
 427        b       _loop_forever
 428rstctl1:
 429        .word   0xfffece10
 430