LXR uboot/cpu/mpc824x/speed.c

   1/*
   2 * (C) Copyright 2001
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2002
   6 * Gregory E. Allen, gallen@arlut.utexas.edu
   7 * Applied Research Laboratories, The University of Texas at Austin
   8 *
   9 * See file CREDITS for list of people who contributed to this
  10 * project.
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 * MA 02111-1307 USA
  26 */
  27
  28#include <common.h>
  29#include <mpc824x.h>
  30#include <asm/processor.h>
  31
  32DECLARE_GLOBAL_DATA_PTR;
  33
  34/* ------------------------------------------------------------------------- */
  35/* NOTE: This describes the proper use of this file.
  36 *
  37 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on
  38 * PCI_SYNC_IN .
  39 *
  40 * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240
  41 * boards. It should be defined as the PCI to Memory Multiplier as
  42 * documented in the MPC8240 Hardware Specs.
  43 *
  44 * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER
  45 * because they can determine it from the PCR.
  46 *
  47 * Gary Milliorn <gary.milliorn@motorola.com> (who should know since
  48 * he designed the Sandpoint) told us that the PCR is not in all revs
  49 * of the MPC8240 CPU, so it's not guaranteeable and we cannot do
  50 * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether.
  51 */
  52/* ------------------------------------------------------------------------- */
  53
  54/* This gives the PCI to Memory multiplier times 10 */
  55/* The index is the value of PLL_CFG[0:4] */
  56/* This is documented in the MPC8240/5 Hardware Specs */
  57
  58short pll_pci_to_mem_multiplier[] = {
  59#if defined(CONFIG_MPC8240)
  60        30, 30, 10, 10, 20, 10,  0, 10,
  61        10,  0, 20,  0, 20,  0, 20,  0,
  62        30,  0, 15,  0, 20,  0, 20,  0,
  63        25,  0, 10,  0, 15, 15,  0,  0,
  64#elif defined(CONFIG_MPC8245)
  65        30, 30, 10, 10, 20, 10, 10, 10,
  66        10, 20, 20, 15, 20, 15, 20, 30,
  67        30, 40, 15, 40, 20, 25, 20, 40,
  68        25, 20, 10, 20, 15, 15, 15,  0,
  69#else
  70#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  71#endif
  72};
  73
  74#define CU824_PLL_STATE_REG     0xFE80002F
  75#define PCR                     0x800000E2
  76
  77/* ------------------------------------------------------------------------- */
  78
  79/* compute the memory bus clock frequency */
  80ulong get_bus_freq (ulong dummy)
  81{
  82        unsigned char pll_cfg;
  83#if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824)
  84        return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER);
  85#elif defined(CONFIG_CU824)
  86        pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG);
  87        pll_cfg &= 0x1f;
  88#else
  89        CONFIG_READ_BYTE(PCR, pll_cfg);
  90        pll_cfg = (pll_cfg >> 3) & 0x1f;
  91#endif
  92        return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10;
  93}
  94
  95
  96/* ------------------------------------------------------------------------- */
  97
  98/* This gives the Memory to CPU Core multiplier times 10 */
  99/* The index is the value of PLLRATIO in HID1 */
 100/* This is documented in the MPC8240 Hardware Specs */
 101/* This is not documented for MPC8245 ? FIXME */
 102short pllratio_to_factor[] = {
 103     0,  0,  0, 10, 20, 20, 25, 45,
 104    30,  0,  0,  0,  0,  0,  0,  0,
 105     0,  0,  0, 10,  0,  0,  0, 45,
 106    30,  0, 40,  0,  0,  0, 35,  0,
 107};
 108
 109/* compute the CPU and memory bus clock frequencies */
 110int get_clocks (void)
 111{
 112        uint hid1 = mfspr(HID1);
 113        hid1 = (hid1 >> (32-5)) & 0x1f;
 114        gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5)
 115                          / 10;
 116        gd->bus_clk = get_bus_freq(0);
 117        return (0);
 118}
 119