LXR uboot/drivers/block/sata

   1/*
   2 * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
   3 * Author: Tor Krill <tor@excito.com>
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 *
  20 * This is a driver for Silicon Image sil3114 sata chip modelled on
  21 * the ata_piix driver
  22 */
  23
  24#include <common.h>
  25#include <pci.h>
  26#include <command.h>
  27#include <config.h>
  28#include <asm/byteorder.h>
  29#include <asm/io.h>
  30#include <ide.h>
  31#include <libata.h>
  32#include "sata_sil3114.h"
  33
  34/* Convert sectorsize to wordsize */
  35#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
  36
  37/* Forwards */
  38u8 sil3114_spin_up (int num);
  39u8 sil3114_spin_down (int num);
  40static int sata_bus_softreset (int num);
  41static void sata_identify (int num, int dev);
  42static u8 check_power_mode (int num);
  43static void sata_port (struct sata_ioports *ioport);
  44static void set_Feature_cmd (int num, int dev);
  45static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
  46                          unsigned int max, u8 usealtstatus);
  47static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
  48static void msleep (int count);
  49
  50static u32 iobase[6] = { 0, 0, 0, 0, 0, 0};     /* PCI BAR registers for device */
  51extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
  52
  53static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
  54
  55static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  56{
  57        while (words--) {
  58                __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
  59        }
  60}
  61
  62static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  63{
  64        while (words--) {
  65                *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
  66        }
  67        return 0;
  68}
  69
  70static int sata_bus_softreset (int num)
  71{
  72        u8 status = 0;
  73
  74        port[num].dev_mask = 1;
  75
  76        port[num].ctl_reg = 0x08;       /*Default value of control reg */
  77        writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  78        udelay (10);
  79        writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
  80        udelay (10);
  81        writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  82
  83        /* spec mandates ">= 2ms" before checking status.
  84         * We wait 150ms, because that was the magic delay used for
  85         * ATAPI devices in Hale Landis's ATADRVR, for the period of time
  86         * between when the ATA command register is written, and then
  87         * status is checked.  Because waiting for "a while" before
  88         * checking status is fine, post SRST, we perform this magic
  89         * delay here as well.
  90         */
  91        msleep (150);
  92        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
  93        while ((status & ATA_BUSY)) {
  94                msleep (100);
  95                status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
  96        }
  97
  98        if (status & ATA_BUSY) {
  99                printf ("ata%u is slow to respond,plz be patient\n", num);
 100        }
 101
 102        while ((status & ATA_BUSY)) {
 103                msleep (100);
 104                status = sata_chk_status (&port[num].ioaddr, 0);
 105        }
 106
 107        if (status & ATA_BUSY) {
 108                printf ("ata%u failed to respond : ", num);
 109                printf ("bus reset failed\n");
 110                port[num].dev_mask = 0;
 111                return 1;
 112        }
 113        return 0;
 114}
 115
 116static void sata_identify (int num, int dev)
 117{
 118        u8 cmd = 0, status = 0, devno = num;
 119        u16 iobuf[ATA_SECTOR_WORDS];
 120        u64 n_sectors = 0;
 121
 122        memset (iobuf, 0, sizeof (iobuf));
 123
 124        if (!(port[num].dev_mask & 0x01)) {
 125                printf ("dev%d is not present on port#%d\n", dev, num);
 126                return;
 127        }
 128
 129        debug ("port=%d dev=%d\n", num, dev);
 130
 131        status = 0;
 132        cmd = ATA_CMD_ID_ATA;   /*Device Identify Command */
 133        writeb (cmd, port[num].ioaddr.command_addr);
 134        readb (port[num].ioaddr.altstatus_addr);
 135        udelay (10);
 136
 137        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
 138        if (status & ATA_ERR) {
 139                printf ("\ndevice not responding\n");
 140                port[num].dev_mask &= ~0x01;
 141                return;
 142        }
 143
 144        input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
 145
 146        ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
 147
 148        debug ("Specific config: %x\n", iobuf[2]);
 149
 150        /* we require LBA and DMA support (bits 8 & 9 of word 49) */
 151        if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
 152                debug ("ata%u: no dma/lba\n", num);
 153        }
 154#ifdef DEBUG
 155        ata_dump_id (iobuf);
 156#endif
 157        n_sectors = ata_id_n_sectors (iobuf);
 158
 159        if (n_sectors == 0) {
 160                port[num].dev_mask &= ~0x01;
 161                return;
 162        }
 163        ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
 164                         ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
 165        ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
 166                         ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
 167        ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
 168                         ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
 169
 170        /* TODO - atm we asume harddisk ie not removable */
 171        sata_dev_desc[devno].removable = 0;
 172
 173        sata_dev_desc[devno].lba = (u32) n_sectors;
 174        debug ("lba=0x%x\n", sata_dev_desc[devno].lba);
 175
 176#ifdef CONFIG_LBA48
 177        if (iobuf[83] & (1 << 10)) {
 178                sata_dev_desc[devno].lba48 = 1;
 179        } else {
 180                sata_dev_desc[devno].lba48 = 0;
 181        }
 182#endif
 183
 184        /* assuming HD */
 185        sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
 186        sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
 187        sata_dev_desc[devno].lun = 0;   /* just to fill something in... */
 188}
 189
 190static void set_Feature_cmd (int num, int dev)
 191{
 192        u8 status = 0;
 193
 194        if (!(port[num].dev_mask & 0x01)) {
 195                debug ("dev%d is not present on port#%d\n", dev, num);
 196                return;
 197        }
 198
 199        writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
 200        writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
 201        writeb (0, port[num].ioaddr.lbal_addr);
 202        writeb (0, port[num].ioaddr.lbam_addr);
 203        writeb (0, port[num].ioaddr.lbah_addr);
 204
 205        writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
 206        writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
 207
 208        udelay (50);
 209        msleep (150);
 210
 211        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
 212        if ((status & (ATA_BUSY | ATA_ERR))) {
 213                printf ("Error  : status 0x%02x\n", status);
 214                port[num].dev_mask &= ~0x01;
 215        }
 216}
 217
 218u8 sil3114_spin_down (int num)
 219{
 220        u8 status = 0;
 221
 222        debug ("Spin down disk\n");
 223
 224        if (!(port[num].dev_mask & 0x01)) {
 225                debug ("Device ata%d is not present\n", num);
 226                return 1;
 227        }
 228
 229        if ((status = check_power_mode (num)) == 0x00) {
 230                debug ("Already in standby\n");
 231                return 0;
 232        }
 233
 234        if (status == 0x01) {
 235                printf ("Failed to check power mode on ata%d\n", num);
 236                return 1;
 237        }
 238
 239        if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
 240                printf ("Device ata%d not ready\n", num);
 241                return 1;
 242        }
 243
 244        writeb (0x00, port[num].ioaddr.feature_addr);
 245
 246        writeb (0x00, port[num].ioaddr.nsect_addr);
 247        writeb (0x00, port[num].ioaddr.lbal_addr);
 248        writeb (0x00, port[num].ioaddr.lbam_addr);
 249        writeb (0x00, port[num].ioaddr.lbah_addr);
 250
 251        writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
 252        writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
 253
 254        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
 255        if ((status & (ATA_BUSY | ATA_ERR))) {
 256                printf ("Error waiting for disk spin down: status 0x%02x\n",
 257                        status);
 258                port[num].dev_mask &= ~0x01;
 259                return 1;
 260        }
 261        return 0;
 262}
 263
 264u8 sil3114_spin_up (int num)
 265{
 266        u8 status = 0;
 267
 268        debug ("Spin up disk\n");
 269
 270        if (!(port[num].dev_mask & 0x01)) {
 271                debug ("Device ata%d is not present\n", num);
 272                return 1;
 273        }
 274
 275        if ((status = check_power_mode (num)) != 0x00) {
 276                if (status == 0x01) {
 277                        printf ("Failed to check power mode on ata%d\n", num);
 278                        return 1;
 279                } else {
 280                        /* should be up and running already */
 281                        return 0;
 282                }
 283        }
 284
 285        if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
 286                printf ("Device ata%d not ready\n", num);
 287                return 1;
 288        }
 289
 290        debug ("Stautus of device check: %d\n", status);
 291
 292        writeb (0x00, port[num].ioaddr.feature_addr);
 293
 294        writeb (0x00, port[num].ioaddr.nsect_addr);
 295        writeb (0x00, port[num].ioaddr.lbal_addr);
 296        writeb (0x00, port[num].ioaddr.lbam_addr);
 297        writeb (0x00, port[num].ioaddr.lbah_addr);
 298
 299        writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
 300        writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
 301
 302        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
 303        if ((status & (ATA_BUSY | ATA_ERR))) {
 304                printf ("Error waiting for disk spin up: status 0x%02x\n",
 305                        status);
 306                port[num].dev_mask &= ~0x01;
 307                return 1;
 308        }
 309
 310        /* Wait for disk to enter Active state */
 311        do {
 312                msleep (10);
 313                status = check_power_mode (num);
 314        } while ((status == 0x00) || (status == 0x80));
 315
 316        if (status == 0x01) {
 317                printf ("Falied waiting for disk to spin up\n");
 318                return 1;
 319        }
 320
 321        return 0;
 322}
 323
 324/* Return value is not the usual here
 325 * 0x00 - Device stand by
 326 * 0x01 - Operation failed
 327 * 0x80 - Device idle
 328 * 0xff - Device active
 329*/
 330static u8 check_power_mode (int num)
 331{
 332        u8 status = 0;
 333        u8 res = 0;
 334        if (!(port[num].dev_mask & 0x01)) {
 335                debug ("Device ata%d is not present\n", num);
 336                return 1;
 337        }
 338
 339        if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
 340                printf ("Device ata%d not ready\n", num);
 341                return 1;
 342        }
 343
 344        writeb (0, port[num].ioaddr.feature_addr);
 345        writeb (0, port[num].ioaddr.nsect_addr);
 346        writeb (0, port[num].ioaddr.lbal_addr);
 347        writeb (0, port[num].ioaddr.lbam_addr);
 348        writeb (0, port[num].ioaddr.lbah_addr);
 349
 350        writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
 351        writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
 352
 353        status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
 354        if ((status & (ATA_BUSY | ATA_ERR))) {
 355                printf
 356                    ("Error waiting for check power mode complete  : status 0x%02x\n",
 357                     status);
 358                port[num].dev_mask &= ~0x01;
 359                return 1;
 360        }
 361        res = readb (port[num].ioaddr.nsect_addr);
 362        debug ("Check powermode: %d\n", res);
 363        return res;
 364
 365}
 366
 367static void sata_port (struct sata_ioports *ioport)
 368{
 369        ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
 370        ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
 371        ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
 372        ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
 373        ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
 374        ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
 375        ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
 376        ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
 377        ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
 378        ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
 379}
 380
 381static u8 wait_for_irq (int num, unsigned int max)
 382{
 383
 384        u32 port = iobase[5];
 385        switch (num) {
 386        case 0:
 387                port += VND_TF_CNST_CH0;
 388                break;
 389        case 1:
 390                port += VND_TF_CNST_CH1;
 391                break;
 392        case 2:
 393                port += VND_TF_CNST_CH2;
 394                break;
 395        case 3:
 396                port += VND_TF_CNST_CH3;
 397                break;
 398        default:
 399                return 1;
 400        }
 401
 402        do {
 403                if (readl (port) & VND_TF_CNST_INTST) {
 404                        break;
 405                }
 406                udelay (1000);
 407                max--;
 408        } while ((max > 0));
 409
 410        return (max == 0);
 411}
 412
 413static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
 414                          unsigned int max, u8 usealtstatus)
 415{
 416        u8 status;
 417
 418        do {
 419                if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
 420                        break;
 421                }
 422                udelay (1000);
 423                max--;
 424        } while ((status & bits) && (max > 0));
 425
 426        return status;
 427}
 428
 429static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
 430{
 431        if (!usealtstatus) {
 432                return readb (ioaddr->status_addr);
 433        } else {
 434                return readb (ioaddr->altstatus_addr);
 435        }
 436}
 437
 438static void msleep (int count)
 439{
 440        int i;
 441
 442        for (i = 0; i < count; i++)
 443                udelay (1000);
 444}
 445
 446/* Read up to 255 sectors
 447 *
 448 * Returns sectors read
 449*/
 450static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
 451                       uchar lba48)
 452{
 453
 454        u8 sr = 0;
 455        u8 status;
 456        u64 blknr = (u64) block;
 457
 458        if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
 459                printf ("Device ata%d not ready\n", device);
 460                return 0;
 461        }
 462
 463        /* Set up transfer */
 464#ifdef CONFIG_LBA48
 465        if (lba48) {
 466                /* write high bits */
 467                writeb (0, port[device].ioaddr.nsect_addr);
 468                writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
 469                writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
 470                writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
 471        }
 472#endif
 473        writeb (blkcnt, port[device].ioaddr.nsect_addr);
 474        writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
 475        writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
 476        writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
 477
 478#ifdef CONFIG_LBA48
 479        if (lba48) {
 480                writeb (ATA_LBA, port[device].ioaddr.device_addr);
 481                writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
 482        } else
 483#endif
 484        {
 485                writeb (ATA_LBA | ((blknr >> 24) & 0xF),
 486                        port[device].ioaddr.device_addr);
 487                writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
 488        }
 489
 490        status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
 491
 492        if (status & ATA_BUSY) {
 493                u8 err = 0;
 494
 495                printf ("Device %d not responding status %d\n", device, status);
 496                err = readb (port[device].ioaddr.error_addr);
 497                printf ("Error reg = 0x%x\n", err);
 498
 499                return (sr);
 500        }
 501        while (blkcnt--) {
 502
 503                if (wait_for_irq (device, 500)) {
 504                        printf ("ata%u irq failed\n", device);
 505                        return sr;
 506                }
 507
 508                status = sata_chk_status (&port[device].ioaddr, 0);
 509                if (status & ATA_ERR) {
 510                        printf ("ata%u error %d\n", device,
 511                                readb (port[device].ioaddr.error_addr));
 512                        return sr;
 513                }
 514                /* Read one sector */
 515                input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
 516                buff += ATA_SECTOR_WORDS;
 517                sr++;
 518
 519        }
 520        return sr;
 521}
 522
 523ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
 524{
 525        ulong n = 0, sread;
 526        u16 *buffer = (u16 *) buff;
 527        u8 status = 0;
 528        u64 blknr = (u64) block;
 529        unsigned char lba48 = 0;
 530
 531#ifdef CONFIG_LBA48
 532        if (blknr > 0xfffffff) {
 533                if (!sata_dev_desc[device].lba48) {
 534                        printf ("Drive doesn't support 48-bit addressing\n");
 535                        return 0;
 536                }
 537                /* more than 28 bits used, use 48bit mode */
 538                lba48 = 1;
 539        }
 540#endif
 541
 542        while (blkcnt > 0) {
 543
 544                if (blkcnt > 255) {
 545                        sread = 255;
 546                } else {
 547                        sread = blkcnt;
 548                }
 549
 550                status = do_one_read (device, blknr, sread, buffer, lba48);
 551                if (status != sread) {
 552                        printf ("Read failed\n");
 553                        return n;
 554                }
 555
 556                blkcnt -= sread;
 557                blknr += sread;
 558                n += sread;
 559                buffer += sread * ATA_SECTOR_WORDS;
 560        }
 561        return n;
 562}
 563
 564ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
 565{
 566        ulong n = 0;
 567        u16 *buffer = (u16 *) buff;
 568        unsigned char status = 0, num = 0;
 569        u64 blknr = (u64) block;
 570#ifdef CONFIG_LBA48
 571        unsigned char lba48 = 0;
 572
 573        if (blknr > 0xfffffff) {
 574                if (!sata_dev_desc[device].lba48) {
 575                        printf ("Drive doesn't support 48-bit addressing\n");
 576                        return 0;
 577                }
 578                /* more than 28 bits used, use 48bit mode */
 579                lba48 = 1;
 580        }
 581#endif
 582        /*Port Number */
 583        num = device;
 584
 585        while (blkcnt-- > 0) {
 586                status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
 587                if (status & ATA_BUSY) {
 588                        printf ("ata%u failed to respond\n", port[num].port_no);
 589                        return n;
 590                }
 591#ifdef CONFIG_LBA48
 592                if (lba48) {
 593                        /* write high bits */
 594                        writeb (0, port[num].ioaddr.nsect_addr);
 595                        writeb ((blknr >> 24) & 0xFF,
 596                                port[num].ioaddr.lbal_addr);
 597                        writeb ((blknr >> 32) & 0xFF,
 598                                port[num].ioaddr.lbam_addr);
 599                        writeb ((blknr >> 40) & 0xFF,
 600                                port[num].ioaddr.lbah_addr);
 601                }
 602#endif
 603                writeb (1, port[num].ioaddr.nsect_addr);
 604                writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
 605                writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
 606                writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
 607#ifdef CONFIG_LBA48
 608                if (lba48) {
 609                        writeb (ATA_LBA, port[num].ioaddr.device_addr);
 610                        writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
 611                } else
 612#endif
 613                {
 614                        writeb (ATA_LBA | ((blknr >> 24) & 0xF),
 615                                port[num].ioaddr.device_addr);
 616                        writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
 617                }
 618
 619                msleep (50);
 620                /*may take up to 4 sec */
 621                status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
 622                if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
 623                        printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
 624                                device, (ulong) blknr, status);
 625                        return (n);
 626                }
 627
 628                output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
 629                readb (port[num].ioaddr.altstatus_addr);
 630                udelay (50);
 631
 632                ++n;
 633                ++blknr;
 634                buffer += ATA_SECTOR_WORDS;
 635        }
 636        return n;
 637}
 638
 639/* Driver implementation */
 640static u8 sil_get_device_cache_line (pci_dev_t pdev)
 641{
 642        u8 cache_line = 0;
 643        pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
 644        return cache_line;
 645}
 646
 647int init_sata (int dev)
 648{
 649        static u8 init_done = 0;
 650        static int res = 1;
 651        pci_dev_t devno;
 652        u8 cls = 0;
 653        u16 cmd = 0;
 654        u32 sconf = 0;
 655
 656        if (init_done) {
 657                return res;
 658        }
 659
 660        init_done = 1;
 661
 662        if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
 663                res = 1;
 664                return res;
 665        }
 666
 667        /* Read out all BARs, even though we only use MMIO from BAR5 */
 668        pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
 669        pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
 670        pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
 671        pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
 672        pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
 673        pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
 674
 675        if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
 676            (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
 677            (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
 678                printf ("Error no base addr for SATA controller\n");
 679                res = 1;
 680                return res;
 681        }
 682
 683        /* mask off unused bits */
 684        iobase[0] &= 0xfffffffc;
 685        iobase[1] &= 0xfffffff8;
 686        iobase[2] &= 0xfffffffc;
 687        iobase[3] &= 0xfffffff8;
 688        iobase[4] &= 0xfffffff0;
 689        iobase[5] &= 0xfffffc00;
 690
 691        /* from sata_sil in Linux kernel */
 692        cls = sil_get_device_cache_line (devno);
 693        if (cls) {
 694                cls >>= 3;
 695                cls++;          /* cls = (line_size/8)+1 */
 696                writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
 697                writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
 698                writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
 699                writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
 700        } else {
 701                printf ("Cache line not set. Driver may not function\n");
 702        }
 703
 704        /* Enable operation */
 705        pci_read_config_word (devno, PCI_COMMAND, &cmd);
 706        cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 707        pci_write_config_word (devno, PCI_COMMAND, cmd);
 708
 709        /* Disable interrupt usage */
 710        pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
 711        sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
 712        pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
 713
 714        res = 0;
 715        return res;
 716}
 717
 718/* Check if device is connected to port */
 719int sata_bus_probe (int portno)
 720{
 721        u32 port = iobase[5];
 722        u32 val;
 723        switch (portno) {
 724        case 0:
 725                port += VND_SSTATUS_CH0;
 726                break;
 727        case 1:
 728                port += VND_SSTATUS_CH1;
 729                break;
 730        case 2:
 731                port += VND_SSTATUS_CH2;
 732                break;
 733        case 3:
 734                port += VND_SSTATUS_CH3;
 735                break;
 736        default:
 737                return 0;
 738        }
 739        val = readl (port);
 740        if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
 741                return 1;
 742        } else {
 743                return 0;
 744        }
 745}
 746
 747int sata_phy_reset (int portno)
 748{
 749        u32 port = iobase[5];
 750        u32 val;
 751        switch (portno) {
 752        case 0:
 753                port += VND_SCONTROL_CH0;
 754                break;
 755        case 1:
 756                port += VND_SCONTROL_CH1;
 757                break;
 758        case 2:
 759                port += VND_SCONTROL_CH2;
 760                break;
 761        case 3:
 762                port += VND_SCONTROL_CH3;
 763                break;
 764        default:
 765                return 0;
 766        }
 767        val = readl (port);
 768        writel (val | SATA_SC_DET_RST, port);
 769        msleep (150);
 770        writel (val & ~SATA_SC_DET_RST, port);
 771        return 0;
 772}
 773
 774int scan_sata (int dev)
 775{
 776        /* A bit brain dead, but the code has a legacy */
 777        switch (dev) {
 778        case 0:
 779                port[0].port_no = 0;
 780                port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
 781                port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
 782                    (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
 783                port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
 784                break;
 785        case 1:
 786                port[1].port_no = 0;
 787                port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
 788                port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
 789                    (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
 790                port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
 791                break;
 792        case 2:
 793                port[2].port_no = 0;
 794                port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
 795                port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
 796                    (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
 797                port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
 798                break;
 799        case 3:
 800                port[3].port_no = 0;
 801                port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
 802                port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
 803                    (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
 804                port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
 805                break;
 806        default:
 807                printf ("Tried to scan unknown port: ata%d\n", dev);
 808                return 1;
 809        }
 810
 811        /* Initialize other registers */
 812        sata_port (&port[dev].ioaddr);
 813
 814        /* Check for attached device */
 815        if (!sata_bus_probe (dev)) {
 816                port[dev].port_state = 0;
 817                debug ("SATA#%d port is not present\n", dev);
 818        } else {
 819                debug ("SATA#%d port is present\n", dev);
 820                if (sata_bus_softreset (dev)) {
 821                        /* soft reset failed, try a hard one */
 822                        sata_phy_reset (dev);
 823                        if (sata_bus_softreset (dev)) {
 824                                port[dev].port_state = 0;
 825                        } else {
 826                                port[dev].port_state = 1;
 827                        }
 828                } else {
 829                        port[dev].port_state = 1;
 830                }
 831        }
 832        if (port[dev].port_state == 1) {
 833                /* Probe device and set xfer mode */
 834                sata_identify (dev, 0);
 835                set_Feature_cmd (dev, 0);
 836        }
 837
 838        return 0;
 839}
 840