LXR uboot/drivers/net/phy/mv88e61xx.c

   1/*
   2 * (C) Copyright 2009
   3 * Marvell Semiconductor <www.marvell.com>
   4 * Prafulla Wadaskar <prafulla@marvell.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22 * MA 02110-1301 USA
  23 */
  24
  25#include <common.h>
  26#include <netdev.h>
  27#include "mv88e61xx.h"
  28
  29#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
  30/* Chip Address mode
  31 * The Switch support two modes of operation
  32 * 1. single chip mode and
  33 * 2. Multi-chip mode
  34 * Refer section 9.2 &9.3 in chip datasheet-02 for more details
  35 *
  36 * By default single chip mode is configured
  37 * multichip mode operation can be configured in board header
  38 */
  39static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
  40{
  41        u16 reg = 0;
  42        u32 timeout = MV88E61XX_PHY_TIMEOUT;
  43
  44        /* Poll till SMIBusy bit is clear */
  45        do {
  46                miiphy_read(name, devaddr, 0x0, &reg);
  47                if (timeout-- == 0) {
  48                        printf("SMI busy timeout\n");
  49                        return -1;
  50                }
  51        } while (reg & (1 << 15));
  52        return 0;
  53}
  54
  55static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
  56{
  57        u16 mii_dev_addr;
  58
  59        /* command to read PHY dev address */
  60        if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
  61                printf("Error..could not read PHY dev address\n");
  62                return;
  63        }
  64        mv88e61xx_busychk_multic(name, mii_dev_addr);
  65        /* Write data to Switch indirect data register */
  66        miiphy_write(name, mii_dev_addr, 0x1, data);
  67        /* Write command to Switch indirect command register (write) */
  68        miiphy_write(name, mii_dev_addr, 0x0,
  69                     reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
  70                                                                         15));
  71}
  72
  73static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
  74{
  75        u16 mii_dev_addr;
  76
  77        /* command to read PHY dev address */
  78        if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
  79                printf("Error..could not read PHY dev address\n");
  80                return;
  81        }
  82        mv88e61xx_busychk_multic(name, mii_dev_addr);
  83        /* Write command to Switch indirect command register (read) */
  84        miiphy_write(name, mii_dev_addr, 0x0,
  85                     reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
  86                                                                         15));
  87        mv88e61xx_busychk_multic(name, mii_dev_addr);
  88        /* Read data from Switch indirect data register */
  89        miiphy_read(name, mii_dev_addr, 0x1, data);
  90}
  91#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
  92
  93static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
  94                                       u32 max_prtnum, u32 ports_ofs)
  95{
  96        u32 prt;
  97        u16 reg;
  98        char *name = swconfig->name;
  99        u32 cpu_port = swconfig->cpuport;
 100        u32 port_mask = swconfig->ports_enabled;
 101        enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
 102
 103        /* be sure all ports are disabled */
 104        for (prt = 0; prt < max_prtnum; prt++) {
 105                RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, &reg);
 106                reg &= ~0x3;
 107                WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
 108
 109                if (!(cpu_port & (1 << prt)))
 110                        continue;
 111                /* Set CPU port VID to 0x1 */
 112                RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, &reg);
 113                reg &= ~0xfff;
 114                reg |= 0x1;
 115                WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
 116        }
 117
 118        /* Setting  Port default priority for all ports to zero */
 119        for (prt = 0; prt < max_prtnum; prt++) {
 120                RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, &reg);
 121                reg &= ~0xc000;
 122                WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
 123        }
 124        /* Setting VID and VID map for all ports except CPU port */
 125        for (prt = 0; prt < max_prtnum; prt++) {
 126                /* only for enabled ports */
 127                if ((1 << prt) & port_mask) {
 128                        /* skip CPU port */
 129                        if ((1 << prt) & cpu_port) {
 130                                /*
 131                                 * Set Vlan map table for cpu_port to see
 132                                 * all ports
 133                                 */
 134                                RD_PHY(name, (ports_ofs + prt),
 135                                       MV88E61XX_PRT_VMAP_REG, &reg);
 136                                reg &= ~((1 << max_prtnum) - 1);
 137                                reg |= port_mask & ~(1 << prt);
 138                                WR_PHY(name, (ports_ofs + prt),
 139                                       MV88E61XX_PRT_VMAP_REG, reg);
 140                        } else {
 141
 142                                /*
 143                                 *  set Ports VLAN Mapping.
 144                                 *      port prt <--> cpu_port VLAN #prt+1.
 145                                 */
 146                                RD_PHY(name, ports_ofs + prt,
 147                                       MV88E61XX_PRT_VID_REG, &reg);
 148                                reg &= ~0x0fff;
 149                                reg |= (prt + 1);
 150                                WR_PHY(name, ports_ofs + prt,
 151                                       MV88E61XX_PRT_VID_REG, reg);
 152
 153                                RD_PHY(name, ports_ofs + prt,
 154                                       MV88E61XX_PRT_VMAP_REG, &reg);
 155                                if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
 156                                        /*
 157                                         * all any port can send frames to all other ports
 158                                         * ref: sec 3.2.1.1 of datasheet
 159                                         */
 160                                        reg |= 0x03f;
 161                                        reg &= ~(1 << prt);
 162                                } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
 163                                        /*
 164                                         * all other ports can send frames to CPU port only
 165                                         * ref: sec 3.2.1.2 of datasheet
 166                                         */
 167                                        reg &= ~((1 << max_prtnum) - 1);
 168                                        reg |= cpu_port;
 169                                }
 170                                WR_PHY(name, ports_ofs + prt,
 171                                       MV88E61XX_PRT_VMAP_REG, reg);
 172                        }
 173                }
 174        }
 175
 176        /*
 177         * enable only appropriate ports to forwarding mode
 178         * and disable the others
 179         */
 180        for (prt = 0; prt < max_prtnum; prt++) {
 181                if ((1 << prt) & port_mask) {
 182                        RD_PHY(name, ports_ofs + prt,
 183                               MV88E61XX_PRT_CTRL_REG, &reg);
 184                        reg |= 0x3;
 185                        WR_PHY(name, ports_ofs + prt,
 186                               MV88E61XX_PRT_CTRL_REG, reg);
 187                } else {
 188                        /* Disable port */
 189                        RD_PHY(name, ports_ofs + prt,
 190                               MV88E61XX_PRT_CTRL_REG, &reg);
 191                        reg &= ~0x3;
 192                        WR_PHY(name, ports_ofs + prt,
 193                               MV88E61XX_PRT_CTRL_REG, reg);
 194                }
 195        }
 196}
 197
 198/*
 199 * Make sure SMIBusy bit cleared before another
 200 * SMI operation can take place
 201 */
 202static int mv88e61xx_busychk(char *name)
 203{
 204        u16 reg = 0;
 205        u32 timeout = MV88E61XX_PHY_TIMEOUT;
 206        do {
 207                RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
 208                       MV88E61XX_PHY_CMD, &reg);
 209                if (timeout-- == 0) {
 210                        printf("SMI busy timeout\n");
 211                        return -1;
 212                }
 213        } while (reg & 1 << 15);        /* busy mask */
 214        return 0;
 215}
 216
 217/*
 218 * Power up the specified port and reset PHY
 219 */
 220static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
 221{
 222        char *name = swconfig->name;
 223
 224        /* Write Copper Specific control reg1 (0x14) for-
 225         * Enable Phy power up
 226         * Energy Detect on (sense&Xmit NLP Periodically
 227         * reset other settings default
 228         */
 229        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
 230        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
 231               MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));
 232
 233        if (mv88e61xx_busychk(name))
 234                return -1;
 235
 236        /* Write PHY ctrl reg (0x0) to apply
 237         * Phy reset (set bit 15 low)
 238         * reset other default values
 239         */
 240        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
 241        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
 242               MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));
 243
 244        if (mv88e61xx_busychk(name))
 245                return -1;
 246
 247        return 0;
 248}
 249
 250/*
 251 * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
 252 * is set to "On-1000Mb/s Link, Off Else"
 253 * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
 254 *
 255 * This is optional settings may be needed on some boards
 256 * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
 257 * Link status
 258 */
 259static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
 260{
 261        char *name = swconfig->name;
 262        u16 reg;
 263
 264        if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
 265                return 0;
 266
 267        /* set page address to 3 */
 268        reg = 3;
 269        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
 270        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
 271               MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
 272                                   1 << MV88E61XX_MODE_OFST |
 273                                   1 << MV88E61XX_OP_OFST |
 274                                   prt << MV88E61XX_ADDR_OFST | 22));
 275
 276        if (mv88e61xx_busychk(name))
 277                return -1;
 278
 279        /* set LED Func Ctrl reg */
 280        reg = 1;        /* LED[0] On-Link, Blink-Activity, Off-NoLink */
 281        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
 282        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
 283               MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
 284                                   1 << MV88E61XX_MODE_OFST |
 285                                   1 << MV88E61XX_OP_OFST |
 286                                   prt << MV88E61XX_ADDR_OFST | 16));
 287
 288        if (mv88e61xx_busychk(name))
 289                return -1;
 290
 291        /* set page address to 0 */
 292        reg = 0;
 293        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
 294        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
 295               MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
 296                                   1 << MV88E61XX_MODE_OFST |
 297                                   1 << MV88E61XX_OP_OFST |
 298                                   prt << MV88E61XX_ADDR_OFST | 22));
 299
 300        if (mv88e61xx_busychk(name))
 301                return -1;
 302
 303        return 0;
 304}
 305
 306/*
 307 * Reverse Transmit polarity for Media Dependent Interface
 308 * Pins (MDIP) bits in Copper Specific Control Register 3
 309 * (Page 0, Reg 20 for each phy (except cpu port)
 310 * Reference: Section 1.1 Switch datasheet-3
 311 *
 312 * This is optional settings may be needed on some boards
 313 * for PHY<->magnetics h/w tuning
 314 */
 315static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
 316{
 317        char *name = swconfig->name;
 318        u16 reg;
 319
 320        if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
 321                return 0;
 322
 323        reg = 0x0f;             /*Reverse MDIP/N[3:0] bits */
 324        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
 325        WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
 326               MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
 327                                   1 << MV88E61XX_MODE_OFST |
 328                                   1 << MV88E61XX_OP_OFST |
 329                                   prt << MV88E61XX_ADDR_OFST | 20));
 330
 331        if (mv88e61xx_busychk(name))
 332                return -1;
 333
 334        return 0;
 335}
 336
 337/*
 338 * Marvell 88E61XX Switch initialization
 339 */
 340int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
 341{
 342        u32 prt;
 343        u16 reg;
 344        char *idstr;
 345        char *name = swconfig->name;
 346
 347        if (miiphy_set_current_dev(name)) {
 348                printf("%s failed\n", __FUNCTION__);
 349                return -1;
 350        }
 351
 352        if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
 353                swconfig->cpuport = (1 << 5);
 354                printf("Invalid cpu port config, using default port5\n");
 355        }
 356
 357        RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg);
 358        switch (reg &= 0xfff0) {
 359        case 0x1610:
 360                idstr = "88E6161";
 361                break;
 362        case 0x1650:
 363                idstr = "88E6165";
 364                break;
 365        case 0x1210:
 366                idstr = "88E6123";
 367                /* ports 2,3,4 not available */
 368                swconfig->ports_enabled &= 0x023;
 369                break;
 370        default:
 371                /* Could not detect switch id */
 372                idstr = "88E61??";
 373                break;
 374        }
 375
 376        /* Port based VLANs configuration */
 377        if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
 378            || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
 379                mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
 380                                           MV88E61XX_PRT_OFST);
 381        else {
 382                printf("Unsupported mode %s failed\n", __FUNCTION__);
 383                return -1;
 384        }
 385
 386        if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
 387                /*
 388                 * Enable RGMII delay on Tx and Rx for CPU port
 389                 * Ref: sec 9.5 of chip datasheet-02
 390                 */
 391                WR_PHY(name, MV88E61XX_PRT_OFST + 5,
 392                       MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
 393                WR_PHY(name, MV88E61XX_PRT_OFST + 4,
 394                       MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
 395        }
 396
 397        for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
 398                if (!((1 << prt) & swconfig->cpuport)) {
 399
 400                        if (mv88361xx_led_init(swconfig, prt))
 401                                return -1;
 402                        if (mv88361xx_reverse_mdipn(swconfig, prt))
 403                                return -1;
 404                        if (mv88361xx_powerup(swconfig, prt))
 405                                return -1;
 406                }
 407
 408                /*Program port state */
 409                RD_PHY(name, MV88E61XX_PRT_OFST + prt,
 410                       MV88E61XX_PRT_CTRL_REG, &reg);
 411                WR_PHY(name, MV88E61XX_PRT_OFST + prt,
 412                       MV88E61XX_PRT_CTRL_REG,
 413                       reg | (swconfig->portstate & 0x03));
 414        }
 415
 416        printf("%s Initialized on %s\n", idstr, name);
 417        return 0;
 418}
 419