1/* 2 * include/asm-armnommu/arch-netarm/netarm_gen_module.h 3 * 4 * Copyright (C) 2005 5 * Art Shipkowski, Videon Central, Inc., <art@videon-central.com> 6 * 7 * Copyright (C) 2000, 2001 NETsilicon, Inc. 8 * Copyright (C) 2000, 2001 Red Hat, Inc. 9 * 10 * This software is copyrighted by Red Hat. LICENSEE agrees that 11 * it will not delete this copyright notice, trademarks or protective 12 * notices from any copy made by LICENSEE. 13 * 14 * This software is provided "AS-IS" and any express or implied 15 * warranties or conditions, including but not limited to any 16 * implied warranties of merchantability and fitness for a particular 17 * purpose regarding this software. In no event shall Red Hat 18 * be liable for any indirect, consequential, or incidental damages, 19 * loss of profits or revenue, loss of use or data, or interruption 20 * of business, whether the alleged damages are labeled in contract, 21 * tort, or indemnity. 22 * 23 * This program is free software; you can redistribute it and/or modify 24 * it under the terms of the GNU General Public License as published by 25 * the Free Software Foundation; either version 2 of the License, or 26 * (at your option) any later version. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 31 * 32 * author(s) : Joe deBlaquiere 33 * 34 * Modified to support NS7520 by Art Shipkowski. 35 */ 36 37#ifndef __NETARM_GEN_MODULE_REGISTERS_H 38#define __NETARM_GEN_MODULE_REGISTERS_H 39 40/* GEN unit register offsets */ 41 42#define NETARM_GEN_MODULE_BASE (0xFFB00000) 43 44#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c))) 45 46#define NETARM_GEN_SYSTEM_CONTROL (0x00) 47#define NETARM_GEN_STATUS_CONTROL (0x04) 48#define NETARM_GEN_PLL_CONTROL (0x08) 49#define NETARM_GEN_SOFTWARE_SERVICE (0x0c) 50 51#define NETARM_GEN_TIMER1_CONTROL (0x10) 52#define NETARM_GEN_TIMER1_STATUS (0x14) 53#define NETARM_GEN_TIMER2_CONTROL (0x18) 54#define NETARM_GEN_TIMER2_STATUS (0x1c) 55 56#define NETARM_GEN_PORTA (0x20) 57#ifndef CONFIG_NETARM_NS7520 58#define NETARM_GEN_PORTB (0x24) 59#endif 60#define NETARM_GEN_PORTC (0x28) 61 62#define NETARM_GEN_INTR_ENABLE (0x30) 63#define NETARM_GEN_INTR_ENABLE_SET (0x34) 64#define NETARM_GEN_INTR_ENABLE_CLR (0x38) 65#define NETARM_GEN_INTR_STATUS_EN (0x34) 66#define NETARM_GEN_INTR_STATUS_RAW (0x38) 67 68#define NETARM_GEN_CACHE_CONTROL1 (0x40) 69#define NETARM_GEN_CACHE_CONTROL2 (0x44) 70 71/* select bitfield definitions */ 72 73/* System Control Register ( 0xFFB0_0000 ) */ 74 75#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000) 76#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000) 77 78#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000) 79#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000) 80#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000) 81 82#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000) 83 84#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000) 85#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000) 86#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000) 87#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000) 88#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000) 89#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000) 90#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000) 91#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000) 92 93#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000) 94#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000) 95#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000) 96#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000) 97#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000) 98 99#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000) 100#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000) 101 102#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000) 103#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000) 104 105#define NETARM_GEN_SYS_CFG_DMATST (0x00001000) 106 107#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800) 108 109#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400) 110 111#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200) 112 113#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100) 114 115#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080) 116 117/* PLL Control Register ( 0xFFB0_0008 ) */ 118 119#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000) 120 121#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \ 122 NETARM_GEN_PLL_CTL_PLLCNT_MASK) 123 124/* Defaults for POLTST and ICP Fields in PLL CTL */ 125#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x) 126#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6) 127#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00) 128#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C) 129 130 131/* Software Service Register ( 0xFFB0_000C ) */ 132 133#define NETARM_GEN_SW_SVC_RESETA (0x123) 134#define NETARM_GEN_SW_SVC_RESETB (0x321) 135 136/* PORT C Register ( 0xFFB0_0028 ) */ 137 138#ifndef CONFIG_NETARM_NS7520 139#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00)) 140#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00)) 141#else 142#define NETARM_GEN_PORT_MODE(x) ((x)<<24) 143#define NETARM_GEN_PORT_DIR(x) ((x)<<16) 144#define NETARM_GEN_PORT_CSF(x) ((x)<<8) 145#endif 146 147/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */ 148 149#define NETARM_GEN_TCTL_ENABLE (0x80000000) 150#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000) 151 152#define NETARM_GEN_TCTL_USE_IRQ (0x00000000) 153#define NETARM_GEN_TCTL_USE_FIQ (0x20000000) 154 155#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000) 156#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF) 157 158#define NETARM_GEN_TSTAT_INTPEN (0x40000000) 159#if ~defined(CONFIG_NETARM_NS7520) 160#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF) 161#else 162#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF) 163#endif 164 165/* prescale to msecs conversion */ 166 167#if !defined(CONFIG_NETARM_PLL_BYPASS) 168#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \ 169 NETARM_GEN_TSTAT_CTC_MASK ) + \ 170 1 ) ) / (NETARM_XTAL_FREQ/1000) ) 171 172#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \ 173 NETARM_GEN_TSTAT_CTC_MASK ) | \ 174 NETARM_GEN_TCTL_USE_PRESCALE ) 175 176#else 177#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \ 178 NETARM_GEN_TSTAT_CTC_MASK ) + \ 179 1 ) ) / (NETARM_XTAL_FREQ/1000) ) 180 181#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \ 182 NETARM_GEN_TSTAT_CTC_MASK ) | \ 183 NETARM_GEN_TCTL_USE_PRESCALE ) 184#endif 185 186#endif 187