1/* 2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23#ifndef AT91_MATRIX_H 24#define AT91_MATRIX_H 25 26#ifdef __ASSEMBLY__ 27 28#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 29#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C) 30#elif defined(CONFIG_AT91SAM9261) 31#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30) 32#elif defined(CONFIG_AT91SAM9263) 33#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120) 34#elif defined(CONFIG_AT91SAM9G45) 35#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128) 36#else 37#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU 38#endif 39 40#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE 41 42#else 43#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 44#define AT91_MATRIX_MASTERS 6 45#define AT91_MATRIX_SLAVES 5 46#elif defined(CONFIG_AT91SAM9261) 47#define AT91_MATRIX_MASTERS 1 48#define AT91_MATRIX_SLAVES 5 49#elif defined(CONFIG_AT91SAM9263) 50#define AT91_MATRIX_MASTERS 9 51#define AT91_MATRIX_SLAVES 7 52#elif defined(CONFIG_AT91SAM9G45) 53#define AT91_MATRIX_MASTERS 11 54#define AT91_MATRIX_SLAVES 8 55#else 56#error CPU not supported. Please update at91_matrix.h 57#endif 58 59typedef struct at91_priority { 60 u32 a; 61 u32 b; 62} at91_priority_t; 63 64typedef struct at91_matrix { 65 u32 mcfg[AT91_MATRIX_MASTERS]; 66#if defined(CONFIG_AT91SAM9261) 67 u32 scfg[AT91_MATRIX_SLAVES]; 68 u32 res61_1[3]; 69 u32 tcr; 70 u32 res61_2[2]; 71 u32 csa; 72 u32 pucr; 73 u32 res61_3[114]; 74#else 75 u32 reserve1[16 - AT91_MATRIX_MASTERS]; 76 u32 scfg[AT91_MATRIX_SLAVES]; 77 u32 reserve2[16 - AT91_MATRIX_SLAVES]; 78 at91_priority_t pr[AT91_MATRIX_SLAVES]; 79 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; 80 u32 mrcr; /* 0x100 Master Remap Control */ 81 u32 reserve4[3]; 82#if defined(CONFIG_AT91SAM9G45) 83 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ 84 u32 womr; /* 0x1E4 Write Protect Mode */ 85 u32 wpsr; /* 0x1E8 Write Protect Status */ 86 u32 resg45_1[10]; 87#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 88 u32 res60_1[3]; 89 u32 csa; 90 u32 res60_2[56]; 91#elif defined(CONFIG_AT91SAM9263) 92 u32 res63_1; 93 u32 tcmr; 94 u32 res63_2[2]; 95 u32 csa[2]; 96 u32 res63_3[54]; 97#else 98 u32 reserve5[60]; 99#endif 100#endif 101} at91_matrix_t; 102 103#endif /* __ASSEMBLY__ */ 104 105#define AT91_MATRIX_CSA_DBPUC 0x00000100 106#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 107#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 108 109#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 110#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 111#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 112#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 113 114#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 115 116#endif 117