1/* 2 * MCF5227x Internal Memory Map 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __IMMAP_5227X__ 27#define __IMMAP_5227X__ 28 29/* Module Base Addresses */ 30#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) 31#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) 32#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) 33#define MMAP_CAN (CONFIG_SYS_MBAR + 0x00020000) 34#define MMAP_RTC (CONFIG_SYS_MBAR + 0x0003C000) 35#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040010) 36#define MMAP_SCM3 (CONFIG_SYS_MBAR + 0x00040070) 37#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) 38#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) 39#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) 40#define MMAP_IACK (CONFIG_SYS_MBAR + 0x00054000) 41#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) 42#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) 43#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) 44#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) 45#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) 46#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) 47#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) 48#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) 49#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) 50#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) 51#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) 52#define MMAP_PWM (CONFIG_SYS_MBAR + 0x00090000) 53#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00094000) 54#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) 55#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) 56#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) 57#define MMAP_ADC (CONFIG_SYS_MBAR + 0x000A8000) 58#define MMAP_LCD (CONFIG_SYS_MBAR + 0x000AC000) 59#define MMAP_LCD_BGLUT (CONFIG_SYS_MBAR + 0x000AC800) 60#define MMAP_LCD_GWLUT (CONFIG_SYS_MBAR + 0x000ACC00) 61#define MMAP_USBHW (CONFIG_SYS_MBAR + 0x000B0000) 62#define MMAP_USBCAPS (CONFIG_SYS_MBAR + 0x000B0100) 63#define MMAP_USBEHCI (CONFIG_SYS_MBAR + 0x000B0140) 64#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B01A0) 65#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) 66#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) 67#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) 68 69#include <asm/coldfire/crossbar.h> 70#include <asm/coldfire/dspi.h> 71#include <asm/coldfire/edma.h> 72#include <asm/coldfire/eport.h> 73#include <asm/coldfire/flexbus.h> 74#include <asm/coldfire/flexcan.h> 75#include <asm/coldfire/intctrl.h> 76#include <asm/coldfire/lcd.h> 77#include <asm/coldfire/pwm.h> 78#include <asm/coldfire/ssi.h> 79 80/* Reset Controller Module (RCM) */ 81typedef struct rcm { 82 u8 rcr; 83 u8 rsr; 84} rcm_t; 85 86/* Chip Configuration Module (CCM) */ 87typedef struct ccm { 88 u16 ccr; /* Chip Configuration (Rd-only) */ 89 u16 resv1; 90 u16 rcon; /* Reset Configuration (Rd-only) */ 91 u16 cir; /* Chip Identification (Rd-only) */ 92 u32 resv2; 93 u16 misccr; /* Miscellaneous Control */ 94 u16 cdr; /* Clock Divider */ 95 u16 uocsr; /* USB On-the-Go Controller Status */ 96 u16 resv4; 97 u16 sbfsr; /* Serial Boot Status */ 98 u16 sbfcr; /* Serial Boot Control */ 99} ccm_t; 100 101typedef struct canex_ctrl { 102 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ 103 u32 res0[0x700]; /* 0x100 */ 104 can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */ 105} canex_t; 106 107/* General Purpose I/O Module (GPIO) */ 108typedef struct gpio { 109 /* Port Output Data Registers */ 110 u8 podr_be; /* 0x00 */ 111 u8 podr_cs; /* 0x01 */ 112 u8 podr_fbctl; /* 0x02 */ 113 u8 podr_i2c; /* 0x03 */ 114 u8 rsvd1; /* 0x04 */ 115 u8 podr_uart; /* 0x05 */ 116 u8 podr_dspi; /* 0x06 */ 117 u8 podr_timer; /* 0x07 */ 118 u8 podr_lcdctl; /* 0x08 */ 119 u8 podr_lcddatah; /* 0x09 */ 120 u8 podr_lcddatam; /* 0x0A */ 121 u8 podr_lcddatal; /* 0x0B */ 122 123 /* Port Data Direction Registers */ 124 u8 pddr_be; /* 0x0C */ 125 u8 pddr_cs; /* 0x0D */ 126 u8 pddr_fbctl; /* 0x0E */ 127 u8 pddr_i2c; /* 0x0F */ 128 u8 rsvd2; /* 0x10 */ 129 u8 pddr_uart; /* 0x11 */ 130 u8 pddr_dspi; /* 0x12 */ 131 u8 pddr_timer; /* 0x13 */ 132 u8 pddr_lcdctl; /* 0x14 */ 133 u8 pddr_lcddatah; /* 0x15 */ 134 u8 pddr_lcddatam; /* 0x16 */ 135 u8 pddr_lcddatal; /* 0x17 */ 136 137 /* Port Pin Data/Set Data Registers */ 138 u8 ppdsdr_be; /* 0x18 */ 139 u8 ppdsdr_cs; /* 0x19 */ 140 u8 ppdsdr_fbctl; /* 0x1A */ 141 u8 ppdsdr_i2c; /* 0x1B */ 142 u8 rsvd3; /* 0x1C */ 143 u8 ppdsdr_uart; /* 0x1D */ 144 u8 ppdsdr_dspi; /* 0x1E */ 145 u8 ppdsdr_timer; /* 0x1F */ 146 u8 ppdsdr_lcdctl; /* 0x20 */ 147 u8 ppdsdr_lcddatah; /* 0x21 */ 148 u8 ppdsdr_lcddatam; /* 0x22 */ 149 u8 ppdsdr_lcddatal; /* 0x23 */ 150 151 /* Port Clear Output Data Registers */ 152 u8 pclrr_be; /* 0x24 */ 153 u8 pclrr_cs; /* 0x25 */ 154 u8 pclrr_fbctl; /* 0x26 */ 155 u8 pclrr_i2c; /* 0x27 */ 156 u8 rsvd4; /* 0x28 */ 157 u8 pclrr_uart; /* 0x29 */ 158 u8 pclrr_dspi; /* 0x2A */ 159 u8 pclrr_timer; /* 0x2B */ 160 u8 pclrr_lcdctl; /* 0x2C */ 161 u8 pclrr_lcddatah; /* 0x2D */ 162 u8 pclrr_lcddatam; /* 0x2E */ 163 u8 pclrr_lcddatal; /* 0x2F */ 164 165 /* Pin Assignment Registers */ 166 u8 par_be; /* 0x30 */ 167 u8 par_cs; /* 0x31 */ 168 u8 par_fbctl; /* 0x32 */ 169 u8 par_i2c; /* 0x33 */ 170 u16 par_uart; /* 0x34 */ 171 u8 par_dspi; /* 0x36 */ 172 u8 par_timer; /* 0x37 */ 173 u8 par_lcdctl; /* 0x38 */ 174 u8 par_irq; /* 0x39 */ 175 u16 rsvd6; /* 0x3A - 0x3B */ 176 u32 par_lcdh; /* 0x3C */ 177 u32 par_lcdl; /* 0x40 */ 178 179 /* Mode select control registers */ 180 u8 mscr_fb; /* 0x44 */ 181 u8 mscr_sdram; /* 0x45 */ 182 183 u16 rsvd7; /* 0x46 - 0x47 */ 184 u8 dscr_dspi; /* 0x48 */ 185 u8 dscr_timer; /* 0x49 */ 186 u8 dscr_i2c; /* 0x4A */ 187 u8 dscr_lcd; /* 0x4B */ 188 u8 dscr_debug; /* 0x4C */ 189 u8 dscr_clkrst; /* 0x4D */ 190 u8 dscr_irq; /* 0x4E */ 191 u8 dscr_uart; /* 0x4F */ 192} gpio_t; 193 194/* SDRAM Controller (SDRAMC) */ 195typedef struct sdramc { 196 u32 sdmr; /* Mode/Extended Mode */ 197 u32 sdcr; /* Control */ 198 u32 sdcfg1; /* Configuration 1 */ 199 u32 sdcfg2; /* Chip Select */ 200 u8 resv0[0x100]; 201 u32 sdcs0; /* Mode/Extended Mode */ 202 u32 sdcs1; /* Mode/Extended Mode */ 203} sdramc_t; 204 205/* Phase Locked Loop (PLL) */ 206typedef struct pll { 207 u32 pcr; /* PLL Control */ 208 u32 psr; /* PLL Status */ 209} pll_t; 210 211/* System Control Module register */ 212typedef struct scm1 { 213 u32 mpr; /* 0x00 Master Privilege */ 214 u32 rsvd1[7]; 215 u32 pacra; /* 0x20 */ 216 u32 pacrb; /* 0x24 */ 217 u32 pacrc; /* 0x28 */ 218 u32 pacrd; /* 0x2C */ 219 u32 rsvd2[4]; 220 u32 pacre; /* 0x40 */ 221 u32 pacrf; /* 0x44 */ 222 u32 pacrg; /* 0x48 */ 223 u32 rsvd3; 224 u32 pacri; /* 0x50 */ 225} scm1_t; 226 227typedef struct scm2_ctrl { 228 u8 res1[3]; /* 0x00 - 0x02 */ 229 u8 wcr; /* 0x03 wakeup control */ 230 u16 res2; /* 0x04 - 0x05 */ 231 u16 cwcr; /* 0x06 Core Watchdog Control */ 232 u8 res3[3]; /* 0x08 - 0x0A */ 233 u8 cwsr; /* 0x0B Core Watchdog Service */ 234 u8 res4[2]; /* 0x0C - 0x0D */ 235 u8 scmisr; /* 0x0F Interrupt Status */ 236 u32 res5; /* 0x20 */ 237 u32 bcr; /* 0x24 Burst Configuration */ 238} scm2_t; 239 240typedef struct scm3_ctrl { 241 u32 cfadr; /* 0x00 Core Fault Address */ 242 u8 res7; /* 0x04 */ 243 u8 cfier; /* 0x05 Core Fault Interrupt Enable */ 244 u8 cfloc; /* 0x06 Core Fault Location */ 245 u8 cfatr; /* 0x07 Core Fault Attributes */ 246 u32 cfdtr; /* 0x08 Core Fault Data */ 247} scm3_t; 248 249typedef struct rtcex { 250 u32 rsvd1[3]; 251 u32 gocu; 252 u32 gocl; 253} rtcex_t; 254#endif /* __IMMAP_5227X__ */ 255