1/* 2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> 3 * 4 * (C) Copyright 2008-2009 5 * Stefan Roese, DENX Software Engineering, sr@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef _PPC4xx_UIC_H_ 27#define _PPC4xx_UIC_H_ 28 29/* 30 * Define the number of UIC's 31 */ 32#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ 33 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 34 defined(CONFIG_460SX) 35#define UIC_MAX 4 36#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 37 defined(CONFIG_405EX) 38#define UIC_MAX 3 39#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ 40 defined(CONFIG_440EP) || defined(CONFIG_440GR) 41#define UIC_MAX 2 42#else 43#define UIC_MAX 1 44#endif 45 46#define IRQ_MAX (UIC_MAX * 32) 47 48/* 49 * UIC register 50 */ 51#define UIC_SR 0x0 /* UIC status */ 52#define UIC_ER 0x2 /* UIC enable */ 53#define UIC_CR 0x3 /* UIC critical */ 54#define UIC_PR 0x4 /* UIC polarity */ 55#define UIC_TR 0x5 /* UIC triggering */ 56#define UIC_MSR 0x6 /* UIC masked status */ 57#define UIC_VR 0x7 /* UIC vector */ 58#define UIC_VCR 0x8 /* UIC vector configuration */ 59 60/* 61 * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's 62 * are cascaded on. With this trick we can use the common UIC code for 440GX 63 * too. 64 */ 65#if defined(CONFIG_440GX) 66#define UIC0_DCR_BASE 0x200 67#define UIC1_DCR_BASE 0xc0 68#define UIC2_DCR_BASE 0xd0 69#define UIC3_DCR_BASE 0x210 70#else 71#define UIC0_DCR_BASE 0xc0 72#define UIC1_DCR_BASE 0xd0 73#define UIC2_DCR_BASE 0xe0 74#define UIC3_DCR_BASE 0xf0 75#endif 76 77#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */ 78#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */ 79#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */ 80#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ 81#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ 82#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ 83#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */ 84#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ 85 86#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */ 87#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */ 88#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */ 89#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ 90#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ 91#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ 92#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */ 93#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ 94 95#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ 96#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */ 97#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */ 98#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ 99#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ 100#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ 101#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */ 102#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ 103 104#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ 105#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */ 106#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */ 107#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ 108#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ 109#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ 110#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */ 111#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ 112 113/* 114 * Now the interrupt vector definitions. They are different for most of 115 * the 4xx variants, so we need some more #ifdef's here. No mask 116 * definitions anymore here. For this please use the UIC_MASK macro below. 117 * 118 * Note: Please only define the interrupts really used in U-Boot here. 119 * Those are the cascading and EMAC/MAL related interrupt. 120 */ 121 122#if defined(CONFIG_405EP) || defined(CONFIG_405GP) 123#define VECNUM_MAL_SERR 10 124#define VECNUM_MAL_TXEOB 11 125#define VECNUM_MAL_RXEOB 12 126#define VECNUM_MAL_TXDE 13 127#define VECNUM_MAL_RXDE 14 128#define VECNUM_ETH0 15 129#define VECNUM_ETH1_OFFS 2 130#define VECNUM_EIRQ6 29 131#endif /* defined(CONFIG_405EP) */ 132 133#if defined(CONFIG_405EZ) 134#define VECNUM_USBDEV 15 135#define VECNUM_ETH0 16 136#define VECNUM_MAL_SERR 18 137#define VECNUM_MAL_TXDE 18 138#define VECNUM_MAL_RXDE 18 139#define VECNUM_MAL_TXEOB 19 140#define VECNUM_MAL_RXEOB 21 141#endif /* CONFIG_405EX */ 142 143#if defined(CONFIG_405EX) 144/* UIC 0 */ 145#define VECNUM_MAL_TXEOB 10 146#define VECNUM_MAL_RXEOB 11 147#define VECNUM_ETH0 24 148#define VECNUM_ETH1_OFFS 1 149#define VECNUM_UIC2NCI 28 150#define VECNUM_UIC2CI 29 151#define VECNUM_UIC1NCI 30 152#define VECNUM_UIC1CI 31 153 154/* UIC 1 */ 155#define VECNUM_MAL_SERR (32 + 0) 156#define VECNUM_MAL_TXDE (32 + 1) 157#define VECNUM_MAL_RXDE (32 + 2) 158#endif /* CONFIG_405EX */ 159 160#if defined(CONFIG_440GP) || \ 161 defined(CONFIG_440EP) || defined(CONFIG_440GR) 162/* UIC 0 */ 163#define VECNUM_MAL_TXEOB 10 164#define VECNUM_MAL_RXEOB 11 165#define VECNUM_UIC1NCI 30 166#define VECNUM_UIC1CI 31 167 168/* UIC 1 */ 169#define VECNUM_MAL_SERR (32 + 0) 170#define VECNUM_MAL_TXDE (32 + 1) 171#define VECNUM_MAL_RXDE (32 + 2) 172#define VECNUM_USBDEV (32 + 23) 173#define VECNUM_ETH0 (32 + 28) 174#define VECNUM_ETH1_OFFS 2 175#endif /* CONFIG_440GP */ 176 177#if defined(CONFIG_440GX) 178/* UICB 0 (440GX only) */ 179/* 180 * All those defines below are off-by-one, so that the common UIC code 181 * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc. 182 */ 183#define VECNUM_UIC1CI 0 184#define VECNUM_UIC1NCI 1 185#define VECNUM_UIC2CI 2 186#define VECNUM_UIC2NCI 3 187#define VECNUM_UIC3CI 4 188#define VECNUM_UIC3NCI 5 189 190/* UIC 0, used as UIC1 on 440GX because of UICB0 */ 191#define VECNUM_MAL_TXEOB (32 + 10) 192#define VECNUM_MAL_RXEOB (32 + 11) 193 194/* UIC 1, used as UIC2 on 440GX because of UICB0 */ 195#define VECNUM_MAL_SERR (64 + 0) 196#define VECNUM_MAL_TXDE (64 + 1) 197#define VECNUM_MAL_RXDE (64 + 2) 198#define VECNUM_ETH0 (64 + 28) 199#define VECNUM_ETH1_OFFS 2 200#endif /* CONFIG_440GX */ 201 202#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 203/* UIC 0 */ 204#define VECNUM_MAL_TXEOB 10 205#define VECNUM_MAL_RXEOB 11 206#define VECNUM_USBDEV 20 207#define VECNUM_ETH0 24 208#define VECNUM_ETH1_OFFS 1 209#define VECNUM_UIC2NCI 28 210#define VECNUM_UIC2CI 29 211#define VECNUM_UIC1NCI 30 212#define VECNUM_UIC1CI 31 213 214/* UIC 1 */ 215#define VECNUM_MAL_SERR (32 + 0) 216#define VECNUM_MAL_TXDE (32 + 1) 217#define VECNUM_MAL_RXDE (32 + 2) 218 219/* UIC 2 */ 220#define VECNUM_EIRQ2 (64 + 3) 221#endif /* CONFIG_440EPX */ 222 223#if defined(CONFIG_440SP) 224/* UIC 0 */ 225#define VECNUM_UIC1NCI 30 226#define VECNUM_UIC1CI 31 227 228/* UIC 1 */ 229#define VECNUM_MAL_SERR (32 + 1) 230#define VECNUM_MAL_TXDE (32 + 2) 231#define VECNUM_MAL_RXDE (32 + 3) 232#define VECNUM_MAL_TXEOB (32 + 6) 233#define VECNUM_MAL_RXEOB (32 + 7) 234#define VECNUM_ETH0 (32 + 28) 235#endif /* CONFIG_440SP */ 236 237#if defined(CONFIG_440SPE) 238/* UIC 0 */ 239#define VECNUM_UIC2NCI 10 240#define VECNUM_UIC2CI 11 241#define VECNUM_UIC3NCI 16 242#define VECNUM_UIC3CI 17 243#define VECNUM_UIC1NCI 30 244#define VECNUM_UIC1CI 31 245 246/* UIC 1 */ 247#define VECNUM_MAL_SERR (32 + 1) 248#define VECNUM_MAL_TXDE (32 + 2) 249#define VECNUM_MAL_RXDE (32 + 3) 250#define VECNUM_MAL_TXEOB (32 + 6) 251#define VECNUM_MAL_RXEOB (32 + 7) 252#define VECNUM_ETH0 (32 + 28) 253#endif /* CONFIG_440SPE */ 254 255#if defined(CONFIG_460EX) || defined(CONFIG_460GT) 256/* UIC 0 */ 257#define VECNUM_UIC2NCI 10 258#define VECNUM_UIC2CI 11 259#define VECNUM_UIC3NCI 16 260#define VECNUM_UIC3CI 17 261#define VECNUM_UIC1NCI 30 262#define VECNUM_UIC1CI 31 263 264/* UIC 2 */ 265#define VECNUM_MAL_SERR (64 + 3) 266#define VECNUM_MAL_TXDE (64 + 4) 267#define VECNUM_MAL_RXDE (64 + 5) 268#define VECNUM_MAL_TXEOB (64 + 6) 269#define VECNUM_MAL_RXEOB (64 + 7) 270#define VECNUM_ETH0 (64 + 16) 271#define VECNUM_ETH1_OFFS 1 272#endif /* CONFIG_460EX */ 273 274#if defined(CONFIG_460SX) 275/* UIC 0 */ 276#define VECNUM_UIC2NCI 10 277#define VECNUM_UIC2CI 11 278#define VECNUM_UIC3NCI 16 279#define VECNUM_UIC3CI 17 280#define VECNUM_ETH0 19 281#define VECNUM_ETH1_OFFS 1 282#define VECNUM_UIC1NCI 30 283#define VECNUM_UIC1CI 31 284 285/* UIC 1 */ 286#define VECNUM_MAL_SERR (32 + 1) 287#define VECNUM_MAL_TXDE (32 + 2) 288#define VECNUM_MAL_RXDE (32 + 3) 289#define VECNUM_MAL_TXEOB (32 + 6) 290#define VECNUM_MAL_RXEOB (32 + 7) 291#endif /* CONFIG_460EX */ 292 293#if !defined(VECNUM_ETH1_OFFS) 294#define VECNUM_ETH1_OFFS 1 295#endif 296 297/* 298 * Mask definitions (used for example in 4xx_enet.c) 299 */ 300#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) 301/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ 302#define UIC_NR(vec) ((vec) >> 5) 303 304#endif /* _PPC4xx_UIC_H_ */ 305