1/* 2 * (C) Copyright 2000 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 37#define CONFIG_ETX094 1 /* ...on a ETX_094 board */ 38 39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 40#undef CONFIG_8xx_CONS_SMC2 41#undef CONFIG_8xx_CONS_NONE 42#define CONFIG_BAUDRATE 57600 43#if 0 44#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 45#else 46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47#endif 48 49#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 50 51#define CONFIG_BOARD_TYPES 1 /* support board types */ 52 53#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ 54#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ 55#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ 56 57#define CONFIG_ETHADDR 08:00:06:00:00:00 58 59#ifdef CONFIG_ETHADDR 60#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */ 61#endif 62 63#undef CONFIG_BOOTARGS 64#define CONFIG_RAMBOOTCOMMAND \ 65 "bootp; " \ 66 "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \ 67 "U-Boot_version=U-Boot-1.0.x-Date " \ 68 "panic=1 " \ 69 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 70 "bootm" 71#define CONFIG_NFSBOOTCOMMAND \ 72 "bootp; " \ 73 "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \ 74 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 75 "bootm" 76#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 77 78#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 79#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 80 81#define CONFIG_WATCHDOG 1 /* watchdog enabled */ 82 83#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 84 85 86/* 87 * BOOTP options 88 */ 89#define CONFIG_BOOTP_SUBNETMASK 90#define CONFIG_BOOTP_GATEWAY 91#define CONFIG_BOOTP_HOSTNAME 92#define CONFIG_BOOTP_BOOTPATH 93#define CONFIG_BOOTP_BOOTFILESIZE 94 95 96/* 97 * Command line configuration. 98 */ 99#include <config_cmd_default.h> 100 101 102/* 103 * Miscellaneous configurable options 104 */ 105#define CONFIG_SYS_LONGHELP /* undef to save memory */ 106#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 107#if defined(CONFIG_CMD_KGDB) 108#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 109#else 110#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 111#endif 112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 115 116#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ 117#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ 118 119#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 120 121#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 122 123#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 124 125/* 126 * Low Level Configuration Settings 127 * (address mappings, register initial values, etc.) 128 * You should know what you are doing if you make changes here. 129 */ 130/*----------------------------------------------------------------------- 131 * Internal Memory Mapped Register 132 */ 133#define CONFIG_SYS_IMMR 0xFFF00000 134 135/*----------------------------------------------------------------------- 136 * Definitions for initial stack pointer and data area (in DPRAM) 137 */ 138#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 139#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 140#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 141#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 142#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 143 144/*----------------------------------------------------------------------- 145 * Start addresses for the final memory configuration 146 * (Set up by the startup code) 147 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 148 */ 149#define CONFIG_SYS_SDRAM_BASE 0x00000000 150#define CONFIG_SYS_FLASH_BASE 0x40000000 151#ifdef DEBUG 152#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 153#else 154#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 155#endif 156#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 157#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 158 159/* 160 * For booting Linux, the board info and command line data 161 * have to be in the first 8 MB of memory, since this is 162 * the maximum mapped by the Linux kernel during initialization. 163 */ 164#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 165/*----------------------------------------------------------------------- 166 * FLASH organization 167 */ 168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 169#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 170 171#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 172#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ 173 174#define CONFIG_ENV_IS_IN_FLASH 1 175#ifdef CONFIG_FLASH_16BIT 176#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 177#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ 178#else 179#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 180#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 181#endif 182 183/*----------------------------------------------------------------------- 184 * Hardware Information Block 185 */ 186#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 187#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 188#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 189 190/*----------------------------------------------------------------------- 191 * Cache Configuration 192 */ 193#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 194#if defined(CONFIG_CMD_KGDB) 195#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 196#endif 197 198/*----------------------------------------------------------------------- 199 * SYPCR - System Protection Control 11-9 200 * SYPCR can only be written once after reset! 201 *----------------------------------------------------------------------- 202 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 203 */ 204#if defined(CONFIG_WATCHDOG) 205#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 206 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 207#else 208#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 209#endif /* CONFIG_WATCHDOG */ 210 211/*----------------------------------------------------------------------- 212 * SIUMCR - SIU Module Configuration 11-6 213 *----------------------------------------------------------------------- 214 * PCMCIA config., multi-function pin tri-state 215 */ 216#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 217 218/*----------------------------------------------------------------------- 219 * TBSCR - Time Base Status and Control 11-26 220 *----------------------------------------------------------------------- 221 * Clear Reference Interrupt Status, Timebase freezing enabled 222 */ 223#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 224 225/*----------------------------------------------------------------------- 226 * RTCSC - Real-Time Clock Status and Control Register 11-27 227 *----------------------------------------------------------------------- 228 */ 229#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 230 231/*----------------------------------------------------------------------- 232 * PISCR - Periodic Interrupt Status and Control 11-31 233 *----------------------------------------------------------------------- 234 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 235 */ 236#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 237 238/*----------------------------------------------------------------------- 239 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 240 *----------------------------------------------------------------------- 241 * Reset PLL lock status sticky bit, timer expired status bit and timer 242 * interrupt status bit - leave PLL multiplication factor unchanged ! 243 */ 244#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 245 246/*----------------------------------------------------------------------- 247 * SCCR - System Clock and reset Control Register 15-27 248 *----------------------------------------------------------------------- 249 * Set clock output, timebase and RTC source and divider, 250 * power management and some other internal clocks 251 */ 252#define SCCR_MASK SCCR_EBDF11 253#define CONFIG_SYS_SCCR (SCCR_TBS | \ 254 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 255 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 256 SCCR_DFALCD00) 257 258/*----------------------------------------------------------------------- 259 * PCMCIA stuff 260 *----------------------------------------------------------------------- 261 * 262 */ 263#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 264#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 265#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 266#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 267#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 268#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 269#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 270#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 271 272/*----------------------------------------------------------------------- 273 * 274 *----------------------------------------------------------------------- 275 * 276 */ 277#define CONFIG_SYS_DER 0 278 279/* 280 * Init Memory Controller: 281 * 282 * BR0/1 and OR0/1 (FLASH) 283 */ 284 285#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 286#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 287 288/* used to re-map FLASH both when starting from SRAM or FLASH: 289 * restrict access enough to keep SRAM working (if any) 290 * but not too much to meddle with FLASH accesses 291 */ 292#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 293#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 294 295/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ 296#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ 297 OR_SCY_2_CLK | OR_TRLX ) 298 299#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 300#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 301 302#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */ 303#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) 304#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) 305#else /* 32 bit data port */ 306#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) 307#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32) 308#endif /* CONFIG_FLASH_16BIT */ 309 310#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 311#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 312 313/* 314 * BR2/3 and OR2/3 (SDRAM) 315 * 316 */ 317#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 318#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 319#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 320 321/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 322#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 323 324#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 325#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 326 327#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 328#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 329 330/* 331 * Memory Periodic Timer Prescaler 332 */ 333 334/* periodic timer for refresh */ 335#define CONFIG_SYS_MAMR_PTA 23 /* start with divider for 100 MHz */ 336 337/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 338#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 339#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 340 341/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 342#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 343#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 344 345/* 346 * MAMR settings for SDRAM 347 */ 348 349/* 8 column SDRAM */ 350#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 351 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 352 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) 353/* 9 column SDRAM */ 354#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 355 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 356 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) 357 358 359/* 360 * Internal Definitions 361 * 362 * Boot Flags 363 */ 364#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 365#define BOOTFLAG_WARM 0x02 /* Software reboot */ 366 367#endif /* __CONFIG_H */ 368