1/* 2 * (C) Copyright 2000 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * Keith Outwater, keith_outwater@mvis.com 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25/* 26 * board/config_GEN860T.h - board specific configuration options 27 */ 28 29#ifndef __CONFIG_GEN860T_H 30#define __CONFIG_H 31 32/* 33 * High Level Configuration Options 34 */ 35#define CONFIG_MPC860 36#define CONFIG_GEN860T 37 38/* 39 * Identify the board 40 */ 41#if !defined(CONFIG_SC) 42#define CONFIG_IDENT_STRING " B2" 43#else 44#define CONFIG_IDENT_STRING " SC" 45#endif 46 47/* 48 * Don't depend on the RTC clock to determine clock frequency - 49 * the 860's internal rtc uses a 32.768 KHz clock which is 50 * generated by the DS1337 - and the DS1337 clock can be turned off. 51 */ 52#if !defined(CONFIG_SC) 53#define CONFIG_8xx_GCLK_FREQ 66600000 54#else 55#define CONFIG_8xx_GCLK_FREQ 48000000 56#endif 57 58/* 59 * The RS-232 console port is on SMC1 60 */ 61#define CONFIG_8xx_CONS_SMC1 62#define CONFIG_BAUDRATE 38400 63 64/* 65 * Set allowable console baud rates 66 */ 67#define CONFIG_SYS_BAUDRATE_TABLE { 9600, \ 68 19200, \ 69 38400, \ 70 57600, \ 71 115200, \ 72 } 73 74/* 75 * Print console information 76 */ 77#undef CONFIG_SYS_CONSOLE_INFO_QUIET 78 79/* 80 * Set the autoboot delay in seconds. A delay of -1 disables autoboot 81 */ 82#define CONFIG_BOOTDELAY 5 83 84/* 85 * Pass the clock frequency to the Linux kernel in units of MHz 86 */ 87#define CONFIG_CLOCKS_IN_MHZ 88 89#define CONFIG_PREBOOT \ 90 "echo;echo" 91 92#undef CONFIG_BOOTARGS 93#define CONFIG_BOOTCOMMAND \ 94 "bootp;" \ 95 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 96 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 97 "bootm" 98 99/* 100 * Turn off echo for serial download by default. Allow baud rate to be changed 101 * for downloads 102 */ 103#undef CONFIG_LOADS_ECHO 104#define CONFIG_SYS_LOADS_BAUD_CHANGE 105 106/* 107 * Set default load address for tftp network downloads 108 */ 109#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 110 111/* 112 * Turn off the watchdog timer 113 */ 114#undef CONFIG_WATCHDOG 115 116/* 117 * Do not reboot if a panic occurs 118 */ 119#define CONFIG_PANIC_HANG 120 121/* 122 * Enable the status LED 123 */ 124#define CONFIG_STATUS_LED 125 126/* 127 * Reset address. We pick an address such that when an instruction 128 * is executed at that address, a machine check exception occurs 129 */ 130#define CONFIG_SYS_RESET_ADDRESS ((ulong) -1) 131 132/* 133 * BOOTP options 134 */ 135#define CONFIG_BOOTP_SUBNETMASK 136#define CONFIG_BOOTP_GATEWAY 137#define CONFIG_BOOTP_HOSTNAME 138#define CONFIG_BOOTP_BOOTPATH 139#define CONFIG_BOOTP_BOOTFILESIZE 140 141 142/* 143 * The GEN860T network interface uses the on-chip 10/100 FEC with 144 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's 145 * MII address is hardwired on the board to zero. 146 */ 147#define CONFIG_FEC_ENET 148#define CONFIG_SYS_DISCOVER_PHY 149#define CONFIG_MII 150#define CONFIG_MII_INIT 1 151#define CONFIG_PHY_ADDR 0 152 153/* 154 * Set default IP stuff just to get bootstrap entries into the 155 * environment so that we can source the full default environment. 156 */ 157#define CONFIG_ETHADDR 9a:52:63:15:85:25 158#define CONFIG_SERVERIP 10.0.4.201 159#define CONFIG_IPADDR 10.0.4.111 160 161/* 162 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to 163 * the MPC860T I2C interface. 164 */ 165#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 166#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ 167#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ 168#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ 169#define CONFIG_ENV_EEPROM_SIZE (32 * 1024) 170 171/* 172 * Enable I2C and select the hardware/software driver 173 */ 174#define CONFIG_HARD_I2C 1 /* CPM based I2C */ 175#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ 176 177#ifdef CONFIG_HARD_I2C 178#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */ 179#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */ 180#endif 181 182#ifdef CONFIG_SOFT_I2C 183#define PB_SCL 0x00000020 /* PB 26 */ 184#define PB_SDA 0x00000010 /* PB 27 */ 185#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 186#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 187#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 188#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 189#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 190 else immr->im_cpm.cp_pbdat &= ~PB_SDA 191#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 192 else immr->im_cpm.cp_pbdat &= ~PB_SCL 193#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 194#endif 195 196/* 197 * Allow environment overwrites by anyone 198 */ 199#define CONFIG_ENV_OVERWRITE 200 201#if !defined(CONFIG_SC) 202/* 203 * The MPC860's internal RTC is horribly broken in rev D masks. Three 204 * internal MPC860T circuit nodes were inadvertently left floating; this 205 * causes KAPWR current in power down mode to be three orders of magnitude 206 * higher than specified in the datasheet (from 10 uA to 10 mA). No 207 * reasonable battery can keep that kind RTC running during powerdown for any 208 * length of time, so we use an external RTC on the I2C bus instead. 209 */ 210#define CONFIG_RTC_DS1337 211#define CONFIG_SYS_I2C_RTC_ADDR 0x68 212 213#else 214/* 215 * No external RTC on SC variant, so we're stuck with the internal one. 216 */ 217#define CONFIG_RTC_MPC8xx 218#endif 219 220/* 221 * Power On Self Test support 222 */ 223#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \ 224 CONFIG_SYS_POST_MEMORY | \ 225 CONFIG_SYS_POST_CPU | \ 226 CONFIG_SYS_POST_UART | \ 227 CONFIG_SYS_POST_SPR ) 228 229 230/* 231 * Command line configuration. 232 */ 233#include <config_cmd_default.h> 234 235#define CONFIG_CMD_ASKENV 236#define CONFIG_CMD_DHCP 237#define CONFIG_CMD_I2C 238#define CONFIG_CMD_EEPROM 239#define CONFIG_CMD_REGINFO 240#define CONFIG_CMD_IMMAP 241#define CONFIG_CMD_ELF 242#define CONFIG_CMD_DATE 243#define CONFIG_CMD_FPGA 244#define CONFIG_CMD_MII 245#define CONFIG_CMD_BEDBUG 246 247#ifdef CONFIG_POST 248#define CONFIG_CMD_DIAG 249#endif 250 251/* 252 * There is no IDE/PCMCIA hardware support on the board. 253 */ 254#undef CONFIG_IDE_PCMCIA 255#undef CONFIG_IDE_LED 256#undef CONFIG_IDE_RESET 257 258/* 259 * Enable the call to misc_init_r() for miscellaneous platform 260 * dependent initialization. 261 */ 262#define CONFIG_MISC_INIT_R 263 264/* 265 * Enable call to last_stage_init() so we can twiddle some LEDS :) 266 */ 267#define CONFIG_LAST_STAGE_INIT 268 269/* 270 * Virtex2 FPGA configuration support 271 */ 272#define CONFIG_FPGA_COUNT 1 273#define CONFIG_FPGA 274#define CONFIG_FPGA_XILINX 275#define CONFIG_FPGA_VIRTEX2 276#define CONFIG_SYS_FPGA_PROG_FEEDBACK 277 278/* 279 * Verbose help from command monitor. 280 */ 281#define CONFIG_SYS_LONGHELP 282#if !defined(CONFIG_SC) 283#define CONFIG_SYS_PROMPT "B2> " 284#else 285#define CONFIG_SYS_PROMPT "SC> " 286#endif 287 288 289/* 290 * Use the "hush" command parser 291 */ 292#define CONFIG_SYS_HUSH_PARSER 293#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 294 295/* 296 * Set buffer size for console I/O 297 */ 298#if defined(CONFIG_CMD_KGDB) 299#define CONFIG_SYS_CBSIZE 1024 300#else 301#define CONFIG_SYS_CBSIZE 256 302#endif 303 304/* 305 * Print buffer size 306 */ 307#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 308 309/* 310 * Maximum number of arguments that a command can accept 311 */ 312#define CONFIG_SYS_MAXARGS 16 313 314/* 315 * Boot argument buffer size 316 */ 317#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 318 319/* 320 * Default memory test range 321 */ 322#define CONFIG_SYS_MEMTEST_START 0x0100000 323#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (128 * 1024)) 324 325/* 326 * Select the more full-featured memory test 327 */ 328#define CONFIG_SYS_ALT_MEMTEST 329 330/* 331 * Default load address 332 */ 333#define CONFIG_SYS_LOAD_ADDR 0x01000000 334 335/* 336 * Set decrementer frequency (1 ms ticks) 337 */ 338#define CONFIG_SYS_HZ 1000 339 340/* 341 * Device memory map (after SDRAM remap to 0x0): 342 * 343 * CS Device Base Addr Size 344 * ---------------------------------------------------- 345 * CS0* Flash 0x40000000 64 M 346 * CS1* SDRAM 0x00000000 16 M 347 * CS2* Disk-On-Chip 0x50000000 32 K 348 * CS3* FPGA 0x60000000 64 M 349 * CS4* SelectMap 0x70000000 32 K 350 * CS5* Mil-Std 1553 I/F 0x80000000 32 K 351 * CS6* Unused 352 * CS7* Unused 353 * IMMR 860T Registers 0xfff00000 354 */ 355 356/* 357 * Base addresses and block sizes 358 */ 359#define CONFIG_SYS_IMMR 0xFF000000 360 361#define SDRAM_BASE 0x00000000 362#define SDRAM_SIZE (64 * 1024 * 1024) 363 364#define FLASH_BASE 0x40000000 365#define FLASH_SIZE (16 * 1024 * 1024) 366 367#define DOC_BASE 0x50000000 368#define DOC_SIZE (32 * 1024) 369 370#define FPGA_BASE 0x60000000 371#define FPGA_SIZE (64 * 1024 * 1024) 372 373#define SELECTMAP_BASE 0x70000000 374#define SELECTMAP_SIZE (32 * 1024) 375 376#define M1553_BASE 0x80000000 377#define M1553_SIZE (64 * 1024) 378 379/* 380 * Definitions for initial stack pointer and data area (in DPRAM) 381 */ 382#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 383#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 384#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ 385#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE) 386#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 387 388/* 389 * Start addresses for the final memory configuration 390 * (Set up by the startup code) 391 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 392 */ 393#define CONFIG_SYS_SDRAM_BASE SDRAM_BASE 394 395/* 396 * FLASH organization 397 */ 398#define CONFIG_SYS_FLASH_BASE FLASH_BASE 399#define CONFIG_SYS_FLASH_SIZE FLASH_SIZE 400#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) 401#define CONFIG_SYS_MAX_FLASH_BANKS 1 402#define CONFIG_SYS_MAX_FLASH_SECT 128 403 404/* 405 * The timeout values are for an entire chip and are in milliseconds. 406 * Yes I know that the write timeout is huge. Accroding to the 407 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst 408 * case VCC and temp after 100K programming cycles. It works out 409 * to 280 minutes (might as well be forever). 410 */ 411#define CONFIG_SYS_FLASH_ERASE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 5000) 412#define CONFIG_SYS_FLASH_WRITE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1) 413 414/* 415 * Allow direct writes to FLASH from tftp transfers (** dangerous **) 416 */ 417#define CONFIG_SYS_DIRECT_FLASH_TFTP 418 419/* 420 * Reserve memory for U-Boot. 421 */ 422#define CONFIG_SYS_MAX_UBOOT_SECTS 4 423#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE) 424#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 425 426/* 427 * Select environment placement. NOTE that u-boot.lds must 428 * be edited if this is changed! 429 */ 430#undef CONFIG_ENV_IS_IN_FLASH 431#define CONFIG_ENV_IS_IN_EEPROM 432 433#if defined(CONFIG_ENV_IS_IN_EEPROM) 434#define CONFIG_ENV_SIZE (2 * 1024) 435#define CONFIG_ENV_OFFSET (CONFIG_ENV_EEPROM_SIZE - (8 * 1024)) 436#else 437#define CONFIG_ENV_SIZE 0x1000 438#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE 439 440/* 441 * This ultimately gets passed right into the linker script, so we have to 442 * use a number :( 443 */ 444#define CONFIG_ENV_OFFSET 0x060000 445#endif 446 447/* 448 * Reserve memory for malloc() 449 */ 450#define CONFIG_SYS_MALLOC_LEN (128 * 1024) 451 452/* 453 * For booting Linux, the board info and command line data 454 * have to be in the first 8 MB of memory, since this is 455 * the maximum mapped by the Linux kernel during initialization. 456 */ 457#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 458 459/* 460 * Cache Configuration 461 */ 462#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 463#if defined(CONFIG_CMD_KGDB) 464#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of above value */ 465#endif 466 467/*------------------------------------------------------------------------ 468 * SYPCR - System Protection Control UM 11-9 469 * ----------------------------------------------------------------------- 470 * SYPCR can only be written once after reset! 471 * 472 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 473 */ 474#if defined(CONFIG_WATCHDOG) 475#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ 476 SYPCR_BMT | \ 477 SYPCR_BME | \ 478 SYPCR_SWF | \ 479 SYPCR_SWE | \ 480 SYPCR_SWRI | \ 481 SYPCR_SWP \ 482 ) 483#else 484#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \ 485 SYPCR_BMT | \ 486 SYPCR_BME | \ 487 SYPCR_SWF | \ 488 SYPCR_SWP \ 489 ) 490#endif 491 492/*----------------------------------------------------------------------- 493 * SIUMCR - SIU Module Configuration UM 11-6 494 *----------------------------------------------------------------------- 495 * Set debug pin mux, enable SPKROUT and GPLB5*. 496 */ 497#define CONFIG_SYS_SIUMCR ( SIUMCR_DBGC11 | \ 498 SIUMCR_DBPC11 | \ 499 SIUMCR_MLRC11 | \ 500 SIUMCR_GB5E \ 501 ) 502 503/*----------------------------------------------------------------------- 504 * TBSCR - Time Base Status and Control UM 11-26 505 *----------------------------------------------------------------------- 506 * Clear Reference Interrupt Status, Timebase freeze enabled 507 */ 508#define CONFIG_SYS_TBSCR ( TBSCR_REFA | \ 509 TBSCR_REFB | \ 510 TBSCR_TBF \ 511 ) 512 513/*----------------------------------------------------------------------- 514 * RTCSC - Real-Time Clock Status and Control Register UM 11-27 515 *----------------------------------------------------------------------- 516 */ 517#define CONFIG_SYS_RTCSC ( RTCSC_SEC | \ 518 RTCSC_ALR | \ 519 RTCSC_RTF | \ 520 RTCSC_RTE \ 521 ) 522 523/*----------------------------------------------------------------------- 524 * PISCR - Periodic Interrupt Status and Control UM 11-31 525 *----------------------------------------------------------------------- 526 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 527 */ 528#define CONFIG_SYS_PISCR ( PISCR_PS | \ 529 PISCR_PITF \ 530 ) 531 532/*----------------------------------------------------------------------- 533 * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 534 *----------------------------------------------------------------------- 535 * Reset PLL lock status sticky bit, timer expired status bit and timer 536 * interrupt status bit. Set MF for 1:2:1 mode. 537 */ 538#define CONFIG_SYS_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ 539 PLPRCR_SPLSS | \ 540 PLPRCR_TEXPS | \ 541 PLPRCR_TMIST \ 542 ) 543 544/*----------------------------------------------------------------------- 545 * SCCR - System Clock and reset Control Register UM 15-27 546 *----------------------------------------------------------------------- 547 * Set clock output, timebase and RTC source and divider, 548 * power management and some other internal clocks 549 */ 550#define SCCR_MASK SCCR_EBDF11 551 552#if !defined(CONFIG_SC) 553#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ 554 SCCR_COM00 | /* full strength CLKOUT */ \ 555 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ 556 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ 557 SCCR_DFNL000 | \ 558 SCCR_DFNH000 \ 559 ) 560#else 561#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ 562 SCCR_COM00 | /* full strength CLKOUT */ \ 563 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ 564 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ 565 SCCR_DFNL000 | \ 566 SCCR_DFNH000 | \ 567 SCCR_RTDIV | \ 568 SCCR_RTSEL \ 569 ) 570#endif 571 572/*----------------------------------------------------------------------- 573 * DER - Debug Enable Register UM 37-46 574 *----------------------------------------------------------------------- 575 * Mask all events that can cause entry into debug mode 576 */ 577#define CONFIG_SYS_DER 0 578 579/* 580 * Initialize Memory Controller: 581 * 582 * BR0 and OR0 (FLASH memory) 583 */ 584#define FLASH_BASE0_PRELIM FLASH_BASE 585 586/* 587 * Flash address mask 588 */ 589#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000 590 591/* 592 * FLASH timing: 593 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 594 */ 595#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | \ 596 OR_ACS_DIV2 | \ 597 OR_BI | \ 598 OR_SCY_2_CLK | \ 599 OR_TRLX | \ 600 OR_EHTR \ 601 ) 602 603#define CONFIG_SYS_OR0_PRELIM ( CONFIG_SYS_PRELIM_OR_AM | \ 604 CONFIG_SYS_OR_TIMING_FLASH \ 605 ) 606 607#define CONFIG_SYS_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ 608 BR_MS_GPCM | \ 609 BR_PS_8 | \ 610 BR_V \ 611 ) 612 613/* 614 * SDRAM configuration 615 */ 616#define CONFIG_SYS_OR1_AM 0xfc000000 617#define CONFIG_SYS_OR1 ( (CONFIG_SYS_OR1_AM & OR_AM_MSK) | \ 618 OR_CSNT_SAM \ 619 ) 620 621#define CONFIG_SYS_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ 622 BR_MS_UPMA | \ 623 BR_PS_32 | \ 624 BR_V \ 625 ) 626 627/* 628 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank 629 * of 256 MBit SDRAM 630 */ 631#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 632 633/* 634 * Periodic timer for refresh @ 33 MHz system clock 635 */ 636#define CONFIG_SYS_MAMR_PTA 64 637 638/* 639 * MAMR settings for SDRAM 640 */ 641#define CONFIG_SYS_MAMR_8COL ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ 642 MAMR_PTAE | \ 643 MAMR_AMA_TYPE_1 | \ 644 MAMR_DSA_1_CYCL | \ 645 MAMR_G0CLA_A10 | \ 646 MAMR_RLFA_1X | \ 647 MAMR_WLFA_1X | \ 648 MAMR_TLFA_4X \ 649 ) 650 651/* 652 * CS2* configuration for Disk On Chip: 653 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, 654 * no burst. 655 */ 656#define CONFIG_SYS_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ 657 OR_CSNT_SAM | \ 658 OR_ACS_DIV2 | \ 659 OR_BI | \ 660 OR_SCY_2_CLK | \ 661 OR_TRLX | \ 662 OR_EHTR \ 663 ) 664 665#define CONFIG_SYS_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ 666 BR_PS_8 | \ 667 BR_MS_GPCM | \ 668 BR_V \ 669 ) 670 671/* 672 * CS3* configuration for FPGA: 673 * 33 MHz bus with SCY=15, no burst. 674 * The FPGA uses TA and TEA to terminate bus cycles, but we 675 * clear SETA and set the cycle length to a large number so that 676 * the cycle will still complete even if there is a configuration 677 * error that prevents TA from asserting on FPGA accesss. 678 */ 679#define CONFIG_SYS_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ 680 OR_SCY_15_CLK | \ 681 OR_BI \ 682 ) 683 684#define CONFIG_SYS_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ 685 BR_PS_32 | \ 686 BR_MS_GPCM | \ 687 BR_V \ 688 ) 689/* 690 * CS4* configuration for FPGA SelectMap configuration interface. 691 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge 692 * of GCLK1_50 693 */ 694#define CONFIG_SYS_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ 695 OR_G5LS | \ 696 OR_BI \ 697 ) 698 699#define CONFIG_SYS_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ 700 BR_PS_8 | \ 701 BR_MS_UPMB | \ 702 BR_V \ 703 ) 704 705/* 706 * CS5* configuration for Mil-Std 1553 databus interface. 707 * 33 MHz bus, GPCM, no burst. 708 * The 1553 interface uses TA and TEA to terminate bus cycles, 709 * but we clear SETA and set the cycle length to a large number so that 710 * the cycle will still complete even if there is a configuration 711 * error that prevents TA from asserting on FPGA accesss. 712 */ 713#define CONFIG_SYS_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ 714 OR_SCY_15_CLK | \ 715 OR_EHTR | \ 716 OR_TRLX | \ 717 OR_CSNT_SAM | \ 718 OR_BI \ 719 ) 720 721#define CONFIG_SYS_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ 722 BR_PS_16 | \ 723 BR_MS_GPCM | \ 724 BR_V \ 725 ) 726 727/* 728 * Boot Flags 729 */ 730#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 731#define BOOTFLAG_WARM 0x02 /* Software reboot */ 732 733/* 734 * FEC interrupt assignment 735 */ 736#define FEC_INTERRUPT SIU_LEVEL1 737 738/* 739 * Sanity checks 740 */ 741#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) 742#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured 743#endif 744 745#endif /* __CONFIG_GEN860T_H */ 746