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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37
38#define CONFIG_BOOKE 1
39#define CONFIG_E500 1
40#define CONFIG_MPC85xx 1
41#define CONFIG_MPC8540 1
42#define CONFIG_MPC8540ADS 1
43
44#ifndef CONFIG_HAS_FEC
45#define CONFIG_HAS_FEC 1
46#endif
47
48#define CONFIG_PCI
49#define CONFIG_SYS_PCI_64BIT 1
50#define CONFIG_TSEC_ENET
51#define CONFIG_ENV_OVERWRITE
52#define CONFIG_FSL_LAW 1
53
54
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70
71
72#ifndef CONFIG_SYS_CLK_FREQ
73#define CONFIG_SYS_CLK_FREQ 33000000
74#endif
75
76
77
78
79
80#define CONFIG_L2_CACHE
81#define CONFIG_BTB
82
83#define CONFIG_SYS_MEMTEST_START 0x00200000
84#define CONFIG_SYS_MEMTEST_END 0x00400000
85
86
87
88
89
90
91#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
92#define CONFIG_SYS_CCSRBAR 0xe0000000
93#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
94#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
95
96
97#define CONFIG_FSL_DDR1
98#define CONFIG_SPD_EEPROM
99#define CONFIG_DDR_SPD
100#undef CONFIG_FSL_DDR_INTERACTIVE
101
102#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
103
104#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
106
107#define CONFIG_NUM_DDR_CONTROLLERS 1
108#define CONFIG_DIMM_SLOTS_PER_CTLR 1
109#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
110
111
112#define SPD_EEPROM_ADDRESS 0x51
113
114
115#define CONFIG_SYS_SDRAM_SIZE 128
116#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
117#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
118#define CONFIG_SYS_DDR_TIMING_1 0x37344321
119#define CONFIG_SYS_DDR_TIMING_2 0x00000800
120#define CONFIG_SYS_DDR_CONTROL 0xc2000000
121#define CONFIG_SYS_DDR_MODE 0x00000062
122#define CONFIG_SYS_DDR_INTERVAL 0x05200100
123
124
125
126
127#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
128#define CONFIG_SYS_LBC_SDRAM_SIZE 64
129
130#define CONFIG_SYS_FLASH_BASE 0xff000000
131#define CONFIG_SYS_BR0_PRELIM 0xff001801
132
133#define CONFIG_SYS_OR0_PRELIM 0xff006ff7
134#define CONFIG_SYS_MAX_FLASH_BANKS 1
135#define CONFIG_SYS_MAX_FLASH_SECT 64
136#undef CONFIG_SYS_FLASH_CHECKSUM
137#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
138#define CONFIG_SYS_FLASH_WRITE_TOUT 500
139
140#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
141
142#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
143#define CONFIG_SYS_RAMBOOT
144#else
145#undef CONFIG_SYS_RAMBOOT
146#endif
147
148#define CONFIG_FLASH_CFI_DRIVER
149#define CONFIG_SYS_FLASH_CFI
150#define CONFIG_SYS_FLASH_EMPTY_INFO
151
152#undef CONFIG_CLOCKS_IN_MHZ
153
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176
177#define CONFIG_SYS_BR2_PRELIM 0xf0001861
178
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191
192
193#define CONFIG_SYS_OR2_PRELIM 0xfc006901
194
195#define CONFIG_SYS_LBC_LCRR 0x00030004
196#define CONFIG_SYS_LBC_LBCR 0x00000000
197#define CONFIG_SYS_LBC_LSRT 0x20000000
198#define CONFIG_SYS_LBC_MRTPR 0x20000000
199
200#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
201 | LSDMR_RFCR5 \
202 | LSDMR_PRETOACT3 \
203 | LSDMR_ACTTORW3 \
204 | LSDMR_BL8 \
205 | LSDMR_WRC2 \
206 | LSDMR_CL3 \
207 | LSDMR_RFEN \
208 )
209
210
211
212
213#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
214#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
215#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
216#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
217#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
218
219
220
221
222
223#define CONFIG_SYS_BR4_PRELIM 0xf8000801
224#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
225#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
226
227#define CONFIG_SYS_INIT_RAM_LOCK 1
228#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
229#define CONFIG_SYS_INIT_RAM_END 0x4000
230
231#define CONFIG_SYS_GBL_DATA_SIZE 128
232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
233#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
234
235#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
236#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
237
238
239#define CONFIG_CONS_INDEX 1
240#undef CONFIG_SERIAL_SOFTWARE_FIFO
241#define CONFIG_SYS_NS16550
242#define CONFIG_SYS_NS16550_SERIAL
243#define CONFIG_SYS_NS16550_REG_SIZE 1
244#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
245
246#define CONFIG_SYS_BAUDRATE_TABLE \
247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
248
249#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
250#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
251
252
253#define CONFIG_SYS_HUSH_PARSER
254#ifdef CONFIG_SYS_HUSH_PARSER
255#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
256#endif
257
258
259#define CONFIG_OF_LIBFDT 1
260#define CONFIG_OF_BOARD_SETUP 1
261#define CONFIG_OF_STDOUT_VIA_ALIAS 1
262
263
264
265
266#define CONFIG_FSL_I2C
267#define CONFIG_HARD_I2C
268#undef CONFIG_SOFT_I2C
269#define CONFIG_SYS_I2C_SPEED 400000
270#define CONFIG_SYS_I2C_SLAVE 0x7F
271#define CONFIG_SYS_I2C_NOPROBES {0x69}
272#define CONFIG_SYS_I2C_OFFSET 0x3000
273
274
275#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000
276#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000
277#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
278#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
279
280
281
282
283
284#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
285#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
286#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
287#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
288#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
289#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
290#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
291#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
292
293#if defined(CONFIG_PCI)
294
295#define CONFIG_NET_MULTI
296#define CONFIG_PCI_PNP
297
298#undef CONFIG_EEPRO100
299#undef CONFIG_TULIP
300
301#if !defined(CONFIG_PCI_PNP)
302 #define PCI_ENET0_IOADDR 0xe0000000
303 #define PCI_ENET0_MEMADDR 0xe0000000
304 #define PCI_IDSEL_NUMBER 0x0c
305#endif
306
307#undef CONFIG_PCI_SCAN_SHOW
308#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
309
310#endif
311
312
313#if defined(CONFIG_TSEC_ENET)
314
315#ifndef CONFIG_NET_MULTI
316#define CONFIG_NET_MULTI 1
317#endif
318
319#define CONFIG_MII 1
320#define CONFIG_TSEC1 1
321#define CONFIG_TSEC1_NAME "TSEC0"
322#define CONFIG_TSEC2 1
323#define CONFIG_TSEC2_NAME "TSEC1"
324#define TSEC1_PHY_ADDR 0
325#define TSEC2_PHY_ADDR 1
326#define TSEC1_PHYIDX 0
327#define TSEC2_PHYIDX 0
328#define TSEC1_FLAGS TSEC_GIGABIT
329#define TSEC2_FLAGS TSEC_GIGABIT
330
331
332#if CONFIG_HAS_FEC
333#define CONFIG_MPC85XX_FEC 1
334#define CONFIG_MPC85XX_FEC_NAME "FEC"
335#define FEC_PHY_ADDR 3
336#define FEC_PHYIDX 0
337#define FEC_FLAGS 0
338#endif
339
340
341#define CONFIG_ETHPRIME "TSEC0"
342
343#endif
344
345
346
347
348
349#ifndef CONFIG_SYS_RAMBOOT
350 #define CONFIG_ENV_IS_IN_FLASH 1
351 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
352 #define CONFIG_ENV_SECT_SIZE 0x40000
353 #define CONFIG_ENV_SIZE 0x2000
354#else
355 #define CONFIG_SYS_NO_FLASH 1
356 #define CONFIG_ENV_IS_NOWHERE 1
357 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
358 #define CONFIG_ENV_SIZE 0x2000
359#endif
360
361#define CONFIG_LOADS_ECHO 1
362#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
363
364
365
366
367
368#define CONFIG_BOOTP_BOOTFILESIZE
369#define CONFIG_BOOTP_BOOTPATH
370#define CONFIG_BOOTP_GATEWAY
371#define CONFIG_BOOTP_HOSTNAME
372
373
374
375
376
377#include <config_cmd_default.h>
378
379#define CONFIG_CMD_PING
380#define CONFIG_CMD_I2C
381#define CONFIG_CMD_ELF
382#define CONFIG_CMD_IRQ
383#define CONFIG_CMD_SETEXPR
384
385#if defined(CONFIG_PCI)
386 #define CONFIG_CMD_PCI
387#endif
388
389#if defined(CONFIG_SYS_RAMBOOT)
390 #undef CONFIG_CMD_SAVEENV
391 #undef CONFIG_CMD_LOADS
392#endif
393
394
395#undef CONFIG_WATCHDOG
396
397
398
399
400#define CONFIG_SYS_LONGHELP
401#define CONFIG_CMDLINE_EDITING
402#define CONFIG_SYS_LOAD_ADDR 0x2000000
403#define CONFIG_SYS_PROMPT "=> "
404
405#if defined(CONFIG_CMD_KGDB)
406 #define CONFIG_SYS_CBSIZE 1024
407#else
408 #define CONFIG_SYS_CBSIZE 256
409#endif
410
411#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
412#define CONFIG_SYS_MAXARGS 16
413#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
414#define CONFIG_SYS_HZ 1000
415
416
417
418
419
420
421#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
422
423
424
425
426
427
428#define BOOTFLAG_COLD 0x01
429#define BOOTFLAG_WARM 0x02
430
431#if defined(CONFIG_CMD_KGDB)
432#define CONFIG_KGDB_BAUDRATE 230400
433#define CONFIG_KGDB_SER_INDEX 2
434#endif
435
436
437
438
439
440
441
442#if defined(CONFIG_TSEC_ENET)
443#define CONFIG_HAS_ETH0
444#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
445#define CONFIG_HAS_ETH1
446#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
447#define CONFIG_HAS_ETH2
448#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
449#endif
450
451#define CONFIG_IPADDR 192.168.1.253
452
453#define CONFIG_HOSTNAME unknown
454#define CONFIG_ROOTPATH /nfsroot
455#define CONFIG_BOOTFILE your.uImage
456
457#define CONFIG_SERVERIP 192.168.1.1
458#define CONFIG_GATEWAYIP 192.168.1.1
459#define CONFIG_NETMASK 255.255.255.0
460
461#define CONFIG_LOADADDR 200000
462
463#define CONFIG_BOOTDELAY 10
464#undef CONFIG_BOOTARGS
465
466#define CONFIG_BAUDRATE 115200
467
468#define CONFIG_EXTRA_ENV_SETTINGS \
469 "netdev=eth0\0" \
470 "consoledev=ttyS0\0" \
471 "ramdiskaddr=1000000\0" \
472 "ramdiskfile=your.ramdisk.u-boot\0" \
473 "fdtaddr=400000\0" \
474 "fdtfile=your.fdt.dtb\0"
475
476#define CONFIG_NFSBOOTCOMMAND \
477 "setenv bootargs root=/dev/nfs rw " \
478 "nfsroot=$serverip:$rootpath " \
479 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
480 "console=$consoledev,$baudrate $othbootargs;" \
481 "tftp $loadaddr $bootfile;" \
482 "tftp $fdtaddr $fdtfile;" \
483 "bootm $loadaddr - $fdtaddr"
484
485#define CONFIG_RAMBOOTCOMMAND \
486 "setenv bootargs root=/dev/ram rw " \
487 "console=$consoledev,$baudrate $othbootargs;" \
488 "tftp $ramdiskaddr $ramdiskfile;" \
489 "tftp $loadaddr $bootfile;" \
490 "tftp $fdtaddr $fdtfile;" \
491 "bootm $loadaddr $ramdiskaddr $fdtaddr"
492
493#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
494
495#endif
496