1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 37#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ 38 39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 40#define CONFIG_SYS_SMC_RXBUFLEN 128 41#define CONFIG_SYS_MAXIDLE 10 42#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 43 44#define CONFIG_BOOTCOUNT_LIMIT 45 46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 48#define CONFIG_BOARD_TYPES 1 /* support board types */ 49 50#define CONFIG_PREBOOT "echo;" \ 51 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 52 "echo" 53 54#undef CONFIG_BOOTARGS 55 56#define CONFIG_EXTRA_ENV_SETTINGS \ 57 "netdev=eth0\0" \ 58 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 59 "nfsroot=${serverip}:${rootpath}\0" \ 60 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 61 "addip=setenv bootargs ${bootargs} " \ 62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 63 ":${hostname}:${netdev}:off panic=1\0" \ 64 "flash_nfs=run nfsargs addip;" \ 65 "bootm ${kernel_addr}\0" \ 66 "flash_self=run ramargs addip;" \ 67 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 68 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 69 "rootpath=/opt/eldk/ppc_8xx\0" \ 70 "hostname=TQM860L\0" \ 71 "bootfile=TQM860L/uImage\0" \ 72 "fdt_addr=40040000\0" \ 73 "kernel_addr=40060000\0" \ 74 "ramdisk_addr=40200000\0" \ 75 "u-boot=TQM860L/u-image.bin\0" \ 76 "load=tftp 200000 ${u-boot}\0" \ 77 "update=prot off 40000000 +${filesize};" \ 78 "era 40000000 +${filesize};" \ 79 "cp.b 200000 40000000 ${filesize};" \ 80 "sete filesize;save\0" \ 81 "" 82#define CONFIG_BOOTCOMMAND "run flash_self" 83 84#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 85#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 86 87#undef CONFIG_WATCHDOG /* watchdog disabled */ 88 89#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 90 91#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 92 93/* 94 * BOOTP options 95 */ 96#define CONFIG_BOOTP_SUBNETMASK 97#define CONFIG_BOOTP_GATEWAY 98#define CONFIG_BOOTP_HOSTNAME 99#define CONFIG_BOOTP_BOOTPATH 100#define CONFIG_BOOTP_BOOTFILESIZE 101 102 103#define CONFIG_MAC_PARTITION 104#define CONFIG_DOS_PARTITION 105 106#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 107 108 109/* 110 * Command line configuration. 111 */ 112#include <config_cmd_default.h> 113 114#define CONFIG_CMD_ASKENV 115#define CONFIG_CMD_DATE 116#define CONFIG_CMD_DHCP 117#define CONFIG_CMD_ELF 118#define CONFIG_CMD_EXT2 119#define CONFIG_CMD_IDE 120#define CONFIG_CMD_JFFS2 121#define CONFIG_CMD_NFS 122#define CONFIG_CMD_SNTP 123 124 125#define CONFIG_NETCONSOLE 126 127/* 128 * Miscellaneous configurable options 129 */ 130#define CONFIG_SYS_LONGHELP /* undef to save memory */ 131#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 132 133#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 134#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 135#ifdef CONFIG_SYS_HUSH_PARSER 136#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 137#endif 138 139#if defined(CONFIG_CMD_KGDB) 140#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 141#else 142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 143#endif 144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 147 148#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 149#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 150 151#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 152 153#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 154 155#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 156 157/* 158 * Low Level Configuration Settings 159 * (address mappings, register initial values, etc.) 160 * You should know what you are doing if you make changes here. 161 */ 162/*----------------------------------------------------------------------- 163 * Internal Memory Mapped Register 164 */ 165#define CONFIG_SYS_IMMR 0xFFF00000 166 167/*----------------------------------------------------------------------- 168 * Definitions for initial stack pointer and data area (in DPRAM) 169 */ 170#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 171#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 172#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 176/*----------------------------------------------------------------------- 177 * Start addresses for the final memory configuration 178 * (Set up by the startup code) 179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 180 */ 181#define CONFIG_SYS_SDRAM_BASE 0x00000000 182#define CONFIG_SYS_FLASH_BASE 0x40000000 183#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 184#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 185#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 186 187/* 188 * For booting Linux, the board info and command line data 189 * have to be in the first 8 MB of memory, since this is 190 * the maximum mapped by the Linux kernel during initialization. 191 */ 192#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 193 194/*----------------------------------------------------------------------- 195 * FLASH organization 196 */ 197 198/* use CFI flash driver */ 199#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 200#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 201#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 202#define CONFIG_SYS_FLASH_EMPTY_INFO 203#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 204#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 205#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 206 207#define CONFIG_ENV_IS_IN_FLASH 1 208#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 209#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 210 211/* Address and size of Redundant Environment Sector */ 212#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 213#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 214 215#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 216 217#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 218 219/*----------------------------------------------------------------------- 220 * Dynamic MTD partition support 221 */ 222#define CONFIG_CMD_MTDPARTS 223#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 224#define CONFIG_FLASH_CFI_MTD 225#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 226 227#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 228 "128k(dtb)," \ 229 "1664k(kernel)," \ 230 "2m(rootfs)," \ 231 "4m(data)" 232 233/*----------------------------------------------------------------------- 234 * Hardware Information Block 235 */ 236#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 237#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 238#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 239 240/*----------------------------------------------------------------------- 241 * Cache Configuration 242 */ 243#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 244#if defined(CONFIG_CMD_KGDB) 245#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 246#endif 247 248/*----------------------------------------------------------------------- 249 * SYPCR - System Protection Control 11-9 250 * SYPCR can only be written once after reset! 251 *----------------------------------------------------------------------- 252 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 253 */ 254#if defined(CONFIG_WATCHDOG) 255#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 256 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 257#else 258#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 259#endif 260 261/*----------------------------------------------------------------------- 262 * SIUMCR - SIU Module Configuration 11-6 263 *----------------------------------------------------------------------- 264 * PCMCIA config., multi-function pin tri-state 265 */ 266#ifndef CONFIG_CAN_DRIVER 267#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 268#else /* we must activate GPL5 in the SIUMCR for CAN */ 269#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 270#endif /* CONFIG_CAN_DRIVER */ 271 272/*----------------------------------------------------------------------- 273 * TBSCR - Time Base Status and Control 11-26 274 *----------------------------------------------------------------------- 275 * Clear Reference Interrupt Status, Timebase freezing enabled 276 */ 277#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 278 279/*----------------------------------------------------------------------- 280 * RTCSC - Real-Time Clock Status and Control Register 11-27 281 *----------------------------------------------------------------------- 282 */ 283#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 284 285/*----------------------------------------------------------------------- 286 * PISCR - Periodic Interrupt Status and Control 11-31 287 *----------------------------------------------------------------------- 288 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 289 */ 290#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 291 292/*----------------------------------------------------------------------- 293 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 294 *----------------------------------------------------------------------- 295 * Reset PLL lock status sticky bit, timer expired status bit and timer 296 * interrupt status bit 297 */ 298#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 299 300/*----------------------------------------------------------------------- 301 * SCCR - System Clock and reset Control Register 15-27 302 *----------------------------------------------------------------------- 303 * Set clock output, timebase and RTC source and divider, 304 * power management and some other internal clocks 305 */ 306#define SCCR_MASK SCCR_EBDF11 307#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 308 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 309 SCCR_DFALCD00) 310 311/*----------------------------------------------------------------------- 312 * PCMCIA stuff 313 *----------------------------------------------------------------------- 314 * 315 */ 316#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 317#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 318#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 319#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 320#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 321#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 322#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 323#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 324 325/*----------------------------------------------------------------------- 326 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 327 *----------------------------------------------------------------------- 328 */ 329 330#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 331 332#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 333#undef CONFIG_IDE_LED /* LED for ide not supported */ 334#undef CONFIG_IDE_RESET /* reset for ide not supported */ 335 336#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 337#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 338 339#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 340 341#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 342 343/* Offset for data I/O */ 344#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 345 346/* Offset for normal register accesses */ 347#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 348 349/* Offset for alternate registers */ 350#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 351 352/*----------------------------------------------------------------------- 353 * 354 *----------------------------------------------------------------------- 355 * 356 */ 357#define CONFIG_SYS_DER 0 358 359/* 360 * Init Memory Controller: 361 * 362 * BR0/1 and OR0/1 (FLASH) 363 */ 364 365#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 366#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 367 368/* used to re-map FLASH both when starting from SRAM or FLASH: 369 * restrict access enough to keep SRAM working (if any) 370 * but not too much to meddle with FLASH accesses 371 */ 372#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 373#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 374 375/* 376 * FLASH timing: 377 */ 378#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 379 OR_SCY_3_CLK | OR_EHTR | OR_BI) 380 381#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 382#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 383#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 384 385#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 386#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 387#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 388 389/* 390 * BR2/3 and OR2/3 (SDRAM) 391 * 392 */ 393#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 394#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 395#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 396 397/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 398#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 399 400#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 401#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 402 403#ifndef CONFIG_CAN_DRIVER 404#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 405#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 406#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 407#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 408#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 409#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 410#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 411 BR_PS_8 | BR_MS_UPMB | BR_V ) 412#endif /* CONFIG_CAN_DRIVER */ 413 414/* 415 * Memory Periodic Timer Prescaler 416 * 417 * The Divider for PTA (refresh timer) configuration is based on an 418 * example SDRAM configuration (64 MBit, one bank). The adjustment to 419 * the number of chip selects (NCS) and the actually needed refresh 420 * rate is done by setting MPTPR. 421 * 422 * PTA is calculated from 423 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 424 * 425 * gclk CPU clock (not bus clock!) 426 * Trefresh Refresh cycle * 4 (four word bursts used) 427 * 428 * 4096 Rows from SDRAM example configuration 429 * 1000 factor s -> ms 430 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 431 * 4 Number of refresh cycles per period 432 * 64 Refresh cycle in ms per number of rows 433 * -------------------------------------------- 434 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 435 * 436 * 50 MHz => 50.000.000 / Divider = 98 437 * 66 Mhz => 66.000.000 / Divider = 129 438 * 80 Mhz => 80.000.000 / Divider = 156 439 */ 440 441#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 442#define CONFIG_SYS_MAMR_PTA 98 443 444/* 445 * For 16 MBit, refresh rates could be 31.3 us 446 * (= 64 ms / 2K = 125 / quad bursts). 447 * For a simpler initialization, 15.6 us is used instead. 448 * 449 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 450 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 451 */ 452#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 453#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 454 455/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 456#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 457#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 458 459/* 460 * MAMR settings for SDRAM 461 */ 462 463/* 8 column SDRAM */ 464#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 465 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 467/* 9 column SDRAM */ 468#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 469 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 471 472 473/* 474 * Internal Definitions 475 * 476 * Boot Flags 477 */ 478#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 479#define BOOTFLAG_WARM 0x02 /* Software reboot */ 480 481#define CONFIG_SCC1_ENET 482#define CONFIG_FEC_ENET 483#define CONFIG_ETHPRIME "SCC ETHERNET" 484 485/* pass open firmware flat tree */ 486#define CONFIG_OF_LIBFDT 1 487#define CONFIG_OF_BOARD_SETUP 1 488#define CONFIG_HWCONFIG 1 489 490#endif /* __CONFIG_H */ 491