LXR uboot/include/configs/a320evb.h

   1/*
   2 * (C) Copyright 2009 Faraday Technology
   3 * Po-Yu Chuang <ratbert@faraday-tech.com>
   4 *
   5 * Configuation settings for the Faraday A320 board.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22#ifndef __CONFIG_H
  23#define __CONFIG_H
  24
  25#include <asm/arch/a320.h>
  26
  27/*-----------------------------------------------------------------------
  28 * CPU and Board Configuration Options
  29 */
  30#undef CONFIG_USE_IRQ           /* we don't need IRQ/FIQ stuff */
  31
  32#undef CONFIG_SKIP_LOWLEVEL_INIT
  33
  34/*-----------------------------------------------------------------------
  35 * Timer
  36 */
  37#define CONFIG_SYS_HZ           1000    /* timer ticks per second */
  38
  39/*-----------------------------------------------------------------------
  40 * Real Time Clock
  41 */
  42#define CONFIG_RTC_FTRTC010
  43
  44/*-----------------------------------------------------------------------
  45 * Serial console configuration
  46 */
  47
  48/* FTUART is a high speed NS 16C550A compatible UART */
  49#define CONFIG_BAUDRATE                 38400
  50#define CONFIG_CONS_INDEX               1
  51#define CONFIG_SYS_NS16550
  52#define CONFIG_SYS_NS16550_SERIAL
  53#define CONFIG_SYS_NS16550_COM1         0x98200000
  54#define CONFIG_SYS_NS16550_REG_SIZE     -4
  55#define CONFIG_SYS_NS16550_CLK          18432000
  56
  57/* valid baudrates */
  58#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  59
  60/*-----------------------------------------------------------------------
  61 * Ethernet
  62 */
  63#define CONFIG_NET_MULTI
  64#define CONFIG_FTMAC100
  65
  66#define CONFIG_BOOTDELAY        3
  67
  68/*-----------------------------------------------------------------------
  69 * Command line configuration.
  70 */
  71#include <config_cmd_default.h>
  72
  73#define CONFIG_CMD_CACHE
  74#define CONFIG_CMD_DATE
  75#define CONFIG_CMD_PING
  76
  77/*-----------------------------------------------------------------------
  78 * Miscellaneous configurable options
  79 */
  80#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
  81#define CONFIG_SYS_PROMPT       "A320 # "       /* Monitor Command Prompt */
  82#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
  83
  84/* Print Buffer Size */
  85#define CONFIG_SYS_PBSIZE       \
  86        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  87
  88/* max number of command args */
  89#define CONFIG_SYS_MAXARGS      16
  90
  91/* Boot Argument Buffer Size */
  92#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  93
  94/*-----------------------------------------------------------------------
  95 * Stack sizes
  96 *
  97 * The stack sizes are set up in start.S using the settings below
  98 */
  99#define CONFIG_STACKSIZE        (128 * 1024)    /* regular stack */
 100#ifdef CONFIG_USE_IRQ
 101#define CONFIG_STACKSIZE_IRQ    (4 * 1024)      /* IRQ stack */
 102#define CONFIG_STACKSIZE_FIQ    (4 * 1024)      /* FIQ stack */
 103#endif
 104
 105/*-----------------------------------------------------------------------
 106 * Size of malloc() pool
 107 */
 108#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 109
 110/*-----------------------------------------------------------------------
 111 * size in bytes reserved for initial data
 112*/
 113#define CONFIG_SYS_GBL_DATA_SIZE        128
 114
 115/*-----------------------------------------------------------------------
 116 * SDRAM controller configuration
 117 */
 118#define CONFIG_SYS_FTSDMC020_TP0        (FTSDMC020_TP0_TRAS(2) |        \
 119                                         FTSDMC020_TP0_TRP(1)  |        \
 120                                         FTSDMC020_TP0_TRCD(1) |        \
 121                                         FTSDMC020_TP0_TRF(3)  |        \
 122                                         FTSDMC020_TP0_TWR(1)  |        \
 123                                         FTSDMC020_TP0_TCL(2))
 124
 125#define CONFIG_SYS_FTSDMC020_TP1        (FTSDMC020_TP1_INI_PREC(4) |    \
 126                                         FTSDMC020_TP1_INI_REFT(8) |    \
 127                                         FTSDMC020_TP1_REF_INTV(0x180))
 128
 129#define CONFIG_SYS_FTSDMC020_BANK0_BSR  (FTSDMC020_BANK_ENABLE   |      \
 130                                         FTSDMC020_BANK_DDW_X16  |      \
 131                                         FTSDMC020_BANK_DSZ_256M |      \
 132                                         FTSDMC020_BANK_MBW_32   |      \
 133                                         FTSDMC020_BANK_SIZE_64M)
 134
 135/*-----------------------------------------------------------------------
 136 * Physical Memory Map
 137 */
 138#define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 139#define PHYS_SDRAM_1            0x10000000      /* SDRAM Bank #1 */
 140#define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
 141
 142/*
 143 * Load address and memory test area should agree with
 144 * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
 145 */
 146#define CONFIG_SYS_LOAD_ADDR            0x12000000
 147
 148/* memtest works on 63 MB in DRAM */
 149#define CONFIG_SYS_MEMTEST_START        0x10000000
 150#define CONFIG_SYS_MEMTEST_END          0x13F00000
 151
 152/*-----------------------------------------------------------------------
 153 * Static memory controller configuration
 154 */
 155
 156#include <asm/arch/ftsmc020.h>
 157
 158#define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 159                                 FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 160                                 FTSMC020_BANK_SIZE_1M            |     \
 161                                 FTSMC020_BANK_MBW_8)
 162
 163#define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_RBE      |        \
 164                                 FTSMC020_TPR_AST(3)   |        \
 165                                 FTSMC020_TPR_CTW(3)   |        \
 166                                 FTSMC020_TPR_ATI(0xf) |        \
 167                                 FTSMC020_TPR_AT2(3)   |        \
 168                                 FTSMC020_TPR_WTC(3)   |        \
 169                                 FTSMC020_TPR_AHT(3)   |        \
 170                                 FTSMC020_TPR_TRNA(0xf))
 171
 172#define FTSMC020_BANK1_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 173                                 FTSMC020_BANK_BASE(PHYS_FLASH_2) |     \
 174                                 FTSMC020_BANK_SIZE_32M           |     \
 175                                 FTSMC020_BANK_MBW_32)
 176
 177#define FTSMC020_BANK1_TIMING   (FTSMC020_TPR_AST(3)   |        \
 178                                 FTSMC020_TPR_CTW(3)   |        \
 179                                 FTSMC020_TPR_ATI(0xf) |        \
 180                                 FTSMC020_TPR_AT2(3)   |        \
 181                                 FTSMC020_TPR_WTC(3)   |        \
 182                                 FTSMC020_TPR_AHT(3)   |        \
 183                                 FTSMC020_TPR_TRNA(0xf))
 184
 185#define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 186        { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 187        { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 188}
 189
 190/*-----------------------------------------------------------------------
 191 * FLASH and environment organization
 192 */
 193
 194/* use CFI framework */
 195#define CONFIG_SYS_FLASH_CFI
 196#define CONFIG_FLASH_CFI_DRIVER
 197
 198/* support JEDEC */
 199#define CONFIG_FLASH_CFI_LEGACY
 200#define CONFIG_SYS_FLASH_LEGACY_512Kx8
 201
 202#define PHYS_FLASH_1                    0x00000000
 203#define PHYS_FLASH_2                    0x00400000
 204#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 205#define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2, }
 206
 207#define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 208
 209/* max number of memory banks */
 210#define CONFIG_SYS_MAX_FLASH_BANKS      2
 211
 212/* max number of sectors on one chip */
 213#define CONFIG_SYS_MAX_FLASH_SECT       512
 214
 215#undef CONFIG_SYS_FLASH_EMPTY_INFO
 216
 217/* environments */
 218#define CONFIG_ENV_IS_IN_FLASH
 219#define CONFIG_ENV_ADDR                 0x00060000
 220#define CONFIG_ENV_SIZE                 0x20000
 221
 222#endif  /* __CONFIG_H */
 223