1/* 2 * U-boot - Configuration file for BF561 Acvilon System On Module 3 * For more information please go to http://www.niistt.ru/ 4 */ 5 6#ifndef __CONFIG_BF561_ACVILON_H__ 7#define __CONFIG_BF561_ACVILON_H__ 8 9#include <asm/config-pre.h> 10 11 12/* 13 * Processor Settings 14 */ 15#define CONFIG_BFIN_CPU bf561-0.5 16#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS 17 18 19/* 20 * Clock Settings 21 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 22 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 23 */ 24/* CONFIG_CLKIN_HZ is any value in Hz */ 25#define CONFIG_CLKIN_HZ 12000000 26/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 27/* 1 = CLKIN / 2 */ 28#define CONFIG_CLKIN_HALF 0 29/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 30/* 1 = bypass PLL */ 31#define CONFIG_PLL_BYPASS 0 32/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 33/* Values can range from 0-63 (where 0 means 64) */ 34#define CONFIG_VCO_MULT 50 35/* CCLK_DIV controls the core clock divider */ 36/* Values can be 1, 2, 4, or 8 ONLY */ 37#define CONFIG_CCLK_DIV 1 38/* SCLK_DIV controls the system clock divider */ 39/* Values can range from 1-15 */ 40#define CONFIG_SCLK_DIV 5 41 42 43/* 44 * Memory Settings 45 */ 46#define CONFIG_MEM_ADD_WDTH 10 47#define CONFIG_MEM_SIZE 128 48 49#define CONFIG_EBIU_SDRRC_VAL 0x300 50#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189 51 52#define CONFIG_EBIU_AMGCTL_VAL 0x4e 53#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 54#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554 55 56#define CONFIG_SYS_MONITOR_LEN (256 * 1024) 57#define CONFIG_SYS_MALLOC_LEN (128 * 1024) 58 59 60/* 61 * RTC Settings 62 */ 63#define CONFIG_RTC_DS1337 64#define CONFIG_SYS_I2C_RTC_ADDR 0x68 65 66/* I2C SYSMON (LM75, AD7414 is almost compatible) */ 67#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 68#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 69#define CONFIG_SYS_I2C_DTT_ADDR 0x49 70/*#define CONFIG_SYS_DTT_MAX_TEMP 70 71#define CONFIG_SYS_DTT_LOW_TEMP -30 72#define CONFIG_SYS_DTT_HYSTERESIS 3*/ 73 74 75/* 76 * Network Settings 77 */ 78#define ADI_CMDS_NETWORK 1 79#define CONFIG_NET_MULTI 80#define CONFIG_CMD_NET 81#define CONFIG_CMD_MII 82#define CONFIG_CMD_DATE 83#define CONFIG_CMD_DTT 84 85#if defined(CONFIG_CMD_NET) 86 87#define CONFIG_SMC911X 1 88#define CONFIG_SMC911X_32_BIT 89/* #define CONFIG_SMC911X_16_BIT */ 90#define CONFIG_SMC911X_BASE 0x28000000 91 92#endif /* (CONFIG_CMD_NET) */ 93 94#define CONFIG_HOSTNAME bf561-acvilon 95 96/* Uncomment next line to use fixed MAC address */ 97/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ 98 99 100/* 101 * Flash Settings 102 */ 103#define CONFIG_SYS_NO_FLASH 104 105 106/* 107 * I2C Settings 108 */ 109#define CONFIG_HARD_I2C 110/* Use 300kHz speed by default */ 111#define CONFIG_SYS_I2C_SPEED 0x00 112#define CONFIG_PCA9564_I2C 113#define CONFIG_PCA9564_BASE 0x2c000000 114 115 116/* 117 * SPI Settings 118 */ 119#define CONFIG_BFIN_SPI 120#define CONFIG_ENV_SPI_MAX_HZ 10000000 121#define CONFIG_SF_DEFAULT_SPEED 10000000 122#define CONFIG_SPI_FLASH 123#define CONFIG_SPI_FLASH_ATMEL 124 125 126/* 127 * Env Storage Settings 128 */ 129#define CONFIG_ENV_IS_IN_SPI_FLASH 130/* #define CONFIG_CMD_SAVEENV */ 131#define CONFIG_ENV_SECT_SIZE (1056 * 8) 132#define CONFIG_ENV_OFFSET ((16 + 256) * 1056) 133#define CONFIG_ENV_SIZE (8 * 1056) 134#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 135 136 137/* 138 * NAND Settings 139 * We're using NAND_PLAT driver to make things simplier 140 */ 141#define CONFIG_NAND_PLAT 142#define CONFIG_CMD_NAND 143#define CONFIG_SYS_NAND_BASE 0x24000000 144#define CONFIG_SYS_MAX_NAND_DEVICE 1 145 146#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) 147#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) 148#define BFIN_NAND_READY PF10 149#define BFIN_NAND_WRITE(addr, cmd) \ 150 do { \ 151 bfin_write8(addr, cmd); \ 152 SSYNC(); \ 153 } while (0) 154 155#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) 156#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) 157#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY) 158#define NAND_PLAT_INIT() \ 159 do { \ 160 bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \ 161 bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \ 162 } while (0) 163 164 165/* 166 * Misc Settings 167 */ 168#define CONFIG_UART_CONSOLE 0 169#define CONFIG_BAUDRATE 57600 170#define CONFIG_SYS_PROMPT "Acvilon> " 171 172 173/* 174 * Pull in common ADI header for remaining command/environment setup 175 */ 176#include <configs/bfin_adi_common.h> 177 178#endif /* __CONFIG_BF561_ACVILON_H__ */ 179