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29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32
33
34
35#ifdef CONFIG_MK_PCI
36#define CONFIG_PCI
37#define CONFIG_PCI1
38#endif
39
40#ifdef CONFIG_MK_66
41#define CONFIG_SYS_CLK_DIV 1
42#endif
43
44#ifdef CONFIG_MK_33
45#define CONFIG_SYS_CLK_DIV 2
46#endif
47
48#ifdef CONFIG_MK_PCIE
49#define CONFIG_PCIE1
50#endif
51
52
53
54
55#define CONFIG_BOOKE 1
56#define CONFIG_E500 1
57#define CONFIG_MPC85xx 1
58#define CONFIG_MPC8548 1
59#define CONFIG_SBC8548 1
60
61#undef CONFIG_RIO
62
63#ifdef CONFIG_PCI
64#define CONFIG_FSL_PCI_INIT
65#define CONFIG_SYS_PCI_64BIT 1
66#endif
67#ifdef CONFIG_PCIE1
68#define CONFIG_FSL_PCIE_RESET 1
69#endif
70
71#define CONFIG_TSEC_ENET
72#define CONFIG_ENV_OVERWRITE
73
74#define CONFIG_INTERRUPTS
75
76#define CONFIG_FSL_LAW 1
77
78
79
80
81#ifndef CONFIG_SYS_CLK_DIV
82#define CONFIG_SYS_CLK_DIV 1
83#endif
84#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
85
86
87
88
89#define CONFIG_L2_CACHE
90#define CONFIG_BTB
91
92
93
94
95#define CONFIG_ENABLE_36BIT_PHYS 1
96
97#define CONFIG_BOARD_EARLY_INIT_F 1
98
99#undef CONFIG_SYS_DRAM_TEST
100#define CONFIG_SYS_MEMTEST_START 0x00200000
101#define CONFIG_SYS_MEMTEST_END 0x00400000
102
103
104
105
106
107#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
108#define CONFIG_SYS_CCSRBAR 0xe0000000
109#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
110#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
111
112#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
113#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
114#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
115
116
117#define CONFIG_FSL_DDR2
118#undef CONFIG_FSL_DDR_INTERACTIVE
119#undef CONFIG_SPD_EEPROM
120#undef CONFIG_DDR_SPD
121#undef CONFIG_DDR_ECC
122
123#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
124#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
125
126#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
127#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
128#define CONFIG_VERY_BIG_RAM
129
130#define CONFIG_NUM_DDR_CONTROLLERS 1
131#define CONFIG_DIMM_SLOTS_PER_CTLR 1
132#define CONFIG_CHIP_SELECTS_PER_CTRL 2
133
134
135#define SPD_EEPROM_ADDRESS 0x51
136
137
138
139
140#ifndef CONFIG_SPD_EEPROM
141 #define CONFIG_SYS_SDRAM_SIZE 256
142#endif
143
144#undef CONFIG_CLOCKS_IN_MHZ
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194
195#define CONFIG_SYS_BOOT_BLOCK 0xff800000
196#define CONFIG_SYS_ALT_FLASH 0xfb800000
197#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
198
199#define CONFIG_SYS_BR0_PRELIM 0xff800801
200#define CONFIG_SYS_BR6_PRELIM 0xfb801801
201
202#define CONFIG_SYS_OR0_PRELIM 0xff806e65
203#define CONFIG_SYS_OR6_PRELIM 0xf8006e65
204
205#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
206 CONFIG_SYS_ALT_FLASH}
207#define CONFIG_SYS_MAX_FLASH_BANKS 2
208#define CONFIG_SYS_MAX_FLASH_SECT 256
209#undef CONFIG_SYS_FLASH_CHECKSUM
210#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
211#define CONFIG_SYS_FLASH_WRITE_TOUT 500
212
213#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
214
215#define CONFIG_FLASH_CFI_DRIVER
216#define CONFIG_SYS_FLASH_CFI
217#define CONFIG_SYS_FLASH_EMPTY_INFO
218
219
220
221#define CONFIG_SYS_BR5_PRELIM 0xf8000801
222#define CONFIG_SYS_OR5_PRELIM 0xff006e65
223#define CONFIG_SYS_EPLD_BASE 0xf8000000
224#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
225#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
226#define CONFIG_SYS_BD_REV 0xf8300000
227#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
228
229
230
231
232#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
233#define CONFIG_SYS_LBC_SDRAM_SIZE 128
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251#define CONFIG_SYS_BR3_PRELIM 0xf0001861
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266
267#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
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284
285#define CONFIG_SYS_BR4_PRELIM 0xf4001861
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300
301#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
302
303#define CONFIG_SYS_LBC_LCRR 0x00000002
304#define CONFIG_SYS_LBC_LBCR 0x00000000
305#define CONFIG_SYS_LBC_LSRT 0x20000000
306#define CONFIG_SYS_LBC_MRTPR 0x00000000
307
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313
314#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
315 | LSDMR_PRETOACT7 \
316 | LSDMR_ACTTORW7 \
317 | LSDMR_BL8 \
318 | LSDMR_WRC4 \
319 | LSDMR_CL3 \
320 | LSDMR_RFEN \
321 )
322
323#define CONFIG_SYS_INIT_RAM_LOCK 1
324#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
325#define CONFIG_SYS_INIT_RAM_END 0x4000
326
327#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
328
329#define CONFIG_SYS_GBL_DATA_SIZE 128
330#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
331#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
332
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339
340#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)
341#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
342
343
344#define CONFIG_CONS_INDEX 1
345#undef CONFIG_SERIAL_SOFTWARE_FIFO
346#define CONFIG_SYS_NS16550
347#define CONFIG_SYS_NS16550_SERIAL
348#define CONFIG_SYS_NS16550_REG_SIZE 1
349#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
350
351#define CONFIG_SYS_BAUDRATE_TABLE \
352 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
353
354#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
355#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
356
357
358#define CONFIG_SYS_HUSH_PARSER
359#ifdef CONFIG_SYS_HUSH_PARSER
360#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
361#endif
362
363
364#define CONFIG_OF_LIBFDT 1
365#define CONFIG_OF_BOARD_SETUP 1
366#define CONFIG_OF_STDOUT_VIA_ALIAS 1
367
368
369
370
371#define CONFIG_FSL_I2C
372#define CONFIG_HARD_I2C
373#undef CONFIG_SOFT_I2C
374#define CONFIG_SYS_I2C_SPEED 400000
375#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
376#define CONFIG_SYS_I2C_SLAVE 0x7F
377#define CONFIG_SYS_I2C_OFFSET 0x3000
378
379
380
381
382
383#define CONFIG_SYS_PCI_VIRT 0x80000000
384#define CONFIG_SYS_PCI_PHYS 0x80000000
385
386#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
387#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
388#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
389#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
390#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
391#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
392#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
393#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000
394
395#ifdef CONFIG_PCIE1
396#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
397#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
398#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
399#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
400#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
401#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
402#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
403#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
404#endif
405
406#ifdef CONFIG_RIO
407
408
409
410#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
411#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
412#endif
413
414#if defined(CONFIG_PCI)
415
416#define CONFIG_NET_MULTI
417#define CONFIG_PCI_PNP
418
419#undef CONFIG_EEPRO100
420#undef CONFIG_TULIP
421
422#define CONFIG_PCI_SCAN_SHOW
423
424#endif
425
426
427#if defined(CONFIG_TSEC_ENET)
428
429#ifndef CONFIG_NET_MULTI
430#define CONFIG_NET_MULTI 1
431#endif
432
433#define CONFIG_MII 1
434#define CONFIG_TSEC1 1
435#define CONFIG_TSEC1_NAME "eTSEC0"
436#define CONFIG_TSEC2 1
437#define CONFIG_TSEC2_NAME "eTSEC1"
438#undef CONFIG_MPC85XX_FEC
439
440#define TSEC1_PHY_ADDR 0x19
441#define TSEC2_PHY_ADDR 0x1a
442
443#define TSEC1_PHYIDX 0
444#define TSEC2_PHYIDX 0
445
446#define TSEC1_FLAGS TSEC_GIGABIT
447#define TSEC2_FLAGS TSEC_GIGABIT
448
449
450#define CONFIG_ETHPRIME "eTSEC0"
451#define CONFIG_PHY_GIGE 1
452#endif
453
454
455
456
457#define CONFIG_ENV_IS_IN_FLASH 1
458#define CONFIG_ENV_SIZE 0x2000
459#if TEXT_BASE == 0xfff00000
460#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
461#define CONFIG_ENV_SECT_SIZE 0x80000
462#elif TEXT_BASE == 0xfffa0000
463#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
464#define CONFIG_ENV_SECT_SIZE 0x20000
465#else
466#warning undefined environment size/location.
467#endif
468
469#define CONFIG_LOADS_ECHO 1
470#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
471
472
473
474
475#define CONFIG_BOOTP_BOOTFILESIZE
476#define CONFIG_BOOTP_BOOTPATH
477#define CONFIG_BOOTP_GATEWAY
478#define CONFIG_BOOTP_HOSTNAME
479
480
481
482
483
484#include <config_cmd_default.h>
485
486#define CONFIG_CMD_PING
487#define CONFIG_CMD_I2C
488#define CONFIG_CMD_MII
489#define CONFIG_CMD_ELF
490
491#if defined(CONFIG_PCI)
492 #define CONFIG_CMD_PCI
493#endif
494
495
496#undef CONFIG_WATCHDOG
497
498
499
500
501#define CONFIG_CMDLINE_EDITING
502#define CONFIG_SYS_LONGHELP
503#define CONFIG_SYS_LOAD_ADDR 0x2000000
504#define CONFIG_SYS_PROMPT "=> "
505#if defined(CONFIG_CMD_KGDB)
506#define CONFIG_SYS_CBSIZE 1024
507#else
508#define CONFIG_SYS_CBSIZE 256
509#endif
510#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
511#define CONFIG_SYS_MAXARGS 16
512#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
513#define CONFIG_SYS_HZ 1000
514
515
516
517
518
519
520#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
521
522
523
524
525
526
527#define BOOTFLAG_COLD 0x01
528#define BOOTFLAG_WARM 0x02
529
530#if defined(CONFIG_CMD_KGDB)
531#define CONFIG_KGDB_BAUDRATE 230400
532#define CONFIG_KGDB_SER_INDEX 2
533#endif
534
535
536
537
538
539
540#if defined(CONFIG_TSEC_ENET)
541#define CONFIG_HAS_ETH0
542#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
543#define CONFIG_HAS_ETH1
544#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
545#endif
546
547#define CONFIG_IPADDR 192.168.0.55
548
549#define CONFIG_HOSTNAME sbc8548
550#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
551#define CONFIG_BOOTFILE /uImage
552#define CONFIG_UBOOTPATH /u-boot.bin
553
554#define CONFIG_SERVERIP 192.168.0.2
555#define CONFIG_GATEWAYIP 192.168.0.1
556#define CONFIG_NETMASK 255.255.255.0
557
558#define CONFIG_LOADADDR 1000000
559
560#define CONFIG_BOOTDELAY 10
561#undef CONFIG_BOOTARGS
562
563#define CONFIG_BAUDRATE 115200
564
565#define CONFIG_EXTRA_ENV_SETTINGS \
566 "netdev=eth0\0" \
567 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
568 "tftpflash=tftpboot $loadaddr $uboot; " \
569 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
570 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
571 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
572 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
573 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
574 "consoledev=ttyS0\0" \
575 "ramdiskaddr=2000000\0" \
576 "ramdiskfile=uRamdisk\0" \
577 "fdtaddr=c00000\0" \
578 "fdtfile=sbc8548.dtb\0"
579
580#define CONFIG_NFSBOOTCOMMAND \
581 "setenv bootargs root=/dev/nfs rw " \
582 "nfsroot=$serverip:$rootpath " \
583 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
584 "console=$consoledev,$baudrate $othbootargs;" \
585 "tftp $loadaddr $bootfile;" \
586 "tftp $fdtaddr $fdtfile;" \
587 "bootm $loadaddr - $fdtaddr"
588
589
590#define CONFIG_RAMBOOTCOMMAND \
591 "setenv bootargs root=/dev/ram rw " \
592 "console=$consoledev,$baudrate $othbootargs;" \
593 "tftp $ramdiskaddr $ramdiskfile;" \
594 "tftp $loadaddr $bootfile;" \
595 "tftp $fdtaddr $fdtfile;" \
596 "bootm $loadaddr $ramdiskaddr $fdtaddr"
597
598#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
599
600#endif
601