1/* 2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] 3 * 4 * Copyright (C) 2005 Ivan Kokshaysky 5 * Copyright (C) SAN People 6 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 7 * 8 * Power Management Controller (PMC) - System peripherals registers. 9 * Based on AT91RM9200 datasheet revision E. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17#ifndef AT91_PMC_H 18#define AT91_PMC_H 19 20#define AT91_ASM_PMC_MOR (AT91_PMC_BASE + 0x20) 21#define AT91_ASM_PMC_PLLAR (AT91_PMC_BASE + 0x28) 22#define AT91_ASM_PMC_PLLBR (AT91_PMC_BASE + 0x2c) 23#define AT91_ASM_PMC_MCKR (AT91_PMC_BASE + 0x30) 24#define AT91_ASM_PMC_SR (AT91_PMC_BASE + 0x68) 25 26#ifndef __ASSEMBLY__ 27 28#include <asm/types.h> 29 30typedef struct at91_pmc { 31 u32 scer; /* 0x00 System Clock Enable Register */ 32 u32 scdr; /* 0x04 System Clock Disable Register */ 33 u32 scsr; /* 0x08 System Clock Status Register */ 34 u32 reserved0; 35 u32 pcer; /* 0x10 Peripheral Clock Enable Register */ 36 u32 pcdr; /* 0x14 Peripheral Clock Disable Register */ 37 u32 pcsr; /* 0x18 Peripheral Clock Status Register */ 38 u32 reserved1; 39 u32 mor; /* 0x20 Main Oscilator Register */ 40 u32 mcfr; /* 0x24 Main Clock Frequency Register */ 41 u32 pllar; /* 0x28 PLL A Register */ 42 u32 pllbr; /* 0x2C PLL B Register */ 43 u32 mckr; /* 0x30 Master Clock Register */ 44 u32 reserved2[3]; 45 u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */ 46 u32 reserved3[4]; 47 u32 ier; /* 0x60 Interrupt Enable Register */ 48 u32 idr; /* 0x64 Interrupt Disable Register */ 49 u32 sr; /* 0x68 Status Register */ 50 u32 imr; /* 0x6C Interrupt Mask Register */ 51 u32 reserved4[4]; 52 u32 pllicpr; /* 0x80 Change Pump Current Register (SAM9) */ 53 u32 reserved5[21]; 54 u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */ 55 u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */ 56 u32 reserved8[5]; 57} at91_pmc_t; 58 59#endif /* end not assembly */ 60 61#define AT91_PMC_MOR_MOSCEN 0x01 62#define AT91_PMC_MOR_OSCBYPASS 0x02 63#define AT91_PMC_MOR_OSCOUNT(x) ((x & 0xff) << 8) 64 65#define AT91_PMC_PLLXR_DIV(x) (x & 0xFF) 66#define AT91_PMC_PLLXR_PLLCOUNT(x) ((x & 0x3F) << 8) 67#define AT91_PMC_PLLXR_OUT(x) ((x & 0x03) << 14) 68#define AT91_PMC_PLLXR_MUL(x) ((x & 0x7FF) << 16) 69#define AT91_PMC_PLLAR_29 0x20000000 70#define AT91_PMC_PLLBR_USBDIV_1 0x00000000 71#define AT91_PMC_PLLBR_USBDIV_2 0x10000000 72#define AT91_PMC_PLLBR_USBDIV_4 0x20000000 73 74#define AT91_PMC_MCFR_MAINRDY 0x00010000 75#define AT91_PMC_MCFR_MAINF_MASK 0x0000FFFF 76 77#define AT91_PMC_MCKR_CSS_SLOW 0x00000000 78#define AT91_PMC_MCKR_CSS_MAIN 0x00000001 79#define AT91_PMC_MCKR_CSS_PLLA 0x00000002 80#define AT91_PMC_MCKR_CSS_PLLB 0x00000003 81#define AT91_PMC_MCKR_CSS_MASK 0x00000003 82 83#define AT91_PMC_MCKR_PRES_1 0x00000000 84#define AT91_PMC_MCKR_PRES_2 0x00000004 85#define AT91_PMC_MCKR_PRES_4 0x00000008 86#define AT91_PMC_MCKR_PRES_8 0x0000000C 87#define AT91_PMC_MCKR_PRES_16 0x00000010 88#define AT91_PMC_MCKR_PRES_32 0x00000014 89#define AT91_PMC_MCKR_PRES_64 0x00000018 90#define AT91_PMC_MCKR_PRES_MASK 0x0000001C 91 92#define AT91_PMC_MCKR_MDIV_1 0x00000000 93#define AT91_PMC_MCKR_MDIV_2 0x00000100 94#define AT91_PMC_MCKR_MDIV_4 0x00000200 95#define AT91_PMC_MCKR_MDIV_MASK 0x00000300 96 97#define AT91_PMC_MCKR_PLLADIV_1 0x00001000 98#define AT91_PMC_MCKR_PLLADIV_2 0x00002000 99 100#define AT91_PMC_IXR_MOSCS 0x00000001 101#define AT91_PMC_IXR_LOCKA 0x00000002 102#define AT91_PMC_IXR_LOCKB 0x00000004 103#define AT91_PMC_IXR_MCKRDY 0x00000008 104#define AT91_PMC_IXR_LOCKU 0x00000040 105#define AT91_PMC_IXR_PCKRDY0 0x00000100 106#define AT91_PMC_IXR_PCKRDY1 0x00000200 107#define AT91_PMC_IXR_PCKRDY2 0x00000400 108#define AT91_PMC_IXR_PCKRDY3 0x00000800 109 110#ifdef CONFIG_AT91_LEGACY 111#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ 112#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ 113 114#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ 115#endif 116 117#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 118#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 119#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 120#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ 121#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 122#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 123#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ 124#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 125#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 126#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 127#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ 128#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ 129#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 130#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 131 132#ifdef CONFIG_AT91_LEGACY 133#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ 134#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ 135#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 136 137#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ 138#endif 139 140#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 141#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 142#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 143#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ 144 145#ifdef CONFIG_AT91_LEGACY 146#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 147#endif 148#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 149#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ 150#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 151#ifdef CONFIG_AT91_LEGACY 152#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ 153#endif 154#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ 155#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ 156#ifdef CONFIG_AT91_LEGACY 157#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ 158#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ 159#endif 160#define AT91_PMC_DIV (0xff << 0) /* Divider */ 161#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 162#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 163#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ 164#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ 165#define AT91_PMC_USBDIV_1 (0 << 28) 166#define AT91_PMC_USBDIV_2 (1 << 28) 167#define AT91_PMC_USBDIV_4 (2 << 28) 168#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 169#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ 170 171#ifdef CONFIG_AT91_LEGACY 172#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ 173#endif 174#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ 175#define AT91_PMC_CSS_SLOW (0 << 0) 176#define AT91_PMC_CSS_MAIN (1 << 0) 177#define AT91_PMC_CSS_PLLA (2 << 0) 178#define AT91_PMC_CSS_PLLB (3 << 0) 179#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ 180#define AT91_PMC_PRES_1 (0 << 2) 181#define AT91_PMC_PRES_2 (1 << 2) 182#define AT91_PMC_PRES_4 (2 << 2) 183#define AT91_PMC_PRES_8 (3 << 2) 184#define AT91_PMC_PRES_16 (4 << 2) 185#define AT91_PMC_PRES_32 (5 << 2) 186#define AT91_PMC_PRES_64 (6 << 2) 187#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ 188#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ 189#define AT91RM9200_PMC_MDIV_2 (1 << 8) 190#define AT91RM9200_PMC_MDIV_3 (2 << 8) 191#define AT91RM9200_PMC_MDIV_4 (3 << 8) 192#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ 193#define AT91SAM9_PMC_MDIV_2 (1 << 8) 194#define AT91SAM9_PMC_MDIV_4 (2 << 8) 195#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ 196#define AT91SAM9_PMC_MDIV_6 (3 << 8) 197#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ 198#define AT91_PMC_PDIV_1 (0 << 12) 199#define AT91_PMC_PDIV_2 (1 << 12) 200 201#ifdef CONFIG_AT91_LEGACY 202#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ 203 204#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ 205#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ 206#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ 207#endif 208#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ 209#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 210#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 211#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 212#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ 213#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ 214#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 215#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 216#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 217#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ 218#ifdef CONFIG_AT91_LEGACY 219#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ 220 221#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ 222#endif 223#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ 224#ifdef CONFIG_AT91_LEGACY 225#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ 226#endif /* CONFIG_AT91_LEGACY */ 227#endif 228