1/* 2 * (C) Copyright 2004 3 * Texas Instruments, <www.ti.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23#ifndef _OMAP24XX_I2C_H_ 24#define _OMAP24XX_I2C_H_ 25 26#define I2C_BASE1 0x48070000 27#define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ 28 29#define I2C_DEFAULT_BASE I2C_BASE1 30 31struct i2c { 32 unsigned short rev; /* 0x00 */ 33 unsigned short res1; 34 unsigned short ie; /* 0x04 */ 35 unsigned short res2; 36 unsigned short stat; /* 0x08 */ 37 unsigned short res3; 38 unsigned short iv; /* 0x0C */ 39 unsigned short res4[3]; 40 unsigned short buf; /* 0x14 */ 41 unsigned short res5; 42 unsigned short cnt; /* 0x18 */ 43 unsigned short res6; 44 unsigned short data; /* 0x1C */ 45 unsigned short res7; 46 unsigned short sysc; /* 0x20 */ 47 unsigned short res8; 48 unsigned short con; /* 0x24 */ 49 unsigned short res9; 50 unsigned short oa; /* 0x28 */ 51 unsigned short res10; 52 unsigned short sa; /* 0x2C */ 53 unsigned short res11; 54 unsigned short psc; /* 0x30 */ 55 unsigned short res12; 56 unsigned short scll; /* 0x34 */ 57 unsigned short res13; 58 unsigned short sclh; /* 0x38 */ 59 unsigned short res14; 60 unsigned short systest; /* 0x3c */ 61 unsigned short res15; 62}; 63 64#define I2C_BUS_MAX 2 65 66/* I2C masks */ 67 68/* I2C Interrupt Enable Register (I2C_IE): */ 69#define I2C_IE_GC_IE (1 << 5) 70#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ 71#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ 72#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ 73#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ 74#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ 75 76/* I2C Status Register (I2C_STAT): */ 77 78#define I2C_STAT_SBD (1 << 15) /* Single byte data */ 79#define I2C_STAT_BB (1 << 12) /* Bus busy */ 80#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 81#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 82#define I2C_STAT_AAS (1 << 9) /* Address as slave */ 83#define I2C_STAT_GC (1 << 5) 84#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 85#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 86#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ 87#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ 88#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ 89 90 91/* I2C Interrupt Code Register (I2C_INTCODE): */ 92 93#define I2C_INTCODE_MASK 7 94#define I2C_INTCODE_NONE 0 95#define I2C_INTCODE_AL 1 /* Arbitration lost */ 96#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ 97#define I2C_INTCODE_ARDY 3 /* Register access ready */ 98#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ 99#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ 100 101/* I2C Buffer Configuration Register (I2C_BUF): */ 102 103#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ 104#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ 105 106/* I2C Configuration Register (I2C_CON): */ 107 108#define I2C_CON_EN (1 << 15) /* I2C module enable */ 109#define I2C_CON_BE (1 << 14) /* Big endian mode */ 110#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ 111#define I2C_CON_MST (1 << 10) /* Master/slave mode */ 112#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ 113#define I2C_CON_XA (1 << 8) /* Expand address */ 114#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ 115#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ 116 117/* I2C System Test Register (I2C_SYSTEST): */ 118 119#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 120#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ 121#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 122#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 123#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ 124#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ 125#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ 126#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ 127 128/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ 129#define OMAP_I2C_STANDARD 100000 130#define OMAP_I2C_FAST_MODE 400000 131#define OMAP_I2C_HIGH_SPEED 3400000 132 133#define SYSTEM_CLOCK_12 12000000 134#define SYSTEM_CLOCK_13 13000000 135#define SYSTEM_CLOCK_192 19200000 136#define SYSTEM_CLOCK_96 96000000 137 138#ifndef I2C_IP_CLK 139#define I2C_IP_CLK SYSTEM_CLOCK_96 140#endif 141 142#ifndef I2C_INTERNAL_SAMPLING_CLK 143#define I2C_INTERNAL_SAMPLING_CLK 19200000 144#endif 145 146/* These are the trim values for standard and fast speed */ 147#ifndef I2C_FASTSPEED_SCLL_TRIM 148#define I2C_FASTSPEED_SCLL_TRIM 6 149#endif 150#ifndef I2C_FASTSPEED_SCLH_TRIM 151#define I2C_FASTSPEED_SCLH_TRIM 6 152#endif 153 154/* These are the trim values for high speed */ 155#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM 156#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 157#endif 158#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM 159#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 160#endif 161#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM 162#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM 163#endif 164#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM 165#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM 166#endif 167 168#define I2C_PSC_MAX 0x0f 169#define I2C_PSC_MIN 0x00 170 171 172#endif 173