LXR uboot/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended

   1/* DO NOT EDIT THIS FILE
   2 * Automatically generated by generate-cdef-headers.xsl
   3 * DO NOT EDIT THIS FILE
   4 */
   5
   6#ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__
   7#define __BFIN_CDEF_ADSP_EDN_BF534_extended__
   8
   9#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
  10#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
  11#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
  12#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
  13#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
  14#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
  15#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
  16#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
  17#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
  18#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
  19#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
  20#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
  21#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
  22#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
  23#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
  24#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
  25#define bfin_read_SWRST()              bfin_read16(SWRST)
  26#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
  27#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration Register */
  28#define bfin_read_SYSCR()              bfin_read16(SYSCR)
  29#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
  30#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
  31#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
  32#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
  33#define pSIC_IMASK                     ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
  34#define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
  35#define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
  36#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
  37#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
  38#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
  39#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
  40#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
  41#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
  42#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
  43#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
  44#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
  45#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
  46#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
  47#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
  48#define pSIC_ISR                       ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
  49#define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
  50#define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
  51#define pSIC_IWR                       ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
  52#define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
  53#define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
  54#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
  55#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
  56#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
  57#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
  58#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
  59#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
  60#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
  61#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
  62#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
  63#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
  64#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
  65#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
  66#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
  67#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
  68#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
  69#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
  70#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
  71#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
  72#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
  73#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
  74#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
  75#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
  76#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
  77#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
  78#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
  79#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
  80#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
  81#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
  82#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
  83#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
  84#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
  85#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
  86#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
  87#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
  88#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
  89#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
  90#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
  91#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
  92#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
  93#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
  94#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
  95#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
  96#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
  97#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
  98#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
  99#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 100#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 101#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
 102#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 103#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 104#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
 105#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 106#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 107#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
 108#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 109#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 110#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
 111#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
 112#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 113#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
 114#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 115#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 116#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
 117#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
 118#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
 119#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
 120#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
 121#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
 122#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
 123#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
 124#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
 125#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
 126#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
 127#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
 128#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
 129#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
 130#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
 131#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
 132#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
 133#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
 134#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
 135#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
 136#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
 137#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
 138#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 139#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 140#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
 141#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 142#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 143#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
 144#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 145#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 146#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
 147#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 148#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 149#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
 150#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 151#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 152#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
 153#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 154#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 155#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
 156#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 157#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 158#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
 159#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 160#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 161#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
 162#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 163#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 164#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
 165#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 166#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 167#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
 168#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 169#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 170#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
 171#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 172#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 173#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
 174#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 175#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 176#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
 177#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 178#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 179#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
 180#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 181#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 182#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
 183#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 184#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 185#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
 186#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 187#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 188#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
 189#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 190#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 191#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
 192#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 193#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 194#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
 195#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 196#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 197#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
 198#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 199#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 200#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
 201#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 202#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 203#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
 204#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 205#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 206#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
 207#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 208#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 209#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
 210#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 211#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 212#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
 213#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 214#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 215#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
 216#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 217#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 218#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
 219#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
 220#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 221#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
 222#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 223#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 224#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
 225#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 226#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 227#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
 228#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 229#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 230#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
 231#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 232#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 233#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
 234#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
 235#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
 236#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
 237#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
 238#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
 239#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
 240#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
 241#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
 242#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
 243#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
 244#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
 245#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
 246#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
 247#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
 248#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
 249#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
 250#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
 251#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
 252#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
 253#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
 254#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
 255#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
 256#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
 257#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
 258#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
 259#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
 260#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
 261#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
 262#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
 263#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
 264#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
 265#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
 266#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
 267#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
 268#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
 269#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
 270#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
 271#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
 272#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
 273#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
 274#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
 275#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
 276#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
 277#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
 278#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
 279#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
 280#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
 281#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
 282#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
 283#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
 284#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
 285#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
 286#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
 287#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
 288#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
 289#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
 290#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
 291#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */
 292#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
 293#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
 294#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 295#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 296#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
 297#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 298#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 299#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
 300#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
 301#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 302#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
 303#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
 304#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 305#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
 306#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
 307#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
 308#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
 309#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 310#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
 311#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
 312#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 313#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
 314#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
 315#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 316#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
 317#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
 318#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 319#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
 320#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
 321#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 322#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
 323#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 324#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 325#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
 326#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 327#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 328#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
 329#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
 330#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 331#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
 332#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
 333#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 334#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
 335#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
 336#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 337#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
 338#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
 339#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 340#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
 341#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
 342#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 343#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
 344#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
 345#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 346#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
 347#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
 348#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 349#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
 350#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
 351#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 352#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
 353#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
 354#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 355#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
 356#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
 357#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 358#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
 359#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 360#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 361#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
 362#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 363#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 364#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
 365#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
 366#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 367#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
 368#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
 369#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 370#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
 371#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
 372#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
 373#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
 374#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 375#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
 376#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
 377#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 378#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
 379#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
 380#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 381#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
 382#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
 383#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 384#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
 385#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
 386#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 387#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
 388#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 389#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 390#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
 391#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 392#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 393#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
 394#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
 395#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 396#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
 397#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
 398#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 399#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
 400#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
 401#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 402#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
 403#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
 404#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 405#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
 406#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
 407#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 408#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
 409#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
 410#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 411#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
 412#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
 413#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 414#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
 415#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
 416#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 417#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
 418#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
 419#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 420#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
 421#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
 422#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 423#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
 424#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 425#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 426#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
 427#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
 428#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 429#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
 430#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
 431#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 432#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
 433#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
 434#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
 435#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
 436#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
 437#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
 438#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
 439#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
 440#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
 441#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
 442#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
 443#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 444#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
 445#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 446#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 447#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
 448#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 449#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 450#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
 451#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 452#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 453#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
 454#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 455#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 456#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
 457#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 458#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 459#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
 460#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 461#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 462#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
 463#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 464#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 465#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
 466#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 467#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 468#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
 469#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 470#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 471#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
 472#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 473#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 474#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
 475#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 476#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 477#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
 478#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 479#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 480#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
 481#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 482#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 483#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
 484#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 485#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 486#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
 487#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 488#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 489#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
 490#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 491#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 492#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
 493#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 494#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 495#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
 496#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 497#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 498#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
 499#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 500#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 501#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
 502#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 503#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 504#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
 505#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 506#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 507#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
 508#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 509#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 510#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
 511#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 512#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 513#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
 514#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 515#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 516#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
 517#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 518#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 519#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
 520#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 521#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 522#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
 523#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 524#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 525#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
 526#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 527#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 528#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
 529#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 530#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 531#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
 532#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 533#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 534#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
 535#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 536#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 537#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
 538#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 539#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 540#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
 541#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 542#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 543#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
 544#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 545#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 546#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
 547#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 548#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 549#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
 550#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 551#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 552#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
 553#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 554#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 555#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
 556#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 557#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 558#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
 559#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 560#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 561#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
 562#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 563#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 564#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
 565#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 566#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 567#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
 568#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 569#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 570#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
 571#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 572#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 573#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
 574#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 575#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 576#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
 577#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 578#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 579#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
 580#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 581#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 582#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
 583#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 584#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 585#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
 586#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 587#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 588#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
 589#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 590#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 591#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
 592#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 593#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 594#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
 595#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 596#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 597#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
 598#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 599#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 600#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
 601#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 602#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 603#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
 604#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 605#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 606#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
 607#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 608#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 609#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
 610#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 611#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 612#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
 613#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 614#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 615#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
 616#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 617#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 618#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
 619#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 620#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 621#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
 622#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 623#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 624#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
 625#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 626#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 627#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
 628#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 629#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 630#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
 631#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 632#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 633#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
 634#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 635#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 636#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
 637#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 638#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 639#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
 640#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 641#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 642#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
 643#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 644#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 645#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
 646#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 647#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 648#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
 649#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 650#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 651#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
 652#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 653#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 654#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
 655#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 656#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 657#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
 658#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 659#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 660#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
 661#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 662#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 663#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
 664#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 665#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 666#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
 667#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 668#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 669#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
 670#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 671#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 672#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
 673#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 674#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 675#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
 676#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 677#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 678#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
 679#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 680#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
 681#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
 682#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 683#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 684#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
 685#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 686#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 687#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
 688#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 689#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 690#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
 691#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 692#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 693#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
 694#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 695#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 696#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
 697#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 698#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 699#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
 700#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 701#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 702#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
 703#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 704#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 705#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
 706#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 707#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 708#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
 709#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 710#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 711#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
 712#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 713#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 714#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
 715#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 716#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 717#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
 718#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 719#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 720#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
 721#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 722#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 723#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
 724#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 725#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 726#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
 727#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 728#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 729#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
 730#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 731#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 732#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
 733#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 734#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 735#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
 736#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 737#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 738#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
 739#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 740#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 741#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
 742#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 743#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 744#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
 745#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 746#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 747#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
 748#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 749#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 750#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
 751#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 752#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 753#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
 754#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 755#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 756#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
 757#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 758#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 759#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
 760#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 761#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 762#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
 763#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 764#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 765#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
 766#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 767#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 768#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
 769#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 770#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 771#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
 772#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 773#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 774#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
 775#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 776#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 777#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
 778#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 779#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 780#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
 781#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 782#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 783#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
 784#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 785#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 786#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
 787#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 788#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 789#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
 790#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 791#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 792#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
 793#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 794#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 795#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
 796#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 797#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 798#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
 799#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 800#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 801#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
 802#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 803#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 804#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
 805#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 806#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 807#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
 808#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 809#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 810#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
 811#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 812#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 813#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
 814#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 815#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 816#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
 817#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 818#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 819#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
 820#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 821#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 822#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
 823#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 824#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 825#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
 826#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 827#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 828#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
 829#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 830#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 831#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
 832#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 833#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 834#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
 835#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 836#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 837#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
 838#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 839#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 840#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
 841#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 842#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 843#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
 844#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 845#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 846#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
 847#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 848#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 849#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
 850#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 851#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 852#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
 853#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 854#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 855#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
 856#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 857#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 858#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
 859#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 860#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 861#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
 862#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 863#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 864#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
 865#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 866#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 867#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
 868#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 869#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 870#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
 871#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 872#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 873#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
 874#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 875#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 876#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
 877#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 878#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 879#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
 880#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 881#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 882#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
 883#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 884#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 885#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
 886#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 887#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 888#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
 889#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 890#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 891#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
 892#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 893#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 894#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
 895#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 896#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 897#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
 898#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 899#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 900#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
 901#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 902#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 903#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
 904#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 905#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 906#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
 907#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 908#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 909#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
 910#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 911#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 912#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
 913#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
 914#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 915#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
 916#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
 917#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 918#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
 919#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
 920#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 921#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
 922#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
 923#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 924#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
 925#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
 926#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 927#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
 928#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
 929#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 930#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
 931#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
 932#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 933#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
 934#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
 935#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 936#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
 937#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
 938#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 939#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
 940#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
 941#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 942#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
 943#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
 944#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 945#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
 946#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
 947#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 948#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
 949#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
 950#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 951#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
 952#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
 953#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 954#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
 955#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
 956#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 957#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
 958#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
 959#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 960#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
 961#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
 962#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 963#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
 964#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
 965#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 966#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
 967#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
 968#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 969#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
 970#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
 971#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 972#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
 973#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
 974#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 975#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
 976#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
 977#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 978#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
 979#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
 980#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 981#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
 982#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
 983#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 984#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
 985#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
 986#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 987#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
 988#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
 989#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 990#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
 991#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
 992#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 993#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
 994#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
 995#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 996#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
 997#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
 998#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 999#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
1000#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */

1001#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
1002#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
1003#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
1004#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
1005#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
1006#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
1007#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
1008#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
1009#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
1010#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
1011#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
1012#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
1013#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
1014#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
1015#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
1016#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
1017#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
1018#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
1019#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
1020#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
1021#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
1022#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
1023#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
1024#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
1025#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
1026#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
1027#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
1028#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
1029#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
1030#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
1031#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
1032#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
1033#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
1034#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
1035#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
1036#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
1037#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
1038#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
1039#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
1040#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
1041#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
1042#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
1043#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
1044#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
1045#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
1046#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
1047#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
1048#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
1049#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
1050#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
1051#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
1052#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
1053#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
1054#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
1055#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
1056#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
1057#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
1058#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
1059#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
1060#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
1061#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
1062#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
1063#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
1064#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
1065#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
1066#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
1067#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
1068#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
1069#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
1070#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
1071#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
1072#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
1073#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
1074#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
1075#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
1076#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
1077#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
1078#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
1079#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
1080#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
1081#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
1082#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
1083#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
1084#define pTWI_CLKDIV                    ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
1085#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
1086#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
1087#define pTWI_CONTROL                   ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
1088#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
1089#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
1090#define pTWI_SLAVE_CTL                 ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
1091#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
1092#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
1093#define pTWI_SLAVE_STAT                ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
1094#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
1095#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
1096#define pTWI_SLAVE_ADDR                ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
1097#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
1098#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
1099#define pTWI_MASTER_CTL                ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
1100#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
1101#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
1102#define pTWI_MASTER_STAT               ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
1103#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
1104#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
1105#define pTWI_MASTER_ADDR               ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
1106#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
1107#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
1108#define pTWI_INT_STAT                  ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
1109#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
1110#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
1111#define pTWI_INT_MASK                  ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
1112#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
1113#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
1114#define pTWI_FIFO_CTL                  ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
1115#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
1116#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
1117#define pTWI_FIFO_STAT                 ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
1118#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
1119#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
1120#define pTWI_XMT_DATA8                 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
1121#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
1122#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
1123#define pTWI_XMT_DATA16                ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
1124#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
1125#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
1126#define pTWI_RCV_DATA8                 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
1127#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
1128#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
1129#define pTWI_RCV_DATA16                ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
1130#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
1131#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
1132#define pPORTGIO                       ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
1133#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
1134#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
1135#define pPORTGIO_CLEAR                 ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
1136#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
1137#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
1138#define pPORTGIO_SET                   ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
1139#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
1140#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
1141#define pPORTGIO_TOGGLE                ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
1142#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
1143#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
1144#define pPORTGIO_MASKA                 ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
1145#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
1146#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
1147#define pPORTGIO_MASKA_CLEAR           ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
1148#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
1149#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
1150#define pPORTGIO_MASKA_SET             ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
1151#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
1152#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
1153#define pPORTGIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
1154#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
1155#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
1156#define pPORTGIO_MASKB                 ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
1157#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
1158#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
1159#define pPORTGIO_MASKB_CLEAR           ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
1160#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
1161#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
1162#define pPORTGIO_MASKB_SET             ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
1163#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
1164#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
1165#define pPORTGIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
1166#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
1167#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
1168#define pPORTGIO_DIR                   ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
1169#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
1170#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
1171#define pPORTGIO_POLAR                 ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
1172#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
1173#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
1174#define pPORTGIO_EDGE                  ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
1175#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
1176#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
1177#define pPORTGIO_BOTH                  ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
1178#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
1179#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
1180#define pPORTGIO_INEN                  ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
1181#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
1182#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
1183#define pPORTHIO                       ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
1184#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
1185#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
1186#define pPORTHIO_CLEAR                 ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
1187#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
1188#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
1189#define pPORTHIO_SET                   ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
1190#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
1191#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
1192#define pPORTHIO_TOGGLE                ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
1193#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
1194#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
1195#define pPORTHIO_MASKA                 ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
1196#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
1197#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
1198#define pPORTHIO_MASKA_CLEAR           ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
1199#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
1200#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
1201#define pPORTHIO_MASKA_SET             ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
1202#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
1203#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
1204#define pPORTHIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
1205#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
1206#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
1207#define pPORTHIO_MASKB                 ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
1208#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
1209#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
1210#define pPORTHIO_MASKB_CLEAR           ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
1211#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
1212#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
1213#define pPORTHIO_MASKB_SET             ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
1214#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
1215#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
1216#define pPORTHIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
1217#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
1218#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
1219#define pPORTHIO_DIR                   ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
1220#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
1221#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
1222#define pPORTHIO_POLAR                 ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
1223#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
1224#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
1225#define pPORTHIO_EDGE                  ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
1226#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
1227#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
1228#define pPORTHIO_BOTH                  ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
1229#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
1230#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
1231#define pPORTHIO_INEN                  ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
1232#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
1233#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
1234#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
1235#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
1236#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
1237#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
1238#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
1239#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
1240#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
1241#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
1242#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
1243#define pUART1_IER                     ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
1244#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
1245#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
1246#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
1247#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
1248#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
1249#define pUART1_IIR                     ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
1250#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
1251#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
1252#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
1253#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
1254#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
1255#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
1256#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
1257#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
1258#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
1259#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
1260#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
1261#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
1262#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
1263#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
1264#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
1265#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
1266#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
1267#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
1268#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
1269#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
1270#define pCAN_MC1                       ((uint16_t volatile *)CAN_MC1) /* Mailbox config reg 1 */
1271#define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
1272#define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
1273#define pCAN_MD1                       ((uint16_t volatile *)CAN_MD1) /* Mailbox direction reg 1 */
1274#define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)
1275#define bfin_write_CAN_MD1(val)        bfin_write16(CAN_MD1, val)
1276#define pCAN_TRS1                      ((uint16_t volatile *)CAN_TRS1) /* Transmit Request Set reg 1 */
1277#define bfin_read_CAN_TRS1()           bfin_read16(CAN_TRS1)
1278#define bfin_write_CAN_TRS1(val)       bfin_write16(CAN_TRS1, val)
1279#define pCAN_TRR1                      ((uint16_t volatile *)CAN_TRR1) /* Transmit Request Reset reg 1 */
1280#define bfin_read_CAN_TRR1()           bfin_read16(CAN_TRR1)
1281#define bfin_write_CAN_TRR1(val)       bfin_write16(CAN_TRR1, val)
1282#define pCAN_TA1                       ((uint16_t volatile *)CAN_TA1) /* Transmit Acknowledge reg 1 */
1283#define bfin_read_CAN_TA1()            bfin_read16(CAN_TA1)
1284#define bfin_write_CAN_TA1(val)        bfin_write16(CAN_TA1, val)
1285#define pCAN_AA1                       ((uint16_t volatile *)CAN_AA1) /* Transmit Abort Acknowledge reg 1 */
1286#define bfin_read_CAN_AA1()            bfin_read16(CAN_AA1)
1287#define bfin_write_CAN_AA1(val)        bfin_write16(CAN_AA1, val)
1288#define pCAN_RMP1                      ((uint16_t volatile *)CAN_RMP1) /* Receive Message Pending reg 1 */
1289#define bfin_read_CAN_RMP1()           bfin_read16(CAN_RMP1)
1290#define bfin_write_CAN_RMP1(val)       bfin_write16(CAN_RMP1, val)
1291#define pCAN_RML1                      ((uint16_t volatile *)CAN_RML1) /* Receive Message Lost reg 1 */
1292#define bfin_read_CAN_RML1()           bfin_read16(CAN_RML1)
1293#define bfin_write_CAN_RML1(val)       bfin_write16(CAN_RML1, val)
1294#define pCAN_MBTIF1                    ((uint16_t volatile *)CAN_MBTIF1) /* Mailbox Transmit Interrupt Flag reg 1 */
1295#define bfin_read_CAN_MBTIF1()         bfin_read16(CAN_MBTIF1)
1296#define bfin_write_CAN_MBTIF1(val)     bfin_write16(CAN_MBTIF1, val)
1297#define pCAN_MBRIF1                    ((uint16_t volatile *)CAN_MBRIF1) /* Mailbox Receive  Interrupt Flag reg 1 */
1298#define bfin_read_CAN_MBRIF1()         bfin_read16(CAN_MBRIF1)
1299#define bfin_write_CAN_MBRIF1(val)     bfin_write16(CAN_MBRIF1, val)
1300#define pCAN_MBIM1                     ((uint16_t volatile *)CAN_MBIM1) /* Mailbox Interrupt Mask reg 1 */
1301#define bfin_read_CAN_MBIM1()          bfin_read16(CAN_MBIM1)
1302#define bfin_write_CAN_MBIM1(val)      bfin_write16(CAN_MBIM1, val)
1303#define pCAN_RFH1                      ((uint16_t volatile *)CAN_RFH1) /* Remote Frame Handling reg 1 */
1304#define bfin_read_CAN_RFH1()           bfin_read16(CAN_RFH1)
1305#define bfin_write_CAN_RFH1(val)       bfin_write16(CAN_RFH1, val)
1306#define pCAN_OPSS1                     ((uint16_t volatile *)CAN_OPSS1) /* Overwrite Protection Single Shot Xmission reg 1 */
1307#define bfin_read_CAN_OPSS1()          bfin_read16(CAN_OPSS1)
1308#define bfin_write_CAN_OPSS1(val)      bfin_write16(CAN_OPSS1, val)
1309#define pCAN_MC2                       ((uint16_t volatile *)CAN_MC2) /* Mailbox config reg 2 */
1310#define bfin_read_CAN_MC2()            bfin_read16(CAN_MC2)
1311#define bfin_write_CAN_MC2(val)        bfin_write16(CAN_MC2, val)
1312#define pCAN_MD2                       ((uint16_t volatile *)CAN_MD2) /* Mailbox direction reg 2 */
1313#define bfin_read_CAN_MD2()            bfin_read16(CAN_MD2)
1314#define bfin_write_CAN_MD2(val)        bfin_write16(CAN_MD2, val)
1315#define pCAN_TRS2                      ((uint16_t volatile *)CAN_TRS2) /* Transmit Request Set reg 2 */
1316#define bfin_read_CAN_TRS2()           bfin_read16(CAN_TRS2)
1317#define bfin_write_CAN_TRS2(val)       bfin_write16(CAN_TRS2, val)
1318#define pCAN_TRR2                      ((uint16_t volatile *)CAN_TRR2) /* Transmit Request Reset reg 2 */
1319#define bfin_read_CAN_TRR2()           bfin_read16(CAN_TRR2)
1320#define bfin_write_CAN_TRR2(val)       bfin_write16(CAN_TRR2, val)
1321#define pCAN_TA2                       ((uint16_t volatile *)CAN_TA2) /* Transmit Acknowledge reg 2 */
1322#define bfin_read_CAN_TA2()            bfin_read16(CAN_TA2)
1323#define bfin_write_CAN_TA2(val)        bfin_write16(CAN_TA2, val)
1324#define pCAN_AA2                       ((uint16_t volatile *)CAN_AA2) /* Transmit Abort Acknowledge reg 2 */
1325#define bfin_read_CAN_AA2()            bfin_read16(CAN_AA2)
1326#define bfin_write_CAN_AA2(val)        bfin_write16(CAN_AA2, val)
1327#define pCAN_RMP2                      ((uint16_t volatile *)CAN_RMP2) /* Receive Message Pending reg 2 */
1328#define bfin_read_CAN_RMP2()           bfin_read16(CAN_RMP2)
1329#define bfin_write_CAN_RMP2(val)       bfin_write16(CAN_RMP2, val)
1330#define pCAN_RML2                      ((uint16_t volatile *)CAN_RML2) /* Receive Message Lost reg 2 */
1331#define bfin_read_CAN_RML2()           bfin_read16(CAN_RML2)
1332#define bfin_write_CAN_RML2(val)       bfin_write16(CAN_RML2, val)
1333#define pCAN_MBTIF2                    ((uint16_t volatile *)CAN_MBTIF2) /* Mailbox Transmit Interrupt Flag reg 2 */
1334#define bfin_read_CAN_MBTIF2()         bfin_read16(CAN_MBTIF2)
1335#define bfin_write_CAN_MBTIF2(val)     bfin_write16(CAN_MBTIF2, val)
1336#define pCAN_MBRIF2                    ((uint16_t volatile *)CAN_MBRIF2) /* Mailbox Receive  Interrupt Flag reg 2 */
1337#define bfin_read_CAN_MBRIF2()         bfin_read16(CAN_MBRIF2)
1338#define bfin_write_CAN_MBRIF2(val)     bfin_write16(CAN_MBRIF2, val)
1339#define pCAN_MBIM2                     ((uint16_t volatile *)CAN_MBIM2) /* Mailbox Interrupt Mask reg 2 */
1340#define bfin_read_CAN_MBIM2()          bfin_read16(CAN_MBIM2)
1341#define bfin_write_CAN_MBIM2(val)      bfin_write16(CAN_MBIM2, val)
1342#define pCAN_RFH2                      ((uint16_t volatile *)CAN_RFH2) /* Remote Frame Handling reg 2 */
1343#define bfin_read_CAN_RFH2()           bfin_read16(CAN_RFH2)
1344#define bfin_write_CAN_RFH2(val)       bfin_write16(CAN_RFH2, val)
1345#define pCAN_OPSS2                     ((uint16_t volatile *)CAN_OPSS2) /* Overwrite Protection Single Shot Xmission reg 2 */
1346#define bfin_read_CAN_OPSS2()          bfin_read16(CAN_OPSS2)
1347#define bfin_write_CAN_OPSS2(val)      bfin_write16(CAN_OPSS2, val)
1348#define pCAN_CLOCK                     ((uint16_t volatile *)CAN_CLOCK) /* Bit Timing Configuration register 0 */
1349#define bfin_read_CAN_CLOCK()          bfin_read16(CAN_CLOCK)
1350#define bfin_write_CAN_CLOCK(val)      bfin_write16(CAN_CLOCK, val)
1351#define pCAN_TIMING                    ((uint16_t volatile *)CAN_TIMING) /* Bit Timing Configuration register 1 */
1352#define bfin_read_CAN_TIMING()         bfin_read16(CAN_TIMING)
1353#define bfin_write_CAN_TIMING(val)     bfin_write16(CAN_TIMING, val)
1354#define pCAN_DEBUG                     ((uint16_t volatile *)CAN_DEBUG) /* Config register */
1355#define bfin_read_CAN_DEBUG()          bfin_read16(CAN_DEBUG)
1356#define bfin_write_CAN_DEBUG(val)      bfin_write16(CAN_DEBUG, val)
1357#define pCAN_STATUS                    ((uint16_t volatile *)CAN_STATUS) /* Global Status Register */
1358#define bfin_read_CAN_STATUS()         bfin_read16(CAN_STATUS)
1359#define bfin_write_CAN_STATUS(val)     bfin_write16(CAN_STATUS, val)
1360#define pCAN_CEC                       ((uint16_t volatile *)CAN_CEC) /* Error Counter Register */
1361#define bfin_read_CAN_CEC()            bfin_read16(CAN_CEC)
1362#define bfin_write_CAN_CEC(val)        bfin_write16(CAN_CEC, val)
1363#define pCAN_GIS                       ((uint16_t volatile *)CAN_GIS) /* Global Interrupt Status Register */
1364#define bfin_read_CAN_GIS()            bfin_read16(CAN_GIS)
1365#define bfin_write_CAN_GIS(val)        bfin_write16(CAN_GIS, val)
1366#define pCAN_GIM                       ((uint16_t volatile *)CAN_GIM) /* Global Interrupt Mask Register */
1367#define bfin_read_CAN_GIM()            bfin_read16(CAN_GIM)
1368#define bfin_write_CAN_GIM(val)        bfin_write16(CAN_GIM, val)
1369#define pCAN_GIF                       ((uint16_t volatile *)CAN_GIF) /* Global Interrupt Flag Register */
1370#define bfin_read_CAN_GIF()            bfin_read16(CAN_GIF)
1371#define bfin_write_CAN_GIF(val)        bfin_write16(CAN_GIF, val)
1372#define pCAN_CONTROL                   ((uint16_t volatile *)CAN_CONTROL) /* Master Control Register */
1373#define bfin_read_CAN_CONTROL()        bfin_read16(CAN_CONTROL)
1374#define bfin_write_CAN_CONTROL(val)    bfin_write16(CAN_CONTROL, val)
1375#define pCAN_INTR                      ((uint16_t volatile *)CAN_INTR) /* Interrupt Pending Register */
1376#define bfin_read_CAN_INTR()           bfin_read16(CAN_INTR)
1377#define bfin_write_CAN_INTR(val)       bfin_write16(CAN_INTR, val)
1378#define pCAN_VERSION                   ((uint16_t volatile *)CAN_VERSION) /* Version Code Register */
1379#define bfin_read_CAN_VERSION()        bfin_read16(CAN_VERSION)
1380#define bfin_write_CAN_VERSION(val)    bfin_write16(CAN_VERSION, val)
1381#define pCAN_MBTD                      ((uint16_t volatile *)CAN_MBTD) /* Mailbox Temporary Disable Feature */
1382#define bfin_read_CAN_MBTD()           bfin_read16(CAN_MBTD)
1383#define bfin_write_CAN_MBTD(val)       bfin_write16(CAN_MBTD, val)
1384#define pCAN_EWR                       ((uint16_t volatile *)CAN_EWR) /* Programmable Warning Level */
1385#define bfin_read_CAN_EWR()            bfin_read16(CAN_EWR)
1386#define bfin_write_CAN_EWR(val)        bfin_write16(CAN_EWR, val)
1387#define pCAN_ESR                       ((uint16_t volatile *)CAN_ESR) /* Error Status Register */
1388#define bfin_read_CAN_ESR()            bfin_read16(CAN_ESR)
1389#define bfin_write_CAN_ESR(val)        bfin_write16(CAN_ESR, val)
1390#define pCAN_UCREG                     ((uint16_t volatile *)CAN_UCREG) /* Universal Counter Register/Capture Register */
1391#define bfin_read_CAN_UCREG()          bfin_read16(CAN_UCREG)
1392#define bfin_write_CAN_UCREG(val)      bfin_write16(CAN_UCREG, val)
1393#define pCAN_UCCNT                     ((uint16_t volatile *)CAN_UCCNT) /* Universal Counter */
1394#define bfin_read_CAN_UCCNT()          bfin_read16(CAN_UCCNT)
1395#define bfin_write_CAN_UCCNT(val)      bfin_write16(CAN_UCCNT, val)
1396#define pCAN_UCRC                      ((uint16_t volatile *)CAN_UCRC) /* Universal Counter Force Reload Register */
1397#define bfin_read_CAN_UCRC()           bfin_read16(CAN_UCRC)
1398#define bfin_write_CAN_UCRC(val)       bfin_write16(CAN_UCRC, val)
1399#define pCAN_UCCNF                     ((uint16_t volatile *)CAN_UCCNF) /* Universal Counter Configuration Register */
1400#define bfin_read_CAN_UCCNF()          bfin_read16(CAN_UCCNF)
1401#define bfin_write_CAN_UCCNF(val)      bfin_write16(CAN_UCCNF, val)
1402#define pCAN_VERSION2                  ((uint16_t volatile *)CAN_VERSION2) /* Version Code Register 2 */
1403#define bfin_read_CAN_VERSION2()       bfin_read16(CAN_VERSION2)
1404#define bfin_write_CAN_VERSION2(val)   bfin_write16(CAN_VERSION2, val)
1405#define pCAN_AM00L                     ((uint16_t volatile *)CAN_AM00L) /* Mailbox 0 Low Acceptance Mask */
1406#define bfin_read_CAN_AM00L()          bfin_read16(CAN_AM00L)
1407#define bfin_write_CAN_AM00L(val)      bfin_write16(CAN_AM00L, val)
1408#define pCAN_AM00H                     ((uint16_t volatile *)CAN_AM00H) /* Mailbox 0 High Acceptance Mask */
1409#define bfin_read_CAN_AM00H()          bfin_read16(CAN_AM00H)
1410#define bfin_write_CAN_AM00H(val)      bfin_write16(CAN_AM00H, val)
1411#define pCAN_AM01L                     ((uint16_t volatile *)CAN_AM01L) /* Mailbox 1 Low Acceptance Mask  */
1412#define bfin_read_CAN_AM01L()          bfin_read16(CAN_AM01L)
1413#define bfin_write_CAN_AM01L(val)      bfin_write16(CAN_AM01L, val)
1414#define pCAN_AM01H                     ((uint16_t volatile *)CAN_AM01H) /* Mailbox 1 High Acceptance Mask */
1415#define bfin_read_CAN_AM01H()          bfin_read16(CAN_AM01H)
1416#define bfin_write_CAN_AM01H(val)      bfin_write16(CAN_AM01H, val)
1417#define pCAN_AM02L                     ((uint16_t volatile *)CAN_AM02L) /* Mailbox 2 Low Acceptance Mask  */
1418#define bfin_read_CAN_AM02L()          bfin_read16(CAN_AM02L)
1419#define bfin_write_CAN_AM02L(val)      bfin_write16(CAN_AM02L, val)
1420#define pCAN_AM02H                     ((uint16_t volatile *)CAN_AM02H) /* Mailbox 2 High Acceptance Mask */
1421#define bfin_read_CAN_AM02H()          bfin_read16(CAN_AM02H)
1422#define bfin_write_CAN_AM02H(val)      bfin_write16(CAN_AM02H, val)
1423#define pCAN_AM03L                     ((uint16_t volatile *)CAN_AM03L) /* Mailbox 3 Low Acceptance Mask  */
1424#define bfin_read_CAN_AM03L()          bfin_read16(CAN_AM03L)
1425#define bfin_write_CAN_AM03L(val)      bfin_write16(CAN_AM03L, val)
1426#define pCAN_AM03H                     ((uint16_t volatile *)CAN_AM03H) /* Mailbox 3 High Acceptance Mask */
1427#define bfin_read_CAN_AM03H()          bfin_read16(CAN_AM03H)
1428#define bfin_write_CAN_AM03H(val)      bfin_write16(CAN_AM03H, val)
1429#define pCAN_AM04L                     ((uint16_t volatile *)CAN_AM04L) /* Mailbox 4 Low Acceptance Mask  */
1430#define bfin_read_CAN_AM04L()          bfin_read16(CAN_AM04L)
1431#define bfin_write_CAN_AM04L(val)      bfin_write16(CAN_AM04L, val)
1432#define pCAN_AM04H                     ((uint16_t volatile *)CAN_AM04H) /* Mailbox 4 High Acceptance Mask */
1433#define bfin_read_CAN_AM04H()          bfin_read16(CAN_AM04H)
1434#define bfin_write_CAN_AM04H(val)      bfin_write16(CAN_AM04H, val)
1435#define pCAN_AM05L                     ((uint16_t volatile *)CAN_AM05L) /* Mailbox 5 Low Acceptance Mask  */
1436#define bfin_read_CAN_AM05L()          bfin_read16(CAN_AM05L)
1437#define bfin_write_CAN_AM05L(val)      bfin_write16(CAN_AM05L, val)
1438#define pCAN_AM05H                     ((uint16_t volatile *)CAN_AM05H) /* Mailbox 5 High Acceptance Mask */
1439#define bfin_read_CAN_AM05H()          bfin_read16(CAN_AM05H)
1440#define bfin_write_CAN_AM05H(val)      bfin_write16(CAN_AM05H, val)
1441#define pCAN_AM06L                     ((uint16_t volatile *)CAN_AM06L) /* Mailbox 6 Low Acceptance Mask  */
1442#define bfin_read_CAN_AM06L()          bfin_read16(CAN_AM06L)
1443#define bfin_write_CAN_AM06L(val)      bfin_write16(CAN_AM06L, val)
1444#define pCAN_AM06H                     ((uint16_t volatile *)CAN_AM06H) /* Mailbox 6 High Acceptance Mask */
1445#define bfin_read_CAN_AM06H()          bfin_read16(CAN_AM06H)
1446#define bfin_write_CAN_AM06H(val)      bfin_write16(CAN_AM06H, val)
1447#define pCAN_AM07L                     ((uint16_t volatile *)CAN_AM07L) /* Mailbox 7 Low Acceptance Mask  */
1448#define bfin_read_CAN_AM07L()          bfin_read16(CAN_AM07L)
1449#define bfin_write_CAN_AM07L(val)      bfin_write16(CAN_AM07L, val)
1450#define pCAN_AM07H                     ((uint16_t volatile *)CAN_AM07H) /* Mailbox 7 High Acceptance Mask */
1451#define bfin_read_CAN_AM07H()          bfin_read16(CAN_AM07H)
1452#define bfin_write_CAN_AM07H(val)      bfin_write16(CAN_AM07H, val)
1453#define pCAN_AM08L                     ((uint16_t volatile *)CAN_AM08L) /* Mailbox 8 Low Acceptance Mask  */
1454#define bfin_read_CAN_AM08L()          bfin_read16(CAN_AM08L)
1455#define bfin_write_CAN_AM08L(val)      bfin_write16(CAN_AM08L, val)
1456#define pCAN_AM08H                     ((uint16_t volatile *)CAN_AM08H) /* Mailbox 8 High Acceptance Mask */
1457#define bfin_read_CAN_AM08H()          bfin_read16(CAN_AM08H)
1458#define bfin_write_CAN_AM08H(val)      bfin_write16(CAN_AM08H, val)
1459#define pCAN_AM09L                     ((uint16_t volatile *)CAN_AM09L) /* Mailbox 9 Low Acceptance Mask  */
1460#define bfin_read_CAN_AM09L()          bfin_read16(CAN_AM09L)
1461#define bfin_write_CAN_AM09L(val)      bfin_write16(CAN_AM09L, val)
1462#define pCAN_AM09H                     ((uint16_t volatile *)CAN_AM09H) /* Mailbox 9 High Acceptance Mask */
1463#define bfin_read_CAN_AM09H()          bfin_read16(CAN_AM09H)
1464#define bfin_write_CAN_AM09H(val)      bfin_write16(CAN_AM09H, val)
1465#define pCAN_AM10L                     ((uint16_t volatile *)CAN_AM10L) /* Mailbox 10 Low Acceptance Mask  */
1466#define bfin_read_CAN_AM10L()          bfin_read16(CAN_AM10L)
1467#define bfin_write_CAN_AM10L(val)      bfin_write16(CAN_AM10L, val)
1468#define pCAN_AM10H                     ((uint16_t volatile *)CAN_AM10H) /* Mailbox 10 High Acceptance Mask */
1469#define bfin_read_CAN_AM10H()          bfin_read16(CAN_AM10H)
1470#define bfin_write_CAN_AM10H(val)      bfin_write16(CAN_AM10H, val)
1471#define pCAN_AM11L                     ((uint16_t volatile *)CAN_AM11L) /* Mailbox 11 Low Acceptance Mask  */
1472#define bfin_read_CAN_AM11L()          bfin_read16(CAN_AM11L)
1473#define bfin_write_CAN_AM11L(val)      bfin_write16(CAN_AM11L, val)
1474#define pCAN_AM11H                     ((uint16_t volatile *)CAN_AM11H) /* Mailbox 11 High Acceptance Mask */
1475#define bfin_read_CAN_AM11H()          bfin_read16(CAN_AM11H)
1476#define bfin_write_CAN_AM11H(val)      bfin_write16(CAN_AM11H, val)
1477#define pCAN_AM12L                     ((uint16_t volatile *)CAN_AM12L) /* Mailbox 12 Low Acceptance Mask  */
1478#define bfin_read_CAN_AM12L()          bfin_read16(CAN_AM12L)
1479#define bfin_write_CAN_AM12L(val)      bfin_write16(CAN_AM12L, val)
1480#define pCAN_AM12H                     ((uint16_t volatile *)CAN_AM12H) /* Mailbox 12 High Acceptance Mask */
1481#define bfin_read_CAN_AM12H()          bfin_read16(CAN_AM12H)
1482#define bfin_write_CAN_AM12H(val)      bfin_write16(CAN_AM12H, val)
1483#define pCAN_AM13L                     ((uint16_t volatile *)CAN_AM13L) /* Mailbox 13 Low Acceptance Mask  */
1484#define bfin_read_CAN_AM13L()          bfin_read16(CAN_AM13L)
1485#define bfin_write_CAN_AM13L(val)      bfin_write16(CAN_AM13L, val)
1486#define pCAN_AM13H                     ((uint16_t volatile *)CAN_AM13H) /* Mailbox 13 High Acceptance Mask */
1487#define bfin_read_CAN_AM13H()          bfin_read16(CAN_AM13H)
1488#define bfin_write_CAN_AM13H(val)      bfin_write16(CAN_AM13H, val)
1489#define pCAN_AM14L                     ((uint16_t volatile *)CAN_AM14L) /* Mailbox 14 Low Acceptance Mask  */
1490#define bfin_read_CAN_AM14L()          bfin_read16(CAN_AM14L)
1491#define bfin_write_CAN_AM14L(val)      bfin_write16(CAN_AM14L, val)
1492#define pCAN_AM14H                     ((uint16_t volatile *)CAN_AM14H) /* Mailbox 14 High Acceptance Mask */
1493#define bfin_read_CAN_AM14H()          bfin_read16(CAN_AM14H)
1494#define bfin_write_CAN_AM14H(val)      bfin_write16(CAN_AM14H, val)
1495#define pCAN_AM15L                     ((uint16_t volatile *)CAN_AM15L) /* Mailbox 15 Low Acceptance Mask  */
1496#define bfin_read_CAN_AM15L()          bfin_read16(CAN_AM15L)
1497#define bfin_write_CAN_AM15L(val)      bfin_write16(CAN_AM15L, val)
1498#define pCAN_AM15H                     ((uint16_t volatile *)CAN_AM15H) /* Mailbox 15 High Acceptance Mask */
1499#define bfin_read_CAN_AM15H()          bfin_read16(CAN_AM15H)
1500#define bfin_write_CAN_AM15H(val)      bfin_write16(CAN_AM15H, val)
1501#define pCAN_AM16L                     ((uint16_t volatile *)CAN_AM16L) /* Mailbox 16 Low Acceptance Mask  */
1502#define bfin_read_CAN_AM16L()          bfin_read16(CAN_AM16L)
1503#define bfin_write_CAN_AM16L(val)      bfin_write16(CAN_AM16L, val)
1504#define pCAN_AM16H                     ((uint16_t volatile *)CAN_AM16H) /* Mailbox 16 High Acceptance Mask */
1505#define bfin_read_CAN_AM16H()          bfin_read16(CAN_AM16H)
1506#define bfin_write_CAN_AM16H(val)      bfin_write16(CAN_AM16H, val)
1507#define pCAN_AM17L                     ((uint16_t volatile *)CAN_AM17L) /* Mailbox 17 Low Acceptance Mask  */
1508#define bfin_read_CAN_AM17L()          bfin_read16(CAN_AM17L)
1509#define bfin_write_CAN_AM17L(val)      bfin_write16(CAN_AM17L, val)
1510#define pCAN_AM17H                     ((uint16_t volatile *)CAN_AM17H) /* Mailbox 17 High Acceptance Mask */
1511#define bfin_read_CAN_AM17H()          bfin_read16(CAN_AM17H)
1512#define bfin_write_CAN_AM17H(val)      bfin_write16(CAN_AM17H, val)
1513#define pCAN_AM18L                     ((uint16_t volatile *)CAN_AM18L) /* Mailbox 18 Low Acceptance Mask  */
1514#define bfin_read_CAN_AM18L()          bfin_read16(CAN_AM18L)
1515#define bfin_write_CAN_AM18L(val)      bfin_write16(CAN_AM18L, val)
1516#define pCAN_AM18H                     ((uint16_t volatile *)CAN_AM18H) /* Mailbox 18 High Acceptance Mask */
1517#define bfin_read_CAN_AM18H()          bfin_read16(CAN_AM18H)
1518#define bfin_write_CAN_AM18H(val)      bfin_write16(CAN_AM18H, val)
1519#define pCAN_AM19L                     ((uint16_t volatile *)CAN_AM19L) /* Mailbox 19 Low Acceptance Mask  */
1520#define bfin_read_CAN_AM19L()          bfin_read16(CAN_AM19L)
1521#define bfin_write_CAN_AM19L(val)      bfin_write16(CAN_AM19L, val)
1522#define pCAN_AM19H                     ((uint16_t volatile *)CAN_AM19H) /* Mailbox 19 High Acceptance Mask */
1523#define bfin_read_CAN_AM19H()          bfin_read16(CAN_AM19H)
1524#define bfin_write_CAN_AM19H(val)      bfin_write16(CAN_AM19H, val)
1525#define pCAN_AM20L                     ((uint16_t volatile *)CAN_AM20L) /* Mailbox 20 Low Acceptance Mask  */
1526#define bfin_read_CAN_AM20L()          bfin_read16(CAN_AM20L)
1527#define bfin_write_CAN_AM20L(val)      bfin_write16(CAN_AM20L, val)
1528#define pCAN_AM20H                     ((uint16_t volatile *)CAN_AM20H) /* Mailbox 20 High Acceptance Mask */
1529#define bfin_read_CAN_AM20H()          bfin_read16(CAN_AM20H)
1530#define bfin_write_CAN_AM20H(val)      bfin_write16(CAN_AM20H, val)
1531#define pCAN_AM21L                     ((uint16_t volatile *)CAN_AM21L) /* Mailbox 21 Low Acceptance Mask  */
1532#define bfin_read_CAN_AM21L()          bfin_read16(CAN_AM21L)
1533#define bfin_write_CAN_AM21L(val)      bfin_write16(CAN_AM21L, val)
1534#define pCAN_AM21H                     ((uint16_t volatile *)CAN_AM21H) /* Mailbox 21 High Acceptance Mask */
1535#define bfin_read_CAN_AM21H()          bfin_read16(CAN_AM21H)
1536#define bfin_write_CAN_AM21H(val)      bfin_write16(CAN_AM21H, val)
1537#define pCAN_AM22L                     ((uint16_t volatile *)CAN_AM22L) /* Mailbox 22 Low Acceptance Mask  */
1538#define bfin_read_CAN_AM22L()          bfin_read16(CAN_AM22L)
1539#define bfin_write_CAN_AM22L(val)      bfin_write16(CAN_AM22L, val)
1540#define pCAN_AM22H                     ((uint16_t volatile *)CAN_AM22H) /* Mailbox 22 High Acceptance Mask */
1541#define bfin_read_CAN_AM22H()          bfin_read16(CAN_AM22H)
1542#define bfin_write_CAN_AM22H(val)      bfin_write16(CAN_AM22H, val)
1543#define pCAN_AM23L                     ((uint16_t volatile *)CAN_AM23L) /* Mailbox 23 Low Acceptance Mask  */
1544#define bfin_read_CAN_AM23L()          bfin_read16(CAN_AM23L)
1545#define bfin_write_CAN_AM23L(val)      bfin_write16(CAN_AM23L, val)
1546#define pCAN_AM23H                     ((uint16_t volatile *)CAN_AM23H) /* Mailbox 23 High Acceptance Mask */
1547#define bfin_read_CAN_AM23H()          bfin_read16(CAN_AM23H)
1548#define bfin_write_CAN_AM23H(val)      bfin_write16(CAN_AM23H, val)
1549#define pCAN_AM24L                     ((uint16_t volatile *)CAN_AM24L) /* Mailbox 24 Low Acceptance Mask  */
1550#define bfin_read_CAN_AM24L()          bfin_read16(CAN_AM24L)
1551#define bfin_write_CAN_AM24L(val)      bfin_write16(CAN_AM24L, val)
1552#define pCAN_AM24H                     ((uint16_t volatile *)CAN_AM24H) /* Mailbox 24 High Acceptance Mask */
1553#define bfin_read_CAN_AM24H()          bfin_read16(CAN_AM24H)
1554#define bfin_write_CAN_AM24H(val)      bfin_write16(CAN_AM24H, val)
1555#define pCAN_AM25L                     ((uint16_t volatile *)CAN_AM25L) /* Mailbox 25 Low Acceptance Mask  */
1556#define bfin_read_CAN_AM25L()          bfin_read16(CAN_AM25L)
1557#define bfin_write_CAN_AM25L(val)      bfin_write16(CAN_AM25L, val)
1558#define pCAN_AM25H                     ((uint16_t volatile *)CAN_AM25H) /* Mailbox 25 High Acceptance Mask */
1559#define bfin_read_CAN_AM25H()          bfin_read16(CAN_AM25H)
1560#define bfin_write_CAN_AM25H(val)      bfin_write16(CAN_AM25H, val)
1561#define pCAN_AM26L                     ((uint16_t volatile *)CAN_AM26L) /* Mailbox 26 Low Acceptance Mask  */
1562#define bfin_read_CAN_AM26L()          bfin_read16(CAN_AM26L)
1563#define bfin_write_CAN_AM26L(val)      bfin_write16(CAN_AM26L, val)
1564#define pCAN_AM26H                     ((uint16_t volatile *)CAN_AM26H) /* Mailbox 26 High Acceptance Mask */
1565#define bfin_read_CAN_AM26H()          bfin_read16(CAN_AM26H)
1566#define bfin_write_CAN_AM26H(val)      bfin_write16(CAN_AM26H, val)
1567#define pCAN_AM27L                     ((uint16_t volatile *)CAN_AM27L) /* Mailbox 27 Low Acceptance Mask  */
1568#define bfin_read_CAN_AM27L()          bfin_read16(CAN_AM27L)
1569#define bfin_write_CAN_AM27L(val)      bfin_write16(CAN_AM27L, val)
1570#define pCAN_AM27H                     ((uint16_t volatile *)CAN_AM27H) /* Mailbox 27 High Acceptance Mask */
1571#define bfin_read_CAN_AM27H()          bfin_read16(CAN_AM27H)
1572#define bfin_write_CAN_AM27H(val)      bfin_write16(CAN_AM27H, val)
1573#define pCAN_AM28L                     ((uint16_t volatile *)CAN_AM28L) /* Mailbox 28 Low Acceptance Mask  */
1574#define bfin_read_CAN_AM28L()          bfin_read16(CAN_AM28L)
1575#define bfin_write_CAN_AM28L(val)      bfin_write16(CAN_AM28L, val)
1576#define pCAN_AM28H                     ((uint16_t volatile *)CAN_AM28H) /* Mailbox 28 High Acceptance Mask */
1577#define bfin_read_CAN_AM28H()          bfin_read16(CAN_AM28H)
1578#define bfin_write_CAN_AM28H(val)      bfin_write16(CAN_AM28H, val)
1579#define pCAN_AM29L                     ((uint16_t volatile *)CAN_AM29L) /* Mailbox 29 Low Acceptance Mask  */
1580#define bfin_read_CAN_AM29L()          bfin_read16(CAN_AM29L)
1581#define bfin_write_CAN_AM29L(val)      bfin_write16(CAN_AM29L, val)
1582#define pCAN_AM29H                     ((uint16_t volatile *)CAN_AM29H) /* Mailbox 29 High Acceptance Mask */
1583#define bfin_read_CAN_AM29H()          bfin_read16(CAN_AM29H)
1584#define bfin_write_CAN_AM29H(val)      bfin_write16(CAN_AM29H, val)
1585#define pCAN_AM30L                     ((uint16_t volatile *)CAN_AM30L) /* Mailbox 30 Low Acceptance Mask  */
1586#define bfin_read_CAN_AM30L()          bfin_read16(CAN_AM30L)
1587#define bfin_write_CAN_AM30L(val)      bfin_write16(CAN_AM30L, val)
1588#define pCAN_AM30H                     ((uint16_t volatile *)CAN_AM30H) /* Mailbox 30 High Acceptance Mask */
1589#define bfin_read_CAN_AM30H()          bfin_read16(CAN_AM30H)
1590#define bfin_write_CAN_AM30H(val)      bfin_write16(CAN_AM30H, val)
1591#define pCAN_AM31L                     ((uint16_t volatile *)CAN_AM31L) /* Mailbox 31 Low Acceptance Mask  */
1592#define bfin_read_CAN_AM31L()          bfin_read16(CAN_AM31L)
1593#define bfin_write_CAN_AM31L(val)      bfin_write16(CAN_AM31L, val)
1594#define pCAN_AM31H                     ((uint16_t volatile *)CAN_AM31H) /* Mailbox 31 High Acceptance Mask */
1595#define bfin_read_CAN_AM31H()          bfin_read16(CAN_AM31H)
1596#define bfin_write_CAN_AM31H(val)      bfin_write16(CAN_AM31H, val)
1597#define pCAN_MB00_DATA0                ((uint16_t volatile *)CAN_MB00_DATA0) /* Mailbox 0 Data Word 0 [15:0] Register */
1598#define bfin_read_CAN_MB00_DATA0()     bfin_read16(CAN_MB00_DATA0)
1599#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
1600#define pCAN_MB00_DATA1                ((uint16_t volatile *)CAN_MB00_DATA1) /* Mailbox 0 Data Word 1 [31:16] Register */
1601#define bfin_read_CAN_MB00_DATA1()     bfin_read16(CAN_MB00_DATA1)
1602#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
1603#define pCAN_MB00_DATA2                ((uint16_t volatile *)CAN_MB00_DATA2) /* Mailbox 0 Data Word 2 [47:32] Register */
1604#define bfin_read_CAN_MB00_DATA2()     bfin_read16(CAN_MB00_DATA2)
1605#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
1606#define pCAN_MB00_DATA3                ((uint16_t volatile *)CAN_MB00_DATA3) /* Mailbox 0 Data Word 3 [63:48] Register */
1607#define bfin_read_CAN_MB00_DATA3()     bfin_read16(CAN_MB00_DATA3)
1608#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
1609#define pCAN_MB00_LENGTH               ((uint16_t volatile *)CAN_MB00_LENGTH) /* Mailbox 0 Data Length Code Register */
1610#define bfin_read_CAN_MB00_LENGTH()    bfin_read16(CAN_MB00_LENGTH)
1611#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
1612#define pCAN_MB00_TIMESTAMP            ((uint16_t volatile *)CAN_MB00_TIMESTAMP) /* Mailbox 0 Time Stamp Value Register */
1613#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
1614#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
1615#define pCAN_MB00_ID0                  ((uint16_t volatile *)CAN_MB00_ID0) /* Mailbox 0 Identifier Low Register */
1616#define bfin_read_CAN_MB00_ID0()       bfin_read16(CAN_MB00_ID0)
1617#define bfin_write_CAN_MB00_ID0(val)   bfin_write16(CAN_MB00_ID0, val)
1618#define pCAN_MB00_ID1                  ((uint16_t volatile *)CAN_MB00_ID1) /* Mailbox 0 Identifier High Register */
1619#define bfin_read_CAN_MB00_ID1()       bfin_read16(CAN_MB00_ID1)
1620#define bfin_write_CAN_MB00_ID1(val)   bfin_write16(CAN_MB00_ID1, val)
1621#define pCAN_MB01_DATA0                ((uint16_t volatile *)CAN_MB01_DATA0) /* Mailbox 1 Data Word 0 [15:0] Register  */
1622#define bfin_read_CAN_MB01_DATA0()     bfin_read16(CAN_MB01_DATA0)
1623#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
1624#define pCAN_MB01_DATA1                ((uint16_t volatile *)CAN_MB01_DATA1) /* Mailbox 1 Data Word 1 [31:16] Register */
1625#define bfin_read_CAN_MB01_DATA1()     bfin_read16(CAN_MB01_DATA1)
1626#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
1627#define pCAN_MB01_DATA2                ((uint16_t volatile *)CAN_MB01_DATA2) /* Mailbox 1 Data Word 2 [47:32] Register */
1628#define bfin_read_CAN_MB01_DATA2()     bfin_read16(CAN_MB01_DATA2)
1629#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
1630#define pCAN_MB01_DATA3                ((uint16_t volatile *)CAN_MB01_DATA3) /* Mailbox 1 Data Word 3 [63:48] Register */
1631#define bfin_read_CAN_MB01_DATA3()     bfin_read16(CAN_MB01_DATA3)
1632#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
1633#define pCAN_MB01_LENGTH               ((uint16_t volatile *)CAN_MB01_LENGTH) /* Mailbox 1 Data Length Code Register */
1634#define bfin_read_CAN_MB01_LENGTH()    bfin_read16(CAN_MB01_LENGTH)
1635#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
1636#define pCAN_MB01_TIMESTAMP            ((uint16_t volatile *)CAN_MB01_TIMESTAMP) /* Mailbox 1 Time Stamp Value Register */
1637#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
1638#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
1639#define pCAN_MB01_ID0                  ((uint16_t volatile *)CAN_MB01_ID0) /* Mailbox 1 Identifier Low Register */
1640#define bfin_read_CAN_MB01_ID0()       bfin_read16(CAN_MB01_ID0)
1641#define bfin_write_CAN_MB01_ID0(val)   bfin_write16(CAN_MB01_ID0, val)
1642#define pCAN_MB01_ID1                  ((uint16_t volatile *)CAN_MB01_ID1) /* Mailbox 1 Identifier High Register */
1643#define bfin_read_CAN_MB01_ID1()       bfin_read16(CAN_MB01_ID1)
1644#define bfin_write_CAN_MB01_ID1(val)   bfin_write16(CAN_MB01_ID1, val)
1645#define pCAN_MB02_DATA0                ((uint16_t volatile *)CAN_MB02_DATA0) /* Mailbox 2 Data Word 0 [15:0] Register  */
1646#define bfin_read_CAN_MB02_DATA0()     bfin_read16(CAN_MB02_DATA0)
1647#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
1648#define pCAN_MB02_DATA1                ((uint16_t volatile *)CAN_MB02_DATA1) /* Mailbox 2 Data Word 1 [31:16] Register */
1649#define bfin_read_CAN_MB02_DATA1()     bfin_read16(CAN_MB02_DATA1)
1650#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
1651#define pCAN_MB02_DATA2                ((uint16_t volatile *)CAN_MB02_DATA2) /* Mailbox 2 Data Word 2 [47:32] Register */
1652#define bfin_read_CAN_MB02_DATA2()     bfin_read16(CAN_MB02_DATA2)
1653#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
1654#define pCAN_MB02_DATA3                ((uint16_t volatile *)CAN_MB02_DATA3) /* Mailbox 2 Data Word 3 [63:48] Register */
1655#define bfin_read_CAN_MB02_DATA3()     bfin_read16(CAN_MB02_DATA3)
1656#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
1657#define pCAN_MB02_LENGTH               ((uint16_t volatile *)CAN_MB02_LENGTH) /* Mailbox 2 Data Length Code Register    */
1658#define bfin_read_CAN_MB02_LENGTH()    bfin_read16(CAN_MB02_LENGTH)
1659#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
1660#define pCAN_MB02_TIMESTAMP            ((uint16_t volatile *)CAN_MB02_TIMESTAMP) /* Mailbox 2 Time Stamp Value Register */
1661#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
1662#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
1663#define pCAN_MB02_ID0                  ((uint16_t volatile *)CAN_MB02_ID0) /* Mailbox 2 Identifier Low Register */
1664#define bfin_read_CAN_MB02_ID0()       bfin_read16(CAN_MB02_ID0)
1665#define bfin_write_CAN_MB02_ID0(val)   bfin_write16(CAN_MB02_ID0, val)
1666#define pCAN_MB02_ID1                  ((uint16_t volatile *)CAN_MB02_ID1) /* Mailbox 2 Identifier High Register */
1667#define bfin_read_CAN_MB02_ID1()       bfin_read16(CAN_MB02_ID1)
1668#define bfin_write_CAN_MB02_ID1(val)   bfin_write16(CAN_MB02_ID1, val)
1669#define pCAN_MB03_DATA0                ((uint16_t volatile *)CAN_MB03_DATA0) /* Mailbox 3 Data Word 0 [15:0] Register  */
1670#define bfin_read_CAN_MB03_DATA0()     bfin_read16(CAN_MB03_DATA0)
1671#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
1672#define pCAN_MB03_DATA1                ((uint16_t volatile *)CAN_MB03_DATA1) /* Mailbox 3 Data Word 1 [31:16] Register */
1673#define bfin_read_CAN_MB03_DATA1()     bfin_read16(CAN_MB03_DATA1)
1674#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
1675#define pCAN_MB03_DATA2                ((uint16_t volatile *)CAN_MB03_DATA2) /* Mailbox 3 Data Word 2 [47:32] Register */
1676#define bfin_read_CAN_MB03_DATA2()     bfin_read16(CAN_MB03_DATA2)
1677#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
1678#define pCAN_MB03_DATA3                ((uint16_t volatile *)CAN_MB03_DATA3) /* Mailbox 3 Data Word 3 [63:48] Register */
1679#define bfin_read_CAN_MB03_DATA3()     bfin_read16(CAN_MB03_DATA3)
1680#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
1681#define pCAN_MB03_LENGTH               ((uint16_t volatile *)CAN_MB03_LENGTH) /* Mailbox 3 Data Length Code Register */
1682#define bfin_read_CAN_MB03_LENGTH()    bfin_read16(CAN_MB03_LENGTH)
1683#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
1684#define pCAN_MB03_TIMESTAMP            ((uint16_t volatile *)CAN_MB03_TIMESTAMP) /* Mailbox 3 Time Stamp Value Register */
1685#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
1686#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
1687#define pCAN_MB03_ID0                  ((uint16_t volatile *)CAN_MB03_ID0) /* Mailbox 3 Identifier Low Register */
1688#define bfin_read_CAN_MB03_ID0()       bfin_read16(CAN_MB03_ID0)
1689#define bfin_write_CAN_MB03_ID0(val)   bfin_write16(CAN_MB03_ID0, val)
1690#define pCAN_MB03_ID1                  ((uint16_t volatile *)CAN_MB03_ID1) /* Mailbox 3 Identifier High Register */
1691#define bfin_read_CAN_MB03_ID1()       bfin_read16(CAN_MB03_ID1)
1692#define bfin_write_CAN_MB03_ID1(val)   bfin_write16(CAN_MB03_ID1, val)
1693#define pCAN_MB04_DATA0                ((uint16_t volatile *)CAN_MB04_DATA0) /* Mailbox 4 Data Word 0 [15:0] Register */
1694#define bfin_read_CAN_MB04_DATA0()     bfin_read16(CAN_MB04_DATA0)
1695#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
1696#define pCAN_MB04_DATA1                ((uint16_t volatile *)CAN_MB04_DATA1) /* Mailbox 4 Data Word 1 [31:16] Register */
1697#define bfin_read_CAN_MB04_DATA1()     bfin_read16(CAN_MB04_DATA1)
1698#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
1699#define pCAN_MB04_DATA2                ((uint16_t volatile *)CAN_MB04_DATA2) /* Mailbox 4 Data Word 2 [47:32] Register */
1700#define bfin_read_CAN_MB04_DATA2()     bfin_read16(CAN_MB04_DATA2)
1701#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
1702#define pCAN_MB04_DATA3                ((uint16_t volatile *)CAN_MB04_DATA3) /* Mailbox 4 Data Word 3 [63:48] Register */
1703#define bfin_read_CAN_MB04_DATA3()     bfin_read16(CAN_MB04_DATA3)
1704#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
1705#define pCAN_MB04_LENGTH               ((uint16_t volatile *)CAN_MB04_LENGTH) /* Mailbox 4 Data Length Code Register */
1706#define bfin_read_CAN_MB04_LENGTH()    bfin_read16(CAN_MB04_LENGTH)
1707#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
1708#define pCAN_MB04_TIMESTAMP            ((uint16_t volatile *)CAN_MB04_TIMESTAMP) /* Mailbox 4 Time Stamp Value Register */
1709#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
1710#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
1711#define pCAN_MB04_ID0                  ((uint16_t volatile *)CAN_MB04_ID0) /* Mailbox 4 Identifier Low Register */
1712#define bfin_read_CAN_MB04_ID0()       bfin_read16(CAN_MB04_ID0)
1713#define bfin_write_CAN_MB04_ID0(val)   bfin_write16(CAN_MB04_ID0, val)
1714#define pCAN_MB04_ID1                  ((uint16_t volatile *)CAN_MB04_ID1) /* Mailbox 4 Identifier High Register */
1715#define bfin_read_CAN_MB04_ID1()       bfin_read16(CAN_MB04_ID1)
1716#define bfin_write_CAN_MB04_ID1(val)   bfin_write16(CAN_MB04_ID1, val)
1717#define pCAN_MB05_DATA0                ((uint16_t volatile *)CAN_MB05_DATA0) /* Mailbox 5 Data Word 0 [15:0] Register  */
1718#define bfin_read_CAN_MB05_DATA0()     bfin_read16(CAN_MB05_DATA0)
1719#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
1720#define pCAN_MB05_DATA1                ((uint16_t volatile *)CAN_MB05_DATA1) /* Mailbox 5 Data Word 1 [31:16] Register */
1721#define bfin_read_CAN_MB05_DATA1()     bfin_read16(CAN_MB05_DATA1)
1722#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
1723#define pCAN_MB05_DATA2                ((uint16_t volatile *)CAN_MB05_DATA2) /* Mailbox 5 Data Word 2 [47:32] Register */
1724#define bfin_read_CAN_MB05_DATA2()     bfin_read16(CAN_MB05_DATA2)
1725#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
1726#define pCAN_MB05_DATA3                ((uint16_t volatile *)CAN_MB05_DATA3) /* Mailbox 5 Data Word 3 [63:48] Register */
1727#define bfin_read_CAN_MB05_DATA3()     bfin_read16(CAN_MB05_DATA3)
1728#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
1729#define pCAN_MB05_LENGTH               ((uint16_t volatile *)CAN_MB05_LENGTH) /* Mailbox 5 Data Length Code Register */
1730#define bfin_read_CAN_MB05_LENGTH()    bfin_read16(CAN_MB05_LENGTH)
1731#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
1732#define pCAN_MB05_TIMESTAMP            ((uint16_t volatile *)CAN_MB05_TIMESTAMP) /* Mailbox 5 Time Stamp Value Register */
1733#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
1734#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
1735#define pCAN_MB05_ID0                  ((uint16_t volatile *)CAN_MB05_ID0) /* Mailbox 5 Identifier Low Register */
1736#define bfin_read_CAN_MB05_ID0()       bfin_read16(CAN_MB05_ID0)
1737#define bfin_write_CAN_MB05_ID0(val)   bfin_write16(CAN_MB05_ID0, val)
1738#define pCAN_MB05_ID1                  ((uint16_t volatile *)CAN_MB05_ID1) /* Mailbox 5 Identifier High Register */
1739#define bfin_read_CAN_MB05_ID1()       bfin_read16(CAN_MB05_ID1)
1740#define bfin_write_CAN_MB05_ID1(val)   bfin_write16(CAN_MB05_ID1, val)
1741#define pCAN_MB06_DATA0                ((uint16_t volatile *)CAN_MB06_DATA0) /* Mailbox 6 Data Word 0 [15:0] Register  */
1742#define bfin_read_CAN_MB06_DATA0()     bfin_read16(CAN_MB06_DATA0)
1743#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
1744#define pCAN_MB06_DATA1                ((uint16_t volatile *)CAN_MB06_DATA1) /* Mailbox 6 Data Word 1 [31:16] Register */
1745#define bfin_read_CAN_MB06_DATA1()     bfin_read16(CAN_MB06_DATA1)
1746#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
1747#define pCAN_MB06_DATA2                ((uint16_t volatile *)CAN_MB06_DATA2) /* Mailbox 6 Data Word 2 [47:32] Register */
1748#define bfin_read_CAN_MB06_DATA2()     bfin_read16(CAN_MB06_DATA2)
1749#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
1750#define pCAN_MB06_DATA3                ((uint16_t volatile *)CAN_MB06_DATA3) /* Mailbox 6 Data Word 3 [63:48] Register */
1751#define bfin_read_CAN_MB06_DATA3()     bfin_read16(CAN_MB06_DATA3)
1752#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
1753#define pCAN_MB06_LENGTH               ((uint16_t volatile *)CAN_MB06_LENGTH) /* Mailbox 6 Data Length Code Register */
1754#define bfin_read_CAN_MB06_LENGTH()    bfin_read16(CAN_MB06_LENGTH)
1755#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
1756#define pCAN_MB06_TIMESTAMP            ((uint16_t volatile *)CAN_MB06_TIMESTAMP) /* Mailbox 6 Time Stamp Value Register */
1757#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
1758#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
1759#define pCAN_MB06_ID0                  ((uint16_t volatile *)CAN_MB06_ID0) /* Mailbox 6 Identifier Low Register */
1760#define bfin_read_CAN_MB06_ID0()       bfin_read16(CAN_MB06_ID0)
1761#define bfin_write_CAN_MB06_ID0(val)   bfin_write16(CAN_MB06_ID0, val)
1762#define pCAN_MB06_ID1                  ((uint16_t volatile *)CAN_MB06_ID1) /* Mailbox 6 Identifier High Register */
1763#define bfin_read_CAN_MB06_ID1()       bfin_read16(CAN_MB06_ID1)
1764#define bfin_write_CAN_MB06_ID1(val)   bfin_write16(CAN_MB06_ID1, val)
1765#define pCAN_MB07_DATA0                ((uint16_t volatile *)CAN_MB07_DATA0) /* Mailbox 7 Data Word 0 [15:0] Register */
1766#define bfin_read_CAN_MB07_DATA0()     bfin_read16(CAN_MB07_DATA0)
1767#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
1768#define pCAN_MB07_DATA1                ((uint16_t volatile *)CAN_MB07_DATA1) /* Mailbox 7 Data Word 1 [31:16] Register */
1769#define bfin_read_CAN_MB07_DATA1()     bfin_read16(CAN_MB07_DATA1)
1770#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
1771#define pCAN_MB07_DATA2                ((uint16_t volatile *)CAN_MB07_DATA2) /* Mailbox 7 Data Word 2 [47:32] Register */
1772#define bfin_read_CAN_MB07_DATA2()     bfin_read16(CAN_MB07_DATA2)
1773#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
1774#define pCAN_MB07_DATA3                ((uint16_t volatile *)CAN_MB07_DATA3) /* Mailbox 7 Data Word 3 [63:48] Register */
1775#define bfin_read_CAN_MB07_DATA3()     bfin_read16(CAN_MB07_DATA3)
1776#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
1777#define pCAN_MB07_LENGTH               ((uint16_t volatile *)CAN_MB07_LENGTH) /* Mailbox 7 Data Length Code Register */
1778#define bfin_read_CAN_MB07_LENGTH()    bfin_read16(CAN_MB07_LENGTH)
1779#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
1780#define pCAN_MB07_TIMESTAMP            ((uint16_t volatile *)CAN_MB07_TIMESTAMP) /* Mailbox 7 Time Stamp Value Register */
1781#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
1782#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
1783#define pCAN_MB07_ID0                  ((uint16_t volatile *)CAN_MB07_ID0) /* Mailbox 7 Identifier Low Register */
1784#define bfin_read_CAN_MB07_ID0()       bfin_read16(CAN_MB07_ID0)
1785#define bfin_write_CAN_MB07_ID0(val)   bfin_write16(CAN_MB07_ID0, val)
1786#define pCAN_MB07_ID1                  ((uint16_t volatile *)CAN_MB07_ID1) /* Mailbox 7 Identifier High Register */
1787#define bfin_read_CAN_MB07_ID1()       bfin_read16(CAN_MB07_ID1)
1788#define bfin_write_CAN_MB07_ID1(val)   bfin_write16(CAN_MB07_ID1, val)
1789#define pCAN_MB08_DATA0                ((uint16_t volatile *)CAN_MB08_DATA0) /* Mailbox 8 Data Word 0 [15:0] Register */
1790#define bfin_read_CAN_MB08_DATA0()     bfin_read16(CAN_MB08_DATA0)
1791#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
1792#define pCAN_MB08_DATA1                ((uint16_t volatile *)CAN_MB08_DATA1) /* Mailbox 8 Data Word 1 [31:16] Register */
1793#define bfin_read_CAN_MB08_DATA1()     bfin_read16(CAN_MB08_DATA1)
1794#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
1795#define pCAN_MB08_DATA2                ((uint16_t volatile *)CAN_MB08_DATA2) /* Mailbox 8 Data Word 2 [47:32] Register */
1796#define bfin_read_CAN_MB08_DATA2()     bfin_read16(CAN_MB08_DATA2)
1797#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
1798#define pCAN_MB08_DATA3                ((uint16_t volatile *)CAN_MB08_DATA3) /* Mailbox 8 Data Word 3 [63:48] Register */
1799#define bfin_read_CAN_MB08_DATA3()     bfin_read16(CAN_MB08_DATA3)
1800#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
1801#define pCAN_MB08_LENGTH               ((uint16_t volatile *)CAN_MB08_LENGTH) /* Mailbox 8 Data Length Code Register */
1802#define bfin_read_CAN_MB08_LENGTH()    bfin_read16(CAN_MB08_LENGTH)
1803#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
1804#define pCAN_MB08_TIMESTAMP            ((uint16_t volatile *)CAN_MB08_TIMESTAMP) /* Mailbox 8 Time Stamp Value Register */
1805#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
1806#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
1807#define pCAN_MB08_ID0                  ((uint16_t volatile *)CAN_MB08_ID0) /* Mailbox 8 Identifier Low Register */
1808#define bfin_read_CAN_MB08_ID0()       bfin_read16(CAN_MB08_ID0)
1809#define bfin_write_CAN_MB08_ID0(val)   bfin_write16(CAN_MB08_ID0, val)
1810#define pCAN_MB08_ID1                  ((uint16_t volatile *)CAN_MB08_ID1) /* Mailbox 8 Identifier High Register */
1811#define bfin_read_CAN_MB08_ID1()       bfin_read16(CAN_MB08_ID1)
1812#define bfin_write_CAN_MB08_ID1(val)   bfin_write16(CAN_MB08_ID1, val)
1813#define pCAN_MB09_DATA0                ((uint16_t volatile *)CAN_MB09_DATA0) /* Mailbox 9 Data Word 0 [15:0] Register */
1814#define bfin_read_CAN_MB09_DATA0()     bfin_read16(CAN_MB09_DATA0)
1815#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
1816#define pCAN_MB09_DATA1                ((uint16_t volatile *)CAN_MB09_DATA1) /* Mailbox 9 Data Word 1 [31:16] Register */
1817#define bfin_read_CAN_MB09_DATA1()     bfin_read16(CAN_MB09_DATA1)
1818#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
1819#define pCAN_MB09_DATA2                ((uint16_t volatile *)CAN_MB09_DATA2) /* Mailbox 9 Data Word 2 [47:32] Register */
1820#define bfin_read_CAN_MB09_DATA2()     bfin_read16(CAN_MB09_DATA2)
1821#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
1822#define pCAN_MB09_DATA3                ((uint16_t volatile *)CAN_MB09_DATA3) /* Mailbox 9 Data Word 3 [63:48] Register */
1823#define bfin_read_CAN_MB09_DATA3()     bfin_read16(CAN_MB09_DATA3)
1824#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
1825#define pCAN_MB09_LENGTH               ((uint16_t volatile *)CAN_MB09_LENGTH) /* Mailbox 9 Data Length Code Register */
1826#define bfin_read_CAN_MB09_LENGTH()    bfin_read16(CAN_MB09_LENGTH)
1827#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
1828#define pCAN_MB09_TIMESTAMP            ((uint16_t volatile *)CAN_MB09_TIMESTAMP) /* Mailbox 9 Time Stamp Value Register */
1829#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
1830#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
1831#define pCAN_MB09_ID0                  ((uint16_t volatile *)CAN_MB09_ID0) /* Mailbox 9 Identifier Low Register */
1832#define bfin_read_CAN_MB09_ID0()       bfin_read16(CAN_MB09_ID0)
1833#define bfin_write_CAN_MB09_ID0(val)   bfin_write16(CAN_MB09_ID0, val)
1834#define pCAN_MB09_ID1                  ((uint16_t volatile *)CAN_MB09_ID1) /* Mailbox 9 Identifier High Register */
1835#define bfin_read_CAN_MB09_ID1()       bfin_read16(CAN_MB09_ID1)
1836#define bfin_write_CAN_MB09_ID1(val)   bfin_write16(CAN_MB09_ID1, val)
1837#define pCAN_MB10_DATA0                ((uint16_t volatile *)CAN_MB10_DATA0) /* Mailbox 10 Data Word 0 [15:0] Register */
1838#define bfin_read_CAN_MB10_DATA0()     bfin_read16(CAN_MB10_DATA0)
1839#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
1840#define pCAN_MB10_DATA1                ((uint16_t volatile *)CAN_MB10_DATA1) /* Mailbox 10 Data Word 1 [31:16] Register */
1841#define bfin_read_CAN_MB10_DATA1()     bfin_read16(CAN_MB10_DATA1)
1842#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
1843#define pCAN_MB10_DATA2                ((uint16_t volatile *)CAN_MB10_DATA2) /* Mailbox 10 Data Word 2 [47:32] Register */
1844#define bfin_read_CAN_MB10_DATA2()     bfin_read16(CAN_MB10_DATA2)
1845#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
1846#define pCAN_MB10_DATA3                ((uint16_t volatile *)CAN_MB10_DATA3) /* Mailbox 10 Data Word 3 [63:48] Register */
1847#define bfin_read_CAN_MB10_DATA3()     bfin_read16(CAN_MB10_DATA3)
1848#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
1849#define pCAN_MB10_LENGTH               ((uint16_t volatile *)CAN_MB10_LENGTH) /* Mailbox 10 Data Length Code Register */
1850#define bfin_read_CAN_MB10_LENGTH()    bfin_read16(CAN_MB10_LENGTH)
1851#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
1852#define pCAN_MB10_TIMESTAMP            ((uint16_t volatile *)CAN_MB10_TIMESTAMP) /* Mailbox 10 Time Stamp Value Register */
1853#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
1854#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
1855#define pCAN_MB10_ID0                  ((uint16_t volatile *)CAN_MB10_ID0) /* Mailbox 10 Identifier Low Register */
1856#define bfin_read_CAN_MB10_ID0()       bfin_read16(CAN_MB10_ID0)
1857#define bfin_write_CAN_MB10_ID0(val)   bfin_write16(CAN_MB10_ID0, val)
1858#define pCAN_MB10_ID1                  ((uint16_t volatile *)CAN_MB10_ID1) /* Mailbox 10 Identifier High Register */
1859#define bfin_read_CAN_MB10_ID1()       bfin_read16(CAN_MB10_ID1)
1860#define bfin_write_CAN_MB10_ID1(val)   bfin_write16(CAN_MB10_ID1, val)
1861#define pCAN_MB11_DATA0                ((uint16_t volatile *)CAN_MB11_DATA0) /* Mailbox 11 Data Word 0 [15:0] Register */
1862#define bfin_read_CAN_MB11_DATA0()     bfin_read16(CAN_MB11_DATA0)
1863#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
1864#define pCAN_MB11_DATA1                ((uint16_t volatile *)CAN_MB11_DATA1) /* Mailbox 11 Data Word 1 [31:16] Register */
1865#define bfin_read_CAN_MB11_DATA1()     bfin_read16(CAN_MB11_DATA1)
1866#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
1867#define pCAN_MB11_DATA2                ((uint16_t volatile *)CAN_MB11_DATA2) /* Mailbox 11 Data Word 2 [47:32] Register */
1868#define bfin_read_CAN_MB11_DATA2()     bfin_read16(CAN_MB11_DATA2)
1869#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
1870#define pCAN_MB11_DATA3                ((uint16_t volatile *)CAN_MB11_DATA3) /* Mailbox 11 Data Word 3 [63:48] Register */
1871#define bfin_read_CAN_MB11_DATA3()     bfin_read16(CAN_MB11_DATA3)
1872#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
1873#define pCAN_MB11_LENGTH               ((uint16_t volatile *)CAN_MB11_LENGTH) /* Mailbox 11 Data Length Code Register */
1874#define bfin_read_CAN_MB11_LENGTH()    bfin_read16(CAN_MB11_LENGTH)
1875#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
1876#define pCAN_MB11_TIMESTAMP            ((uint16_t volatile *)CAN_MB11_TIMESTAMP) /* Mailbox 11 Time Stamp Value Register */
1877#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
1878#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
1879#define pCAN_MB11_ID0                  ((uint16_t volatile *)CAN_MB11_ID0) /* Mailbox 11 Identifier Low Register */
1880#define bfin_read_CAN_MB11_ID0()       bfin_read16(CAN_MB11_ID0)
1881#define bfin_write_CAN_MB11_ID0(val)   bfin_write16(CAN_MB11_ID0, val)
1882#define pCAN_MB11_ID1                  ((uint16_t volatile *)CAN_MB11_ID1) /* Mailbox 11 Identifier High Register */
1883#define bfin_read_CAN_MB11_ID1()       bfin_read16(CAN_MB11_ID1)
1884#define bfin_write_CAN_MB11_ID1(val)   bfin_write16(CAN_MB11_ID1, val)
1885#define pCAN_MB12_DATA0                ((uint16_t volatile *)CAN_MB12_DATA0) /* Mailbox 12 Data Word 0 [15:0] Register */
1886#define bfin_read_CAN_MB12_DATA0()     bfin_read16(CAN_MB12_DATA0)
1887#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
1888#define pCAN_MB12_DATA1                ((uint16_t volatile *)CAN_MB12_DATA1) /* Mailbox 12 Data Word 1 [31:16] Register */
1889#define bfin_read_CAN_MB12_DATA1()     bfin_read16(CAN_MB12_DATA1)
1890#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
1891#define pCAN_MB12_DATA2                ((uint16_t volatile *)CAN_MB12_DATA2) /* Mailbox 12 Data Word 2 [47:32] Register */
1892#define bfin_read_CAN_MB12_DATA2()     bfin_read16(CAN_MB12_DATA2)
1893#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
1894#define pCAN_MB12_DATA3                ((uint16_t volatile *)CAN_MB12_DATA3) /* Mailbox 12 Data Word 3 [63:48] Register */
1895#define bfin_read_CAN_MB12_DATA3()     bfin_read16(CAN_MB12_DATA3)
1896#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
1897#define pCAN_MB12_LENGTH               ((uint16_t volatile *)CAN_MB12_LENGTH) /* Mailbox 12 Data Length Code Register */
1898#define bfin_read_CAN_MB12_LENGTH()    bfin_read16(CAN_MB12_LENGTH)
1899#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
1900#define pCAN_MB12_TIMESTAMP            ((uint16_t volatile *)CAN_MB12_TIMESTAMP) /* Mailbox 12 Time Stamp Value Register */
1901#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
1902#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
1903#define pCAN_MB12_ID0                  ((uint16_t volatile *)CAN_MB12_ID0) /* Mailbox 12 Identifier Low Register */
1904#define bfin_read_CAN_MB12_ID0()       bfin_read16(CAN_MB12_ID0)
1905#define bfin_write_CAN_MB12_ID0(val)   bfin_write16(CAN_MB12_ID0, val)
1906#define pCAN_MB12_ID1                  ((uint16_t volatile *)CAN_MB12_ID1) /* Mailbox 12 Identifier High Register */
1907#define bfin_read_CAN_MB12_ID1()       bfin_read16(CAN_MB12_ID1)
1908#define bfin_write_CAN_MB12_ID1(val)   bfin_write16(CAN_MB12_ID1, val)
1909#define pCAN_MB13_DATA0                ((uint16_t volatile *)CAN_MB13_DATA0) /* Mailbox 13 Data Word 0 [15:0] Register */
1910#define bfin_read_CAN_MB13_DATA0()     bfin_read16(CAN_MB13_DATA0)
1911#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
1912#define pCAN_MB13_DATA1                ((uint16_t volatile *)CAN_MB13_DATA1) /* Mailbox 13 Data Word 1 [31:16] Register */
1913#define bfin_read_CAN_MB13_DATA1()     bfin_read16(CAN_MB13_DATA1)
1914#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
1915#define pCAN_MB13_DATA2                ((uint16_t volatile *)CAN_MB13_DATA2) /* Mailbox 13 Data Word 2 [47:32] Register */
1916#define bfin_read_CAN_MB13_DATA2()     bfin_read16(CAN_MB13_DATA2)
1917#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
1918#define pCAN_MB13_DATA3                ((uint16_t volatile *)CAN_MB13_DATA3) /* Mailbox 13 Data Word 3 [63:48] Register */
1919#define bfin_read_CAN_MB13_DATA3()     bfin_read16(CAN_MB13_DATA3)
1920#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
1921#define pCAN_MB13_LENGTH               ((uint16_t volatile *)CAN_MB13_LENGTH) /* Mailbox 13 Data Length Code Register */
1922#define bfin_read_CAN_MB13_LENGTH()    bfin_read16(CAN_MB13_LENGTH)
1923#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
1924#define pCAN_MB13_TIMESTAMP            ((uint16_t volatile *)CAN_MB13_TIMESTAMP) /* Mailbox 13 Time Stamp Value Register */
1925#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
1926#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
1927#define pCAN_MB13_ID0                  ((uint16_t volatile *)CAN_MB13_ID0) /* Mailbox 13 Identifier Low Register */
1928#define bfin_read_CAN_MB13_ID0()       bfin_read16(CAN_MB13_ID0)
1929#define bfin_write_CAN_MB13_ID0(val)   bfin_write16(CAN_MB13_ID0, val)
1930#define pCAN_MB13_ID1                  ((uint16_t volatile *)CAN_MB13_ID1) /* Mailbox 13 Identifier High Register */
1931#define bfin_read_CAN_MB13_ID1()       bfin_read16(CAN_MB13_ID1)
1932#define bfin_write_CAN_MB13_ID1(val)   bfin_write16(CAN_MB13_ID1, val)
1933#define pCAN_MB14_DATA0                ((uint16_t volatile *)CAN_MB14_DATA0) /* Mailbox 14 Data Word 0 [15:0] Register */
1934#define bfin_read_CAN_MB14_DATA0()     bfin_read16(CAN_MB14_DATA0)
1935#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
1936#define pCAN_MB14_DATA1                ((uint16_t volatile *)CAN_MB14_DATA1) /* Mailbox 14 Data Word 1 [31:16] Register */
1937#define bfin_read_CAN_MB14_DATA1()     bfin_read16(CAN_MB14_DATA1)
1938#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
1939#define pCAN_MB14_DATA2                ((uint16_t volatile *)CAN_MB14_DATA2) /* Mailbox 14 Data Word 2 [47:32] Register */
1940#define bfin_read_CAN_MB14_DATA2()     bfin_read16(CAN_MB14_DATA2)
1941#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
1942#define pCAN_MB14_DATA3                ((uint16_t volatile *)CAN_MB14_DATA3) /* Mailbox 14 Data Word 3 [63:48] Register */
1943#define bfin_read_CAN_MB14_DATA3()     bfin_read16(CAN_MB14_DATA3)
1944#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
1945#define pCAN_MB14_LENGTH               ((uint16_t volatile *)CAN_MB14_LENGTH) /* Mailbox 14 Data Length Code Register */
1946#define bfin_read_CAN_MB14_LENGTH()    bfin_read16(CAN_MB14_LENGTH)
1947#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
1948#define pCAN_MB14_TIMESTAMP            ((uint16_t volatile *)CAN_MB14_TIMESTAMP) /* Mailbox 14 Time Stamp Value Register */
1949#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
1950#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
1951#define pCAN_MB14_ID0                  ((uint16_t volatile *)CAN_MB14_ID0) /* Mailbox 14 Identifier Low Register */
1952#define bfin_read_CAN_MB14_ID0()       bfin_read16(CAN_MB14_ID0)
1953#define bfin_write_CAN_MB14_ID0(val)   bfin_write16(CAN_MB14_ID0, val)
1954#define pCAN_MB14_ID1                  ((uint16_t volatile *)CAN_MB14_ID1) /* Mailbox 14 Identifier High Register */
1955#define bfin_read_CAN_MB14_ID1()       bfin_read16(CAN_MB14_ID1)
1956#define bfin_write_CAN_MB14_ID1(val)   bfin_write16(CAN_MB14_ID1, val)
1957#define pCAN_MB15_DATA0                ((uint16_t volatile *)CAN_MB15_DATA0) /* Mailbox 15 Data Word 0 [15:0] Register */
1958#define bfin_read_CAN_MB15_DATA0()     bfin_read16(CAN_MB15_DATA0)
1959#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
1960#define pCAN_MB15_DATA1                ((uint16_t volatile *)CAN_MB15_DATA1) /* Mailbox 15 Data Word 1 [31:16] Register */
1961#define bfin_read_CAN_MB15_DATA1()     bfin_read16(CAN_MB15_DATA1)
1962#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
1963#define pCAN_MB15_DATA2                ((uint16_t volatile *)CAN_MB15_DATA2) /* Mailbox 15 Data Word 2 [47:32] Register */
1964#define bfin_read_CAN_MB15_DATA2()     bfin_read16(CAN_MB15_DATA2)
1965#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
1966#define pCAN_MB15_DATA3                ((uint16_t volatile *)CAN_MB15_DATA3) /* Mailbox 15 Data Word 3 [63:48] Register */
1967#define bfin_read_CAN_MB15_DATA3()     bfin_read16(CAN_MB15_DATA3)
1968#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
1969#define pCAN_MB15_LENGTH               ((uint16_t volatile *)CAN_MB15_LENGTH) /* Mailbox 15 Data Length Code Register */
1970#define bfin_read_CAN_MB15_LENGTH()    bfin_read16(CAN_MB15_LENGTH)
1971#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
1972#define pCAN_MB15_TIMESTAMP            ((uint16_t volatile *)CAN_MB15_TIMESTAMP) /* Mailbox 15 Time Stamp Value Register */
1973#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
1974#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
1975#define pCAN_MB15_ID0                  ((uint16_t volatile *)CAN_MB15_ID0) /* Mailbox 15 Identifier Low Register */
1976#define bfin_read_CAN_MB15_ID0()       bfin_read16(CAN_MB15_ID0)
1977#define bfin_write_CAN_MB15_ID0(val)   bfin_write16(CAN_MB15_ID0, val)
1978#define pCAN_MB15_ID1                  ((uint16_t volatile *)CAN_MB15_ID1) /* Mailbox 15 Identifier High Register */
1979#define bfin_read_CAN_MB15_ID1()       bfin_read16(CAN_MB15_ID1)
1980#define bfin_write_CAN_MB15_ID1(val)   bfin_write16(CAN_MB15_ID1, val)
1981#define pCAN_MB16_DATA0                ((uint16_t volatile *)CAN_MB16_DATA0) /* Mailbox 16 Data Word 0 [15:0] Register */
1982#define bfin_read_CAN_MB16_DATA0()     bfin_read16(CAN_MB16_DATA0)
1983#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
1984#define pCAN_MB16_DATA1                ((uint16_t volatile *)CAN_MB16_DATA1) /* Mailbox 16 Data Word 1 [31:16] Register */
1985#define bfin_read_CAN_MB16_DATA1()     bfin_read16(CAN_MB16_DATA1)
1986#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
1987#define pCAN_MB16_DATA2                ((uint16_t volatile *)CAN_MB16_DATA2) /* Mailbox 16 Data Word 2 [47:32] Register */
1988#define bfin_read_CAN_MB16_DATA2()     bfin_read16(CAN_MB16_DATA2)
1989#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
1990#define pCAN_MB16_DATA3                ((uint16_t volatile *)CAN_MB16_DATA3) /* Mailbox 16 Data Word 3 [63:48] Register */
1991#define bfin_read_CAN_MB16_DATA3()     bfin_read16(CAN_MB16_DATA3)
1992#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
1993#define pCAN_MB16_LENGTH               ((uint16_t volatile *)CAN_MB16_LENGTH) /* Mailbox 16 Data Length Code Register */
1994#define bfin_read_CAN_MB16_LENGTH()    bfin_read16(CAN_MB16_LENGTH)
1995#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
1996#define pCAN_MB16_TIMESTAMP            ((uint16_t volatile *)CAN_MB16_TIMESTAMP) /* Mailbox 16 Time Stamp Value Register */
1997#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
1998#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
1999#define pCAN_MB16_ID0                  ((uint16_t volatile *)CAN_MB16_ID0) /* Mailbox 16 Identifier Low Register */
2000#define bfin_read_CAN_MB16_ID0()       bfin_read16(CAN_MB16_ID0)

2001#define bfin_write_CAN_MB16_ID0(val)   bfin_write16(CAN_MB16_ID0, val)
2002#define pCAN_MB16_ID1                  ((uint16_t volatile *)CAN_MB16_ID1) /* Mailbox 16 Identifier High Register */
2003#define bfin_read_CAN_MB16_ID1()       bfin_read16(CAN_MB16_ID1)
2004#define bfin_write_CAN_MB16_ID1(val)   bfin_write16(CAN_MB16_ID1, val)
2005#define pCAN_MB17_DATA0                ((uint16_t volatile *)CAN_MB17_DATA0) /* Mailbox 17 Data Word 0 [15:0] Register */
2006#define bfin_read_CAN_MB17_DATA0()     bfin_read16(CAN_MB17_DATA0)
2007#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
2008#define pCAN_MB17_DATA1                ((uint16_t volatile *)CAN_MB17_DATA1) /* Mailbox 17 Data Word 1 [31:16] Register */
2009#define bfin_read_CAN_MB17_DATA1()     bfin_read16(CAN_MB17_DATA1)
2010#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
2011#define pCAN_MB17_DATA2                ((uint16_t volatile *)CAN_MB17_DATA2) /* Mailbox 17 Data Word 2 [47:32] Register */
2012#define bfin_read_CAN_MB17_DATA2()     bfin_read16(CAN_MB17_DATA2)
2013#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
2014#define pCAN_MB17_DATA3                ((uint16_t volatile *)CAN_MB17_DATA3) /* Mailbox 17 Data Word 3 [63:48] Register */
2015#define bfin_read_CAN_MB17_DATA3()     bfin_read16(CAN_MB17_DATA3)
2016#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
2017#define pCAN_MB17_LENGTH               ((uint16_t volatile *)CAN_MB17_LENGTH) /* Mailbox 17 Data Length Code Register */
2018#define bfin_read_CAN_MB17_LENGTH()    bfin_read16(CAN_MB17_LENGTH)
2019#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
2020#define pCAN_MB17_TIMESTAMP            ((uint16_t volatile *)CAN_MB17_TIMESTAMP) /* Mailbox 17 Time Stamp Value Register */
2021#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
2022#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
2023#define pCAN_MB17_ID0                  ((uint16_t volatile *)CAN_MB17_ID0) /* Mailbox 17 Identifier Low Register */
2024#define bfin_read_CAN_MB17_ID0()       bfin_read16(CAN_MB17_ID0)
2025#define bfin_write_CAN_MB17_ID0(val)   bfin_write16(CAN_MB17_ID0, val)
2026#define pCAN_MB17_ID1                  ((uint16_t volatile *)CAN_MB17_ID1) /* Mailbox 17 Identifier High Register */
2027#define bfin_read_CAN_MB17_ID1()       bfin_read16(CAN_MB17_ID1)
2028#define bfin_write_CAN_MB17_ID1(val)   bfin_write16(CAN_MB17_ID1, val)
2029#define pCAN_MB18_DATA0                ((uint16_t volatile *)CAN_MB18_DATA0) /* Mailbox 18 Data Word 0 [15:0] Register */
2030#define bfin_read_CAN_MB18_DATA0()     bfin_read16(CAN_MB18_DATA0)
2031#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
2032#define pCAN_MB18_DATA1                ((uint16_t volatile *)CAN_MB18_DATA1) /* Mailbox 18 Data Word 1 [31:16] Register */
2033#define bfin_read_CAN_MB18_DATA1()     bfin_read16(CAN_MB18_DATA1)
2034#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
2035#define pCAN_MB18_DATA2                ((uint16_t volatile *)CAN_MB18_DATA2) /* Mailbox 18 Data Word 2 [47:32] Register */
2036#define bfin_read_CAN_MB18_DATA2()     bfin_read16(CAN_MB18_DATA2)
2037#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
2038#define pCAN_MB18_DATA3                ((uint16_t volatile *)CAN_MB18_DATA3) /* Mailbox 18 Data Word 3 [63:48] Register */
2039#define bfin_read_CAN_MB18_DATA3()     bfin_read16(CAN_MB18_DATA3)
2040#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
2041#define pCAN_MB18_LENGTH               ((uint16_t volatile *)CAN_MB18_LENGTH) /* Mailbox 18 Data Length Code Register */
2042#define bfin_read_CAN_MB18_LENGTH()    bfin_read16(CAN_MB18_LENGTH)
2043#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
2044#define pCAN_MB18_TIMESTAMP            ((uint16_t volatile *)CAN_MB18_TIMESTAMP) /* Mailbox 18 Time Stamp Value Register */
2045#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
2046#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
2047#define pCAN_MB18_ID0                  ((uint16_t volatile *)CAN_MB18_ID0) /* Mailbox 18 Identifier Low Register */
2048#define bfin_read_CAN_MB18_ID0()       bfin_read16(CAN_MB18_ID0)
2049#define bfin_write_CAN_MB18_ID0(val)   bfin_write16(CAN_MB18_ID0, val)
2050#define pCAN_MB18_ID1                  ((uint16_t volatile *)CAN_MB18_ID1) /* Mailbox 18 Identifier High Register */
2051#define bfin_read_CAN_MB18_ID1()       bfin_read16(CAN_MB18_ID1)
2052#define bfin_write_CAN_MB18_ID1(val)   bfin_write16(CAN_MB18_ID1, val)
2053#define pCAN_MB19_DATA0                ((uint16_t volatile *)CAN_MB19_DATA0) /* Mailbox 19 Data Word 0 [15:0] Register */
2054#define bfin_read_CAN_MB19_DATA0()     bfin_read16(CAN_MB19_DATA0)
2055#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
2056#define pCAN_MB19_DATA1                ((uint16_t volatile *)CAN_MB19_DATA1) /* Mailbox 19 Data Word 1 [31:16] Register */
2057#define bfin_read_CAN_MB19_DATA1()     bfin_read16(CAN_MB19_DATA1)
2058#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
2059#define pCAN_MB19_DATA2                ((uint16_t volatile *)CAN_MB19_DATA2) /* Mailbox 19 Data Word 2 [47:32] Register */
2060#define bfin_read_CAN_MB19_DATA2()     bfin_read16(CAN_MB19_DATA2)
2061#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
2062#define pCAN_MB19_DATA3                ((uint16_t volatile *)CAN_MB19_DATA3) /* Mailbox 19 Data Word 3 [63:48] Register */
2063#define bfin_read_CAN_MB19_DATA3()     bfin_read16(CAN_MB19_DATA3)
2064#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
2065#define pCAN_MB19_LENGTH               ((uint16_t volatile *)CAN_MB19_LENGTH) /* Mailbox 19 Data Length Code Register */
2066#define bfin_read_CAN_MB19_LENGTH()    bfin_read16(CAN_MB19_LENGTH)
2067#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
2068#define pCAN_MB19_TIMESTAMP            ((uint16_t volatile *)CAN_MB19_TIMESTAMP) /* Mailbox 19 Time Stamp Value Register */
2069#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
2070#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
2071#define pCAN_MB19_ID0                  ((uint16_t volatile *)CAN_MB19_ID0) /* Mailbox 19 Identifier Low Register */
2072#define bfin_read_CAN_MB19_ID0()       bfin_read16(CAN_MB19_ID0)
2073#define bfin_write_CAN_MB19_ID0(val)   bfin_write16(CAN_MB19_ID0, val)
2074#define pCAN_MB19_ID1                  ((uint16_t volatile *)CAN_MB19_ID1) /* Mailbox 19 Identifier High Register */
2075#define bfin_read_CAN_MB19_ID1()       bfin_read16(CAN_MB19_ID1)
2076#define bfin_write_CAN_MB19_ID1(val)   bfin_write16(CAN_MB19_ID1, val)
2077#define pCAN_MB20_DATA0                ((uint16_t volatile *)CAN_MB20_DATA0) /* Mailbox 20 Data Word 0 [15:0] Register */
2078#define bfin_read_CAN_MB20_DATA0()     bfin_read16(CAN_MB20_DATA0)
2079#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
2080#define pCAN_MB20_DATA1                ((uint16_t volatile *)CAN_MB20_DATA1) /* Mailbox 20 Data Word 1 [31:16] Register */
2081#define bfin_read_CAN_MB20_DATA1()     bfin_read16(CAN_MB20_DATA1)
2082#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
2083#define pCAN_MB20_DATA2                ((uint16_t volatile *)CAN_MB20_DATA2) /* Mailbox 20 Data Word 2 [47:32] Register */
2084#define bfin_read_CAN_MB20_DATA2()     bfin_read16(CAN_MB20_DATA2)
2085#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
2086#define pCAN_MB20_DATA3                ((uint16_t volatile *)CAN_MB20_DATA3) /* Mailbox 20 Data Word 3 [63:48] Register */
2087#define bfin_read_CAN_MB20_DATA3()     bfin_read16(CAN_MB20_DATA3)
2088#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
2089#define pCAN_MB20_LENGTH               ((uint16_t volatile *)CAN_MB20_LENGTH) /* Mailbox 20 Data Length Code Register */
2090#define bfin_read_CAN_MB20_LENGTH()    bfin_read16(CAN_MB20_LENGTH)
2091#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
2092#define pCAN_MB20_TIMESTAMP            ((uint16_t volatile *)CAN_MB20_TIMESTAMP) /* Mailbox 20 Time Stamp Value Register */
2093#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
2094#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
2095#define pCAN_MB20_ID0                  ((uint16_t volatile *)CAN_MB20_ID0) /* Mailbox 20 Identifier Low Register */
2096#define bfin_read_CAN_MB20_ID0()       bfin_read16(CAN_MB20_ID0)
2097#define bfin_write_CAN_MB20_ID0(val)   bfin_write16(CAN_MB20_ID0, val)
2098#define pCAN_MB20_ID1                  ((uint16_t volatile *)CAN_MB20_ID1) /* Mailbox 20 Identifier High Register */
2099#define bfin_read_CAN_MB20_ID1()       bfin_read16(CAN_MB20_ID1)
2100#define bfin_write_CAN_MB20_ID1(val)   bfin_write16(CAN_MB20_ID1, val)
2101#define pCAN_MB21_DATA0                ((uint16_t volatile *)CAN_MB21_DATA0) /* Mailbox 21 Data Word 0 [15:0] Register */
2102#define bfin_read_CAN_MB21_DATA0()     bfin_read16(CAN_MB21_DATA0)
2103#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
2104#define pCAN_MB21_DATA1                ((uint16_t volatile *)CAN_MB21_DATA1) /* Mailbox 21 Data Word 1 [31:16] Register */
2105#define bfin_read_CAN_MB21_DATA1()     bfin_read16(CAN_MB21_DATA1)
2106#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
2107#define pCAN_MB21_DATA2                ((uint16_t volatile *)CAN_MB21_DATA2) /* Mailbox 21 Data Word 2 [47:32] Register */
2108#define bfin_read_CAN_MB21_DATA2()     bfin_read16(CAN_MB21_DATA2)
2109#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
2110#define pCAN_MB21_DATA3                ((uint16_t volatile *)CAN_MB21_DATA3) /* Mailbox 21 Data Word 3 [63:48] Register */
2111#define bfin_read_CAN_MB21_DATA3()     bfin_read16(CAN_MB21_DATA3)
2112#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
2113#define pCAN_MB21_LENGTH               ((uint16_t volatile *)CAN_MB21_LENGTH) /* Mailbox 21 Data Length Code Register */
2114#define bfin_read_CAN_MB21_LENGTH()    bfin_read16(CAN_MB21_LENGTH)
2115#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
2116#define pCAN_MB21_TIMESTAMP            ((uint16_t volatile *)CAN_MB21_TIMESTAMP) /* Mailbox 21 Time Stamp Value Register */
2117#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
2118#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
2119#define pCAN_MB21_ID0                  ((uint16_t volatile *)CAN_MB21_ID0) /* Mailbox 21 Identifier Low Register */
2120#define bfin_read_CAN_MB21_ID0()       bfin_read16(CAN_MB21_ID0)
2121#define bfin_write_CAN_MB21_ID0(val)   bfin_write16(CAN_MB21_ID0, val)
2122#define pCAN_MB21_ID1                  ((uint16_t volatile *)CAN_MB21_ID1) /* Mailbox 21 Identifier High Register */
2123#define bfin_read_CAN_MB21_ID1()       bfin_read16(CAN_MB21_ID1)
2124#define bfin_write_CAN_MB21_ID1(val)   bfin_write16(CAN_MB21_ID1, val)
2125#define pCAN_MB22_DATA0                ((uint16_t volatile *)CAN_MB22_DATA0) /* Mailbox 22 Data Word 0 [15:0] Register */
2126#define bfin_read_CAN_MB22_DATA0()     bfin_read16(CAN_MB22_DATA0)
2127#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
2128#define pCAN_MB22_DATA1                ((uint16_t volatile *)CAN_MB22_DATA1) /* Mailbox 22 Data Word 1 [31:16] Register */
2129#define bfin_read_CAN_MB22_DATA1()     bfin_read16(CAN_MB22_DATA1)
2130#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
2131#define pCAN_MB22_DATA2                ((uint16_t volatile *)CAN_MB22_DATA2) /* Mailbox 22 Data Word 2 [47:32] Register */
2132#define bfin_read_CAN_MB22_DATA2()     bfin_read16(CAN_MB22_DATA2)
2133#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
2134#define pCAN_MB22_DATA3                ((uint16_t volatile *)CAN_MB22_DATA3) /* Mailbox 22 Data Word 3 [63:48] Register */
2135#define bfin_read_CAN_MB22_DATA3()     bfin_read16(CAN_MB22_DATA3)
2136#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
2137#define pCAN_MB22_LENGTH               ((uint16_t volatile *)CAN_MB22_LENGTH) /* Mailbox 22 Data Length Code Register */
2138#define bfin_read_CAN_MB22_LENGTH()    bfin_read16(CAN_MB22_LENGTH)
2139#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
2140#define pCAN_MB22_TIMESTAMP            ((uint16_t volatile *)CAN_MB22_TIMESTAMP) /* Mailbox 22 Time Stamp Value Register */
2141#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
2142#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
2143#define pCAN_MB22_ID0                  ((uint16_t volatile *)CAN_MB22_ID0) /* Mailbox 22 Identifier Low Register */
2144#define bfin_read_CAN_MB22_ID0()       bfin_read16(CAN_MB22_ID0)
2145#define bfin_write_CAN_MB22_ID0(val)   bfin_write16(CAN_MB22_ID0, val)
2146#define pCAN_MB22_ID1                  ((uint16_t volatile *)CAN_MB22_ID1) /* Mailbox 22 Identifier High Register */
2147#define bfin_read_CAN_MB22_ID1()       bfin_read16(CAN_MB22_ID1)
2148#define bfin_write_CAN_MB22_ID1(val)   bfin_write16(CAN_MB22_ID1, val)
2149#define pCAN_MB23_DATA0                ((uint16_t volatile *)CAN_MB23_DATA0) /* Mailbox 23 Data Word 0 [15:0] Register */
2150#define bfin_read_CAN_MB23_DATA0()     bfin_read16(CAN_MB23_DATA0)
2151#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
2152#define pCAN_MB23_DATA1                ((uint16_t volatile *)CAN_MB23_DATA1) /* Mailbox 23 Data Word 1 [31:16] Register */
2153#define bfin_read_CAN_MB23_DATA1()     bfin_read16(CAN_MB23_DATA1)
2154#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
2155#define pCAN_MB23_DATA2                ((uint16_t volatile *)CAN_MB23_DATA2) /* Mailbox 23 Data Word 2 [47:32] Register */
2156#define bfin_read_CAN_MB23_DATA2()     bfin_read16(CAN_MB23_DATA2)
2157#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
2158#define pCAN_MB23_DATA3                ((uint16_t volatile *)CAN_MB23_DATA3) /* Mailbox 23 Data Word 3 [63:48] Register */
2159#define bfin_read_CAN_MB23_DATA3()     bfin_read16(CAN_MB23_DATA3)
2160#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
2161#define pCAN_MB23_LENGTH               ((uint16_t volatile *)CAN_MB23_LENGTH) /* Mailbox 23 Data Length Code Register */
2162#define bfin_read_CAN_MB23_LENGTH()    bfin_read16(CAN_MB23_LENGTH)
2163#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
2164#define pCAN_MB23_TIMESTAMP            ((uint16_t volatile *)CAN_MB23_TIMESTAMP) /* Mailbox 23 Time Stamp Value Register */
2165#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
2166#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
2167#define pCAN_MB23_ID0                  ((uint16_t volatile *)CAN_MB23_ID0) /* Mailbox 23 Identifier Low Register */
2168#define bfin_read_CAN_MB23_ID0()       bfin_read16(CAN_MB23_ID0)
2169#define bfin_write_CAN_MB23_ID0(val)   bfin_write16(CAN_MB23_ID0, val)
2170#define pCAN_MB23_ID1                  ((uint16_t volatile *)CAN_MB23_ID1) /* Mailbox 23 Identifier High Register */
2171#define bfin_read_CAN_MB23_ID1()       bfin_read16(CAN_MB23_ID1)
2172#define bfin_write_CAN_MB23_ID1(val)   bfin_write16(CAN_MB23_ID1, val)
2173#define pCAN_MB24_DATA0                ((uint16_t volatile *)CAN_MB24_DATA0) /* Mailbox 24 Data Word 0 [15:0] Register */
2174#define bfin_read_CAN_MB24_DATA0()     bfin_read16(CAN_MB24_DATA0)
2175#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
2176#define pCAN_MB24_DATA1                ((uint16_t volatile *)CAN_MB24_DATA1) /* Mailbox 24 Data Word 1 [31:16] Register */
2177#define bfin_read_CAN_MB24_DATA1()     bfin_read16(CAN_MB24_DATA1)
2178#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
2179#define pCAN_MB24_DATA2                ((uint16_t volatile *)CAN_MB24_DATA2) /* Mailbox 24 Data Word 2 [47:32] Register */
2180#define bfin_read_CAN_MB24_DATA2()     bfin_read16(CAN_MB24_DATA2)
2181#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
2182#define pCAN_MB24_DATA3                ((uint16_t volatile *)CAN_MB24_DATA3) /* Mailbox 24 Data Word 3 [63:48] Register */
2183#define bfin_read_CAN_MB24_DATA3()     bfin_read16(CAN_MB24_DATA3)
2184#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
2185#define pCAN_MB24_LENGTH               ((uint16_t volatile *)CAN_MB24_LENGTH) /* Mailbox 24 Data Length Code Register */
2186#define bfin_read_CAN_MB24_LENGTH()    bfin_read16(CAN_MB24_LENGTH)
2187#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
2188#define pCAN_MB24_TIMESTAMP            ((uint16_t volatile *)CAN_MB24_TIMESTAMP) /* Mailbox 24 Time Stamp Value Register */
2189#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
2190#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
2191#define pCAN_MB24_ID0                  ((uint16_t volatile *)CAN_MB24_ID0) /* Mailbox 24 Identifier Low Register */
2192#define bfin_read_CAN_MB24_ID0()       bfin_read16(CAN_MB24_ID0)
2193#define bfin_write_CAN_MB24_ID0(val)   bfin_write16(CAN_MB24_ID0, val)
2194#define pCAN_MB24_ID1                  ((uint16_t volatile *)CAN_MB24_ID1) /* Mailbox 24 Identifier High Register */
2195#define bfin_read_CAN_MB24_ID1()       bfin_read16(CAN_MB24_ID1)
2196#define bfin_write_CAN_MB24_ID1(val)   bfin_write16(CAN_MB24_ID1, val)
2197#define pCAN_MB25_DATA0                ((uint16_t volatile *)CAN_MB25_DATA0) /* Mailbox 25 Data Word 0 [15:0] Register */
2198#define bfin_read_CAN_MB25_DATA0()     bfin_read16(CAN_MB25_DATA0)
2199#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
2200#define pCAN_MB25_DATA1                ((uint16_t volatile *)CAN_MB25_DATA1) /* Mailbox 25 Data Word 1 [31:16] Register */
2201#define bfin_read_CAN_MB25_DATA1()     bfin_read16(CAN_MB25_DATA1)
2202#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
2203#define pCAN_MB25_DATA2                ((uint16_t volatile *)CAN_MB25_DATA2) /* Mailbox 25 Data Word 2 [47:32] Register */
2204#define bfin_read_CAN_MB25_DATA2()     bfin_read16(CAN_MB25_DATA2)
2205#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
2206#define pCAN_MB25_DATA3                ((uint16_t volatile *)CAN_MB25_DATA3) /* Mailbox 25 Data Word 3 [63:48] Register */
2207#define bfin_read_CAN_MB25_DATA3()     bfin_read16(CAN_MB25_DATA3)
2208#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
2209#define pCAN_MB25_LENGTH               ((uint16_t volatile *)CAN_MB25_LENGTH) /* Mailbox 25 Data Length Code Register */
2210#define bfin_read_CAN_MB25_LENGTH()    bfin_read16(CAN_MB25_LENGTH)
2211#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
2212#define pCAN_MB25_TIMESTAMP            ((uint16_t volatile *)CAN_MB25_TIMESTAMP) /* Mailbox 25 Time Stamp Value Register */
2213#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
2214#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
2215#define pCAN_MB25_ID0                  ((uint16_t volatile *)CAN_MB25_ID0) /* Mailbox 25 Identifier Low Register */
2216#define bfin_read_CAN_MB25_ID0()       bfin_read16(CAN_MB25_ID0)
2217#define bfin_write_CAN_MB25_ID0(val)   bfin_write16(CAN_MB25_ID0, val)
2218#define pCAN_MB25_ID1                  ((uint16_t volatile *)CAN_MB25_ID1) /* Mailbox 25 Identifier High Register */
2219#define bfin_read_CAN_MB25_ID1()       bfin_read16(CAN_MB25_ID1)
2220#define bfin_write_CAN_MB25_ID1(val)   bfin_write16(CAN_MB25_ID1, val)
2221#define pCAN_MB26_DATA0                ((uint16_t volatile *)CAN_MB26_DATA0) /* Mailbox 26 Data Word 0 [15:0] Register */
2222#define bfin_read_CAN_MB26_DATA0()     bfin_read16(CAN_MB26_DATA0)
2223#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
2224#define pCAN_MB26_DATA1                ((uint16_t volatile *)CAN_MB26_DATA1) /* Mailbox 26 Data Word 1 [31:16] Register */
2225#define bfin_read_CAN_MB26_DATA1()     bfin_read16(CAN_MB26_DATA1)
2226#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
2227#define pCAN_MB26_DATA2                ((uint16_t volatile *)CAN_MB26_DATA2) /* Mailbox 26 Data Word 2 [47:32] Register */
2228#define bfin_read_CAN_MB26_DATA2()     bfin_read16(CAN_MB26_DATA2)
2229#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
2230#define pCAN_MB26_DATA3                ((uint16_t volatile *)CAN_MB26_DATA3) /* Mailbox 26 Data Word 3 [63:48] Register */
2231#define bfin_read_CAN_MB26_DATA3()     bfin_read16(CAN_MB26_DATA3)
2232#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
2233#define pCAN_MB26_LENGTH               ((uint16_t volatile *)CAN_MB26_LENGTH) /* Mailbox 26 Data Length Code Register */
2234#define bfin_read_CAN_MB26_LENGTH()    bfin_read16(CAN_MB26_LENGTH)
2235#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
2236#define pCAN_MB26_TIMESTAMP            ((uint16_t volatile *)CAN_MB26_TIMESTAMP) /* Mailbox 26 Time Stamp Value Register */
2237#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
2238#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
2239#define pCAN_MB26_ID0                  ((uint16_t volatile *)CAN_MB26_ID0) /* Mailbox 26 Identifier Low Register */
2240#define bfin_read_CAN_MB26_ID0()       bfin_read16(CAN_MB26_ID0)
2241#define bfin_write_CAN_MB26_ID0(val)   bfin_write16(CAN_MB26_ID0, val)
2242#define pCAN_MB26_ID1                  ((uint16_t volatile *)CAN_MB26_ID1) /* Mailbox 26 Identifier High Register */
2243#define bfin_read_CAN_MB26_ID1()       bfin_read16(CAN_MB26_ID1)
2244#define bfin_write_CAN_MB26_ID1(val)   bfin_write16(CAN_MB26_ID1, val)
2245#define pCAN_MB27_DATA0                ((uint16_t volatile *)CAN_MB27_DATA0) /* Mailbox 27 Data Word 0 [15:0] Register */
2246#define bfin_read_CAN_MB27_DATA0()     bfin_read16(CAN_MB27_DATA0)
2247#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
2248#define pCAN_MB27_DATA1                ((uint16_t volatile *)CAN_MB27_DATA1) /* Mailbox 27 Data Word 1 [31:16] Register */
2249#define bfin_read_CAN_MB27_DATA1()     bfin_read16(CAN_MB27_DATA1)
2250#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
2251#define pCAN_MB27_DATA2                ((uint16_t volatile *)CAN_MB27_DATA2) /* Mailbox 27 Data Word 2 [47:32] Register */
2252#define bfin_read_CAN_MB27_DATA2()     bfin_read16(CAN_MB27_DATA2)
2253#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
2254#define pCAN_MB27_DATA3                ((uint16_t volatile *)CAN_MB27_DATA3) /* Mailbox 27 Data Word 3 [63:48] Register */
2255#define bfin_read_CAN_MB27_DATA3()     bfin_read16(CAN_MB27_DATA3)
2256#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
2257#define pCAN_MB27_LENGTH               ((uint16_t volatile *)CAN_MB27_LENGTH) /* Mailbox 27 Data Length Code Register */
2258#define bfin_read_CAN_MB27_LENGTH()    bfin_read16(CAN_MB27_LENGTH)
2259#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
2260#define pCAN_MB27_TIMESTAMP            ((uint16_t volatile *)CAN_MB27_TIMESTAMP) /* Mailbox 27 Time Stamp Value Register */
2261#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
2262#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
2263#define pCAN_MB27_ID0                  ((uint16_t volatile *)CAN_MB27_ID0) /* Mailbox 27 Identifier Low Register */
2264#define bfin_read_CAN_MB27_ID0()       bfin_read16(CAN_MB27_ID0)
2265#define bfin_write_CAN_MB27_ID0(val)   bfin_write16(CAN_MB27_ID0, val)
2266#define pCAN_MB27_ID1                  ((uint16_t volatile *)CAN_MB27_ID1) /* Mailbox 27 Identifier High Register */
2267#define bfin_read_CAN_MB27_ID1()       bfin_read16(CAN_MB27_ID1)
2268#define bfin_write_CAN_MB27_ID1(val)   bfin_write16(CAN_MB27_ID1, val)
2269#define pCAN_MB28_DATA0                ((uint16_t volatile *)CAN_MB28_DATA0) /* Mailbox 28 Data Word 0 [15:0] Register */
2270#define bfin_read_CAN_MB28_DATA0()     bfin_read16(CAN_MB28_DATA0)
2271#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
2272#define pCAN_MB28_DATA1                ((uint16_t volatile *)CAN_MB28_DATA1) /* Mailbox 28 Data Word 1 [31:16] Register */
2273#define bfin_read_CAN_MB28_DATA1()     bfin_read16(CAN_MB28_DATA1)
2274#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
2275#define pCAN_MB28_DATA2                ((uint16_t volatile *)CAN_MB28_DATA2) /* Mailbox 28 Data Word 2 [47:32] Register */
2276#define bfin_read_CAN_MB28_DATA2()     bfin_read16(CAN_MB28_DATA2)
2277#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
2278#define pCAN_MB28_DATA3                ((uint16_t volatile *)CAN_MB28_DATA3) /* Mailbox 28 Data Word 3 [63:48] Register */
2279#define bfin_read_CAN_MB28_DATA3()     bfin_read16(CAN_MB28_DATA3)
2280#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
2281#define pCAN_MB28_LENGTH               ((uint16_t volatile *)CAN_MB28_LENGTH) /* Mailbox 28 Data Length Code Register */
2282#define bfin_read_CAN_MB28_LENGTH()    bfin_read16(CAN_MB28_LENGTH)
2283#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
2284#define pCAN_MB28_TIMESTAMP            ((uint16_t volatile *)CAN_MB28_TIMESTAMP) /* Mailbox 28 Time Stamp Value Register */
2285#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
2286#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
2287#define pCAN_MB28_ID0                  ((uint16_t volatile *)CAN_MB28_ID0) /* Mailbox 28 Identifier Low Register */
2288#define bfin_read_CAN_MB28_ID0()       bfin_read16(CAN_MB28_ID0)
2289#define bfin_write_CAN_MB28_ID0(val)   bfin_write16(CAN_MB28_ID0, val)
2290#define pCAN_MB28_ID1                  ((uint16_t volatile *)CAN_MB28_ID1) /* Mailbox 28 Identifier High Register */
2291#define bfin_read_CAN_MB28_ID1()       bfin_read16(CAN_MB28_ID1)
2292#define bfin_write_CAN_MB28_ID1(val)   bfin_write16(CAN_MB28_ID1, val)
2293#define pCAN_MB29_DATA0                ((uint16_t volatile *)CAN_MB29_DATA0) /* Mailbox 29 Data Word 0 [15:0] Register */
2294#define bfin_read_CAN_MB29_DATA0()     bfin_read16(CAN_MB29_DATA0)
2295#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
2296#define pCAN_MB29_DATA1                ((uint16_t volatile *)CAN_MB29_DATA1) /* Mailbox 29 Data Word 1 [31:16] Register */
2297#define bfin_read_CAN_MB29_DATA1()     bfin_read16(CAN_MB29_DATA1)
2298#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
2299#define pCAN_MB29_DATA2                ((uint16_t volatile *)CAN_MB29_DATA2) /* Mailbox 29 Data Word 2 [47:32] Register */
2300#define bfin_read_CAN_MB29_DATA2()     bfin_read16(CAN_MB29_DATA2)
2301#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
2302#define pCAN_MB29_DATA3                ((uint16_t volatile *)CAN_MB29_DATA3) /* Mailbox 29 Data Word 3 [63:48] Register */
2303#define bfin_read_CAN_MB29_DATA3()     bfin_read16(CAN_MB29_DATA3)
2304#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
2305#define pCAN_MB29_LENGTH               ((uint16_t volatile *)CAN_MB29_LENGTH) /* Mailbox 29 Data Length Code Register */
2306#define bfin_read_CAN_MB29_LENGTH()    bfin_read16(CAN_MB29_LENGTH)
2307#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
2308#define pCAN_MB29_TIMESTAMP            ((uint16_t volatile *)CAN_MB29_TIMESTAMP) /* Mailbox 29 Time Stamp Value Register */
2309#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
2310#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
2311#define pCAN_MB29_ID0                  ((uint16_t volatile *)CAN_MB29_ID0) /* Mailbox 29 Identifier Low Register */
2312#define bfin_read_CAN_MB29_ID0()       bfin_read16(CAN_MB29_ID0)
2313#define bfin_write_CAN_MB29_ID0(val)   bfin_write16(CAN_MB29_ID0, val)
2314#define pCAN_MB29_ID1                  ((uint16_t volatile *)CAN_MB29_ID1) /* Mailbox 29 Identifier High Register */
2315#define bfin_read_CAN_MB29_ID1()       bfin_read16(CAN_MB29_ID1)
2316#define bfin_write_CAN_MB29_ID1(val)   bfin_write16(CAN_MB29_ID1, val)
2317#define pCAN_MB30_DATA0                ((uint16_t volatile *)CAN_MB30_DATA0) /* Mailbox 30 Data Word 0 [15:0] Register */
2318#define bfin_read_CAN_MB30_DATA0()     bfin_read16(CAN_MB30_DATA0)
2319#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
2320#define pCAN_MB30_DATA1                ((uint16_t volatile *)CAN_MB30_DATA1) /* Mailbox 30 Data Word 1 [31:16] Register */
2321#define bfin_read_CAN_MB30_DATA1()     bfin_read16(CAN_MB30_DATA1)
2322#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
2323#define pCAN_MB30_DATA2                ((uint16_t volatile *)CAN_MB30_DATA2) /* Mailbox 30 Data Word 2 [47:32] Register */
2324#define bfin_read_CAN_MB30_DATA2()     bfin_read16(CAN_MB30_DATA2)
2325#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
2326#define pCAN_MB30_DATA3                ((uint16_t volatile *)CAN_MB30_DATA3) /* Mailbox 30 Data Word 3 [63:48] Register */
2327#define bfin_read_CAN_MB30_DATA3()     bfin_read16(CAN_MB30_DATA3)
2328#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
2329#define pCAN_MB30_LENGTH               ((uint16_t volatile *)CAN_MB30_LENGTH) /* Mailbox 30 Data Length Code Register */
2330#define bfin_read_CAN_MB30_LENGTH()    bfin_read16(CAN_MB30_LENGTH)
2331#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
2332#define pCAN_MB30_TIMESTAMP            ((uint16_t volatile *)CAN_MB30_TIMESTAMP) /* Mailbox 30 Time Stamp Value Register */
2333#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
2334#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
2335#define pCAN_MB30_ID0                  ((uint16_t volatile *)CAN_MB30_ID0) /* Mailbox 30 Identifier Low Register */
2336#define bfin_read_CAN_MB30_ID0()       bfin_read16(CAN_MB30_ID0)
2337#define bfin_write_CAN_MB30_ID0(val)   bfin_write16(CAN_MB30_ID0, val)
2338#define pCAN_MB30_ID1                  ((uint16_t volatile *)CAN_MB30_ID1) /* Mailbox 30 Identifier High Register */
2339#define bfin_read_CAN_MB30_ID1()       bfin_read16(CAN_MB30_ID1)
2340#define bfin_write_CAN_MB30_ID1(val)   bfin_write16(CAN_MB30_ID1, val)
2341#define pCAN_MB31_DATA0                ((uint16_t volatile *)CAN_MB31_DATA0) /* Mailbox 31 Data Word 0 [15:0] Register */
2342#define bfin_read_CAN_MB31_DATA0()     bfin_read16(CAN_MB31_DATA0)
2343#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
2344#define pCAN_MB31_DATA1                ((uint16_t volatile *)CAN_MB31_DATA1) /* Mailbox 31 Data Word 1 [31:16] Register */
2345#define bfin_read_CAN_MB31_DATA1()     bfin_read16(CAN_MB31_DATA1)
2346#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
2347#define pCAN_MB31_DATA2                ((uint16_t volatile *)CAN_MB31_DATA2) /* Mailbox 31 Data Word 2 [47:32] Register */
2348#define bfin_read_CAN_MB31_DATA2()     bfin_read16(CAN_MB31_DATA2)
2349#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
2350#define pCAN_MB31_DATA3                ((uint16_t volatile *)CAN_MB31_DATA3) /* Mailbox 31 Data Word 3 [63:48] Register */
2351#define bfin_read_CAN_MB31_DATA3()     bfin_read16(CAN_MB31_DATA3)
2352#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
2353#define pCAN_MB31_LENGTH               ((uint16_t volatile *)CAN_MB31_LENGTH) /* Mailbox 31 Data Length Code Register */
2354#define bfin_read_CAN_MB31_LENGTH()    bfin_read16(CAN_MB31_LENGTH)
2355#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
2356#define pCAN_MB31_TIMESTAMP            ((uint16_t volatile *)CAN_MB31_TIMESTAMP) /* Mailbox 31 Time Stamp Value Register */
2357#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
2358#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
2359#define pCAN_MB31_ID0                  ((uint16_t volatile *)CAN_MB31_ID0) /* Mailbox 31 Identifier Low Register */
2360#define bfin_read_CAN_MB31_ID0()       bfin_read16(CAN_MB31_ID0)
2361#define bfin_write_CAN_MB31_ID0(val)   bfin_write16(CAN_MB31_ID0, val)
2362#define pCAN_MB31_ID1                  ((uint16_t volatile *)CAN_MB31_ID1) /* Mailbox 31 Identifier High Register */
2363#define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
2364#define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
2365#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
2366#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
2367#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
2368#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
2369#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
2370#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
2371#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
2372#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
2373#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
2374#define pPORT_MUX                      ((uint16_t volatile *)PORT_MUX) /* Port Multiplexer Control Register */
2375#define bfin_read_PORT_MUX()           bfin_read16(PORT_MUX)
2376#define bfin_write_PORT_MUX(val)       bfin_write16(PORT_MUX, val)
2377#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
2378#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
2379#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
2380#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
2381#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
2382#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
2383#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
2384#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
2385#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
2386#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
2387#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
2388#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
2389#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
2390#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
2391#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
2392#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
2393#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
2394#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
2395#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
2396#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
2397#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
2398#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
2399#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
2400#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
2401#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
2402#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
2403#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
2404#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
2405#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
2406#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
2407#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
2408#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
2409#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
2410#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
2411#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
2412#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
2413#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
2414#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
2415#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
2416#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
2417#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
2418#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
2419#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
2420#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
2421#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
2422#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
2423#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
2424#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
2425#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* L1 Data Memory Controller Register */
2426#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
2427#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
2428#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR)
2429#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
2430#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
2431#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
2432#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
2433#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
2434#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
2435#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
2436#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
2437#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
2438#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
2439#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
2440#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
2441#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
2442#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
2443#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
2444#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
2445#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
2446#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
2447#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
2448#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
2449#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
2450#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
2451#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
2452#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
2453#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
2454#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
2455#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
2456#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
2457#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
2458#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
2459#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
2460#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
2461#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
2462#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
2463#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
2464#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
2465#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
2466#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
2467#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
2468#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
2469#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
2470#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
2471#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
2472#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
2473#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
2474#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
2475#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
2476#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
2477#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
2478#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
2479#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
2480#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
2481#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
2482#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
2483#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
2484#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
2485#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
2486#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
2487#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
2488#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
2489#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
2490#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
2491#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
2492#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
2493#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
2494#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
2495#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
2496#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
2497#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
2498#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
2499#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
2500#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
2501#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
2502#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
2503#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
2504#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
2505#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
2506#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
2507#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
2508#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
2509#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
2510#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
2511#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
2512#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
2513#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
2514#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
2515#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
2516#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
2517#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
2518#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
2519#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
2520#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
2521#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
2522#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
2523#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
2524#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
2525#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
2526#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
2527#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
2528#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
2529#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
2530#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
2531#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
2532#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
2533#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
2534#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
2535#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
2536#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
2537#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
2538#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
2539#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS)
2540#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
2541#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
2542#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR)
2543#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
2544#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
2545#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
2546#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
2547#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
2548#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
2549#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
2550#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
2551#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
2552#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
2553#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
2554#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
2555#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
2556#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
2557#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
2558#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
2559#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
2560#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
2561#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
2562#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
2563#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
2564#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
2565#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
2566#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
2567#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
2568#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
2569#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
2570#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
2571#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
2572#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
2573#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
2574#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
2575#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
2576#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
2577#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
2578#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
2579#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
2580#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
2581#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
2582#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
2583#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
2584#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
2585#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
2586#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
2587#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
2588#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
2589#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
2590#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
2591#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
2592#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
2593#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
2594#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
2595#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
2596#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
2597#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
2598#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
2599#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
2600#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
2601#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
2602#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
2603#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
2604#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
2605#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
2606#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
2607#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
2608#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
2609#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
2610#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
2611#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
2612#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
2613#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
2614#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
2615#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
2616#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
2617#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
2618#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
2619#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
2620#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
2621#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
2622#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
2623#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
2624#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
2625#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
2626#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
2627#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
2628#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
2629#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
2630#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
2631#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
2632#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
2633#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
2634#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
2635#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
2636#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
2637#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
2638#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
2639#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
2640#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
2641#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
2642#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
2643#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
2644#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
2645#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
2646#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
2647#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
2648#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
2649#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
2650#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
2651#define bfin_read_EVT0()               bfin_readPTR(EVT0)
2652#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
2653#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
2654#define bfin_read_EVT1()               bfin_readPTR(EVT1)
2655#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
2656#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
2657#define bfin_read_EVT2()               bfin_readPTR(EVT2)
2658#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
2659#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
2660#define bfin_read_EVT3()               bfin_readPTR(EVT3)
2661#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
2662#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
2663#define bfin_read_EVT4()               bfin_readPTR(EVT4)
2664#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
2665#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
2666#define bfin_read_EVT5()               bfin_readPTR(EVT5)
2667#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
2668#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
2669#define bfin_read_EVT6()               bfin_readPTR(EVT6)
2670#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
2671#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
2672#define bfin_read_EVT7()               bfin_readPTR(EVT7)
2673#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
2674#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
2675#define bfin_read_EVT8()               bfin_readPTR(EVT8)
2676#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
2677#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
2678#define bfin_read_EVT9()               bfin_readPTR(EVT9)
2679#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
2680#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
2681#define bfin_read_EVT10()              bfin_readPTR(EVT10)
2682#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
2683#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
2684#define bfin_read_EVT11()              bfin_readPTR(EVT11)
2685#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
2686#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
2687#define bfin_read_EVT12()              bfin_readPTR(EVT12)
2688#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
2689#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
2690#define bfin_read_EVT13()              bfin_readPTR(EVT13)
2691#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
2692#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
2693#define bfin_read_EVT14()              bfin_readPTR(EVT14)
2694#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
2695#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
2696#define bfin_read_EVT15()              bfin_readPTR(EVT15)
2697#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
2698#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
2699#define bfin_read_ILAT()               bfin_read32(ILAT)
2700#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
2701#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
2702#define bfin_read_IMASK()              bfin_read32(IMASK)
2703#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
2704#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
2705#define bfin_read_IPEND()              bfin_read32(IPEND)
2706#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
2707#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
2708#define bfin_read_IPRIO()              bfin_read32(IPRIO)
2709#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
2710#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
2711#define bfin_read_TCNTL()              bfin_read32(TCNTL)
2712#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
2713#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
2714#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
2715#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
2716#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
2717#define bfin_read_TSCALE()             bfin_read32(TSCALE)
2718#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
2719#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
2720#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
2721#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
2722#define pCHIPID                        ((uint32_t volatile *)CHIPID)
2723#define bfin_read_CHIPID()             bfin_read32(CHIPID)
2724#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
2725#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
2726#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
2727#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
2728#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
2729#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
2730#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
2731#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
2732#define bfin_read_TBUF()               bfin_readPTR(TBUF)
2733#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
2734#define pPFCTL                         ((uint32_t volatile *)PFCTL)
2735#define bfin_read_PFCTL()              bfin_read32(PFCTL)
2736#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
2737#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
2738#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
2739#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
2740#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
2741#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
2742#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
2743#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
2744#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
2745#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
2746#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
2747#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
2748#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
2749
2750#endif /* __BFIN_CDEF_ADSP_EDN_BF534_extended__ */
2751