1/* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-def-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6#ifndef __BFIN_DEF_ADSP_BF536_proc__ 7#define __BFIN_DEF_ADSP_BF536_proc__ 8 9#include "../mach-common/ADSP-EDN-core_def.h" 10 11#include "ADSP-EDN-BF534-extended_def.h" 12 13#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ 14#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ 15#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ 16#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ 17#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ 18#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ 19#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ 20#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ 21#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ 22#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ 23#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ 24#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ 25#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ 26#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ 27#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ 28#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ 29#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ 30#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ 31#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ 32#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ 33#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ 34#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ 35#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ 36#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ 37#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ 38#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ 39#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ 40#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ 41#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ 42#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ 43#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ 44#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ 45#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ 46#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ 47#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ 48#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ 49#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ 50#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ 51#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ 52#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ 53#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ 54#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ 55#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ 56#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ 57#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ 58#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ 59#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ 60#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ 61#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ 62#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ 63#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ 64#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ 65#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ 66#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ 67#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ 68#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ 69#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ 70#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ 71#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ 72#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ 73#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ 74#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ 75#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ 76#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ 77#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ 78#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ 79#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ 80#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ 81#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ 82#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ 83#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ 84#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ 85#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ 86#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ 87#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ 88#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ 89#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ 90#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ 91#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ 92#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ 93#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) 94#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) 95#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ 96#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) 97#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) 98#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ 99#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) 100#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) 101 102#endif /* __BFIN_DEF_ADSP_BF536_proc__ */ 103