LXR uboot/arch/blackfin/include/asm/mach-bf548/BF549

   1/* DO NOT EDIT THIS FILE
   2 * Automatically generated by generate-cdef-headers.xsl
   3 * DO NOT EDIT THIS FILE
   4 */
   5
   6#ifndef __BFIN_CDEF_ADSP_BF549_proc__
   7#define __BFIN_CDEF_ADSP_BF549_proc__
   8
   9#include "../mach-common/ADSP-EDN-core_cdef.h"
  10
  11#include "ADSP-EDN-BF549-extended_cdef.h"
  12
  13#define pCHIPID                        ((uint32_t volatile *)CHIPID)
  14#define bfin_read_CHIPID()             bfin_read32(CHIPID)
  15#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
  16#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
  17#define bfin_read_SWRST()              bfin_read16(SWRST)
  18#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
  19#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
  20#define bfin_read_SYSCR()              bfin_read16(SYSCR)
  21#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
  22#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
  23#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
  24#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
  25#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
  26#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
  27#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
  28#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
  29#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
  30#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
  31#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
  32#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
  33#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
  34#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
  35#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
  36#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
  37#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
  38#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
  39#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
  40#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
  41#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
  42#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
  43#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
  44#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
  45#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
  46#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
  47#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
  48#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
  49#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
  50#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
  51#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
  52#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
  53#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
  54#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
  55#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
  56#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
  57#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
  58#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
  59#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
  60#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
  61#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
  62#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
  63#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
  64#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
  65#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
  66#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
  67#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
  68#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
  69#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
  70#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
  71#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
  72#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
  73#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
  74#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
  75#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
  76#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
  77#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
  78#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
  79#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
  80#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
  81#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
  82#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
  83#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
  84#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
  85#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
  86#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
  87#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
  88#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
  89#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
  90#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
  91#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
  92#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
  93#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
  94#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
  95#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
  96#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
  97#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
  98#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
  99#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
 100#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 101#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 102#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
 103#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 104#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 105#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
 106#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 107#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 108#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
 109#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 110#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 111#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
 112#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 113#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 114#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
 115#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 116#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 117#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
 118#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 119#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 120#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
 121#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 122#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 123#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
 124#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 125#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 126#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
 127#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 128#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 129#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
 130#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 131#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 132#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
 133#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 134#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 135#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
 136#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 137#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 138#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
 139#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 140#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 141#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
 142#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 143#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 144#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
 145#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 146#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 147#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
 148#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 149#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 150#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
 151#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 152#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 153#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
 154#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 155#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 156#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
 157#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 158#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 159#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
 160#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 161#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 162#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
 163#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 164#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 165#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
 166#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 167#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 168#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
 169#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 170#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 171#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
 172#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 173#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 174#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
 175#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 176#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 177#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
 178#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 179#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 180#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
 181#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 182#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 183#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
 184#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 185#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 186#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
 187#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 188#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 189#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
 190#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 191#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 192#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
 193#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 194#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 195#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
 196#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 197#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 198#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
 199#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 200#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 201#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
 202#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 203#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 204#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
 205#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 206#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 207#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
 208#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 209#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 210#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
 211#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 212#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 213#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
 214#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 215#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 216#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
 217#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 218#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 219#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
 220#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 221#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 222#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
 223#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 224#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 225#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
 226#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 227#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 228#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
 229#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 230#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 231#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
 232#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 233#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 234#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
 235#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 236#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 237#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
 238#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 239#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 240#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
 241#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 242#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 243#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
 244#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 245#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 246#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
 247#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 248#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 249#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
 250#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 251#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 252#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
 253#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 254#define bfin_read_EVT0()               bfin_readPTR(EVT0)
 255#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
 256#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 257#define bfin_read_EVT1()               bfin_readPTR(EVT1)
 258#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
 259#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 260#define bfin_read_EVT2()               bfin_readPTR(EVT2)
 261#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
 262#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 263#define bfin_read_EVT3()               bfin_readPTR(EVT3)
 264#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
 265#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 266#define bfin_read_EVT4()               bfin_readPTR(EVT4)
 267#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
 268#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 269#define bfin_read_EVT5()               bfin_readPTR(EVT5)
 270#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
 271#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 272#define bfin_read_EVT6()               bfin_readPTR(EVT6)
 273#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
 274#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 275#define bfin_read_EVT7()               bfin_readPTR(EVT7)
 276#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
 277#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 278#define bfin_read_EVT8()               bfin_readPTR(EVT8)
 279#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
 280#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 281#define bfin_read_EVT9()               bfin_readPTR(EVT9)
 282#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
 283#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 284#define bfin_read_EVT10()              bfin_readPTR(EVT10)
 285#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
 286#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 287#define bfin_read_EVT11()              bfin_readPTR(EVT11)
 288#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
 289#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 290#define bfin_read_EVT12()              bfin_readPTR(EVT12)
 291#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
 292#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 293#define bfin_read_EVT13()              bfin_readPTR(EVT13)
 294#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
 295#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 296#define bfin_read_EVT14()              bfin_readPTR(EVT14)
 297#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
 298#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 299#define bfin_read_EVT15()              bfin_readPTR(EVT15)
 300#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
 301#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 302#define bfin_read_ILAT()               bfin_read32(ILAT)
 303#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
 304#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 305#define bfin_read_IMASK()              bfin_read32(IMASK)
 306#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
 307#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 308#define bfin_read_IPEND()              bfin_read32(IPEND)
 309#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
 310#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 311#define bfin_read_IPRIO()              bfin_read32(IPRIO)
 312#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
 313#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 314#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 315#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
 316#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 317#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 318#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
 319#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 320#define bfin_read_TBUF()               bfin_readPTR(TBUF)
 321#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
 322
 323#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
 324