LXR uboot/board/adder/adder.c

   1/*
   2 * Copyright (C) 2004-2005 Arabella Software Ltd.
   3 * Yuli Barcohen <yuli@arabellasw.com>
   4 *
   5 * Support for Analogue&Micro Adder boards family.
   6 * Tested on AdderII and Adder87x.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <mpc8xx.h>
  29#if defined(CONFIG_OF_LIBFDT)
  30        #include <libfdt.h>
  31#endif
  32
  33/*
  34 * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
  35 *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
  36 * Minimal CPU frequency is 40MHz.
  37 */
  38static uint sdram_table[] = {
  39        /* Single read  (offset 0x00 in UPM RAM) */
  40        0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
  41        0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
  42
  43        /* Burst read   (offset 0x08 in UPM RAM) */
  44        0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
  45        0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
  46        0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
  47        0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
  48
  49        /* Single write (offset 0x18 in UPM RAM) */
  50        0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
  51        0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  52
  53        /* Burst write  (offset 0x20 in UPM RAM) */
  54        0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
  55        0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
  56        0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  57        0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  58
  59        /* Refresh      (offset 0x30 in UPM RAM) */
  60        0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  61        0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
  62        0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
  63
  64        /* Exception    (offset 0x3C in UPM RAM) */
  65        0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
  66};
  67
  68phys_size_t initdram (int board_type)
  69{
  70        long int msize;
  71        volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
  72        volatile memctl8xx_t *memctl = &immap->im_memctl;
  73
  74        upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
  75
  76        /* Configure SDRAM refresh */
  77        memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
  78
  79        memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
  80        udelay(200);
  81
  82        /* Run precharge from location 0x15 */
  83        memctl->memc_mar = 0x0;
  84        memctl->memc_mcr = 0x80002115;
  85        udelay(200);
  86
  87        /* Run 8 refresh cycles */
  88        memctl->memc_mcr = 0x80002830;
  89        udelay(200);
  90
  91        /* Run MRS pattern from location 0x16 */
  92        memctl->memc_mar = 0x88;
  93        memctl->memc_mcr = 0x80002116;
  94        udelay(200);
  95
  96        memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
  97        memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
  98        memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
  99
 100        msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
 101        memctl->memc_or1  |= ~(msize - 1);
 102
 103        return msize;
 104}
 105
 106int checkboard( void )
 107{
 108        puts("Board: Adder");
 109#if defined(CONFIG_MPC885_FAMILY)
 110        puts("87x\n");
 111#elif defined(CONFIG_MPC866_FAMILY)
 112        puts("II\n");
 113#endif
 114
 115        return 0;
 116}
 117
 118#if defined(CONFIG_OF_BOARD_SETUP)
 119void ft_board_setup(void *blob, bd_t *bd)
 120{
 121        ft_cpu_setup(blob, bd);
 122
 123}
 124#endif
 125