LXR uboot/board/eltec/bab7xx/pci.c

   1/*
   2 * (C) Copyright 2002 ELTEC Elektronik AG
   3 * Frank Gottschling <fgottschling@eltec.de>
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * PCI initialisation for the MPC10x.
  26 */
  27
  28#include <common.h>
  29#include <pci.h>
  30#include <mpc106.h>
  31
  32#ifdef CONFIG_PCI
  33
  34struct pci_controller local_hose;
  35
  36void pci_init_board(void)
  37{
  38    struct pci_controller* hose = (struct pci_controller *)&local_hose;
  39    u32 reg32;
  40    u16 reg16;
  41
  42    hose->first_busno = 0;
  43    hose->last_busno = 0xff;
  44
  45    pci_set_region(hose->regions + 0,
  46        CONFIG_SYS_PCI_MEMORY_BUS,
  47        CONFIG_SYS_PCI_MEMORY_PHYS,
  48    /*
  49    * Attention: pci_hose_phys_to_bus() failes in address compare,
  50    * so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1)
  51    */
  52        CONFIG_SYS_PCI_MEMORY_SIZE-1,
  53        PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  54
  55    /* PCI memory space */
  56    pci_set_region(hose->regions + 1,
  57        CONFIG_SYS_PCI_MEM_BUS,
  58        CONFIG_SYS_PCI_MEM_PHYS,
  59        CONFIG_SYS_PCI_MEM_SIZE,
  60        PCI_REGION_MEM);
  61
  62    /* ISA/PCI memory space */
  63    pci_set_region(hose->regions + 2,
  64        CONFIG_SYS_ISA_MEM_BUS,
  65        CONFIG_SYS_ISA_MEM_PHYS,
  66        CONFIG_SYS_ISA_MEM_SIZE,
  67        PCI_REGION_MEM);
  68
  69    /* PCI I/O space */
  70    pci_set_region(hose->regions + 3,
  71        CONFIG_SYS_PCI_IO_BUS,
  72        CONFIG_SYS_PCI_IO_PHYS,
  73        CONFIG_SYS_PCI_IO_SIZE,
  74        PCI_REGION_IO);
  75
  76    /* ISA/PCI I/O space */
  77    pci_set_region(hose->regions + 4,
  78        CONFIG_SYS_ISA_IO_BUS,
  79        CONFIG_SYS_ISA_IO_PHYS,
  80        CONFIG_SYS_ISA_IO_SIZE,
  81        PCI_REGION_IO);
  82
  83    hose->region_count = 5;
  84
  85    pci_setup_indirect(hose,
  86        MPC106_REG_ADDR,
  87        MPC106_REG_DATA);
  88
  89    pci_register_hose(hose);
  90
  91    hose->last_busno = pci_hose_scan(hose);
  92
  93    /* Initialises the MPC10x PCI Configuration regs. */
  94    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, &reg32);
  95    reg32 |= PICR2_CF_SNOOP_WS(3) |
  96             PICR2_CF_FLUSH_L2 |
  97             PICR2_CF_L2_HIT_DELAY(3) |
  98             PICR2_CF_APHASE_WS(3);
  99    reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
 100    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);
 101
 102    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
 103    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 104    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
 105
 106    /* Clear non-reserved bits in status register */
 107    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
 108
 109    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, &reg32);
 110    reg32 |= PICR1_CF_CBA(63) |
 111             PICR1_CF_BREAD_WS(2) |
 112             PICR1_MCP_EN |
 113             PICR1_CF_DPARK |
 114             PICR1_PROC_TYPE_604 |
 115             PICR1_CF_LOOP_SNOOP |
 116             PICR1_CF_APARK;
 117    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
 118}
 119
 120#endif /* CONFIG_PCI */
 121