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23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/mmu.h>
28#include <asm/immap_85xx.h>
29#include <asm/fsl_pci.h>
30#include <asm/fsl_ddr_sdram.h>
31#include <asm/io.h>
32#include <miiphy.h>
33#include <libfdt.h>
34#include <fdt_support.h>
35#include <tsec.h>
36#include <netdev.h>
37
38#include "../common/sgmii_riser.h"
39
40int checkboard (void)
41{
42 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
43 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
44 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
45 u8 vboot;
46 u8 *pixis_base = (u8 *)PIXIS_BASE;
47
48 if ((uint)&gur->porpllsr != 0xe00e0000) {
49 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
50 }
51 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
52 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
53 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
54 in_8(pixis_base + PIXIS_PVER));
55
56 vboot = in_8(pixis_base + PIXIS_VBOOT);
57 if (vboot & PIXIS_VBOOT_FMAP)
58 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
59 else
60 puts ("Promjet\n");
61
62 lbc->ltesr = 0xffffffff;
63 lbc->lteir = 0xffffffff;
64 ecm->eedr = 0xffffffff;
65 ecm->eeer = 0xffffffff;
66
67 return 0;
68}
69
70phys_size_t
71initdram(int board_type)
72{
73 long dram_size = 0;
74
75 puts("Initializing\n");
76
77 dram_size = fsl_ddr_sdram();
78
79 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
80
81 dram_size *= 0x100000;
82
83 puts(" DDR: ");
84 return dram_size;
85}
86
87#ifdef CONFIG_PCI1
88static struct pci_controller pci1_hose;
89#endif
90
91#ifdef CONFIG_PCIE1
92static struct pci_controller pcie1_hose;
93#endif
94
95#ifdef CONFIG_PCIE2
96static struct pci_controller pcie2_hose;
97#endif
98
99#ifdef CONFIG_PCIE3
100static struct pci_controller pcie3_hose;
101#endif
102
103void pci_init_board(void)
104{
105 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
106 struct fsl_pci_info pci_info[4];
107 u32 devdisr, pordevsr, io_sel;
108 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
109 int first_free_busno = 0;
110 int num = 0;
111
112 int pcie_ep, pcie_configured;
113
114 devdisr = in_be32(&gur->devdisr);
115 pordevsr = in_be32(&gur->pordevsr);
116 porpllsr = in_be32(&gur->porpllsr);
117 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
118
119 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
120
121 if (io_sel & 1) {
122 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
123 printf (" eTSEC1 is in sgmii mode.\n");
124 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
125 printf (" eTSEC3 is in sgmii mode.\n");
126 }
127 puts("\n");
128
129#ifdef CONFIG_PCIE3
130 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
131
132 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
133 SET_STD_PCIE_INFO(pci_info[num], 3);
134 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
135#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
136
137 pci_set_region(&pcie3_hose.regions[0],
138 CONFIG_SYS_PCIE3_MEM_BUS2,
139 CONFIG_SYS_PCIE3_MEM_PHYS2,
140 CONFIG_SYS_PCIE3_MEM_SIZE2,
141 PCI_REGION_MEM);
142
143 pcie3_hose.region_count = 1;
144#endif
145 printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
146 pcie_ep ? "Endpoint" : "Root Complex",
147 pci_info[num].regs);
148 first_free_busno = fsl_pci_init_port(&pci_info[num++],
149 &pcie3_hose, first_free_busno);
150
151
152
153
154
155 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
156 } else {
157 printf (" PCIE3: disabled\n");
158 }
159 puts("\n");
160#else
161 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3);
162#endif
163
164#ifdef CONFIG_PCIE1
165 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
166
167 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
168 SET_STD_PCIE_INFO(pci_info[num], 1);
169 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
170#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
171
172 pci_set_region(&pcie1_hose.regions[0],
173 CONFIG_SYS_PCIE1_MEM_BUS2,
174 CONFIG_SYS_PCIE1_MEM_PHYS2,
175 CONFIG_SYS_PCIE1_MEM_SIZE2,
176 PCI_REGION_MEM);
177
178 pcie1_hose.region_count = 1;
179#endif
180 printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
181 pcie_ep ? "Endpoint" : "Root Complex",
182 pci_info[num].regs);
183
184 first_free_busno = fsl_pci_init_port(&pci_info[num++],
185 &pcie1_hose, first_free_busno);
186 } else {
187 printf (" PCIE1: disabled\n");
188 }
189
190 puts("\n");
191#else
192 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
193#endif
194
195#ifdef CONFIG_PCIE2
196 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
197
198 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
199 SET_STD_PCIE_INFO(pci_info[num], 2);
200 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
201#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
202
203 pci_set_region(&pcie2_hose.regions[0],
204 CONFIG_SYS_PCIE2_MEM_BUS2,
205 CONFIG_SYS_PCIE2_MEM_PHYS2,
206 CONFIG_SYS_PCIE2_MEM_SIZE2,
207 PCI_REGION_MEM);
208
209 pcie2_hose.region_count = 1;
210#endif
211 printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
212 pcie_ep ? "Endpoint" : "Root Complex",
213 pci_info[num].regs);
214 first_free_busno = fsl_pci_init_port(&pci_info[num++],
215 &pcie2_hose, first_free_busno);
216 } else {
217 printf (" PCIE2: disabled\n");
218 }
219
220 puts("\n");
221#else
222 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2);
223#endif
224
225#ifdef CONFIG_PCI1
226 pci_speed = 66666000;
227 pci_32 = 1;
228 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
229 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
230
231 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
232 SET_STD_PCI_INFO(pci_info[num], 1);
233 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
234 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
235 (pci_32) ? 32 : 64,
236 (pci_speed == 33333000) ? "33" :
237 (pci_speed == 66666000) ? "66" : "unknown",
238 pci_clk_sel ? "sync" : "async",
239 pci_agent ? "agent" : "host",
240 pci_arb ? "arbiter" : "external-arbiter",
241 pci_info[num].regs);
242
243 first_free_busno = fsl_pci_init_port(&pci_info[num++],
244 &pci1_hose, first_free_busno);
245 } else {
246 printf (" PCI: disabled\n");
247 }
248
249 puts("\n");
250#else
251 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
252#endif
253}
254
255
256int last_stage_init(void)
257{
258 return 0;
259}
260
261
262unsigned long
263get_board_sys_clk(ulong dummy)
264{
265 u8 i, go_bit, rd_clks;
266 ulong val = 0;
267 u8 *pixis_base = (u8 *)PIXIS_BASE;
268
269 go_bit = in_8(pixis_base + PIXIS_VCTL);
270 go_bit &= 0x01;
271
272 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
273 rd_clks &= 0x1C;
274
275
276
277
278
279
280
281 if (go_bit) {
282 if (rd_clks == 0x1c)
283 i = in_8(pixis_base + PIXIS_AUX);
284 else
285 i = in_8(pixis_base + PIXIS_SPD);
286 } else {
287 i = in_8(pixis_base + PIXIS_SPD);
288 }
289
290 i &= 0x07;
291
292 switch (i) {
293 case 0:
294 val = 33333333;
295 break;
296 case 1:
297 val = 40000000;
298 break;
299 case 2:
300 val = 50000000;
301 break;
302 case 3:
303 val = 66666666;
304 break;
305 case 4:
306 val = 83000000;
307 break;
308 case 5:
309 val = 100000000;
310 break;
311 case 6:
312 val = 133333333;
313 break;
314 case 7:
315 val = 166666666;
316 break;
317 }
318
319 return val;
320}
321
322int board_eth_init(bd_t *bis)
323{
324#ifdef CONFIG_TSEC_ENET
325 struct tsec_info_struct tsec_info[2];
326 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
327 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
328 int num = 0;
329
330#ifdef CONFIG_TSEC1
331 SET_STD_TSEC_INFO(tsec_info[num], 1);
332 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
333 tsec_info[num].flags |= TSEC_SGMII;
334 num++;
335#endif
336#ifdef CONFIG_TSEC3
337 SET_STD_TSEC_INFO(tsec_info[num], 3);
338 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
339 tsec_info[num].flags |= TSEC_SGMII;
340 num++;
341#endif
342
343 if (!num) {
344 printf("No TSECs initialized\n");
345
346 return 0;
347 }
348
349 if (io_sel & 1)
350 fsl_sgmii_riser_init(tsec_info, num);
351
352
353 tsec_eth_init(bis, tsec_info, num);
354#endif
355 return pci_eth_init(bis);
356}
357
358#if defined(CONFIG_OF_BOARD_SETUP)
359void ft_board_setup(void *blob, bd_t *bd)
360{
361 ft_cpu_setup(blob, bd);
362
363
364#ifdef CONFIG_PCI1
365 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
366#endif
367#ifdef CONFIG_PCIE2
368 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
369#endif
370#ifdef CONFIG_PCIE1
371 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
372#endif
373#ifdef CONFIG_PCIE3
374 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
375#endif
376#ifdef CONFIG_FSL_SGMII_RISER
377 fsl_sgmii_riser_fdt_fixup(blob);
378#endif
379}
380#endif
381
