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23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/immap_86xx.h>
28#include <asm/fsl_pci.h>
29#include <asm/fsl_ddr_sdram.h>
30#include <i2c.h>
31#include <asm/io.h>
32#include <libfdt.h>
33#include <fdt_support.h>
34#include <spd_sdram.h>
35#include <netdev.h>
36
37void sdram_init(void);
38phys_size_t fixed_sdram(void);
39void mpc8610hpcd_diu_init(void);
40
41
42
43int board_early_init_f(void)
44{
45 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
46 volatile ccsr_gur_t *gur = &immap->im_gur;
47
48 gur->gpiocr |= 0x88aa5500;
49
50 return 0;
51}
52
53int misc_init_r(void)
54{
55 u8 tmp_val, version;
56 u8 *pixis_base = (u8 *)PIXIS_BASE;
57
58
59 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
60 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
61
62
63 version = in_8(pixis_base + PIXIS_PVER);
64 if(version >= 0x07) {
65 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
66 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
67 }
68
69
70
71
72
73 tmp_val = 0xBF;
74 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
75
76 tmp_val = 0;
77 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
78 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
79
80 tmp_val = 0x10;
81 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
82
83 tmp_val = 0;
84 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
85 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
86
87#ifdef CONFIG_FSL_DIU_FB
88 mpc8610hpcd_diu_init();
89#endif
90
91 return 0;
92}
93
94int checkboard(void)
95{
96 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
97 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
98 u8 *pixis_base = (u8 *)PIXIS_BASE;
99
100 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
101 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
102 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
103 in_8(pixis_base + PIXIS_PVER));
104
105 mcm->abcr |= 0x00010000;
106 mcm->hpmr3 = 0x80000008;
107 mcm->hpmr0 = 0;
108 mcm->hpmr1 = 0;
109 mcm->hpmr2 = 0;
110 mcm->hpmr4 = 0;
111 mcm->hpmr5 = 0;
112
113 return 0;
114}
115
116
117phys_size_t
118initdram(int board_type)
119{
120 phys_size_t dram_size = 0;
121
122#if defined(CONFIG_SPD_EEPROM)
123 dram_size = fsl_ddr_sdram();
124#else
125 dram_size = fixed_sdram();
126#endif
127
128 setup_ddr_bat(dram_size);
129
130 puts(" DDR: ");
131 return dram_size;
132}
133
134
135#if !defined(CONFIG_SPD_EEPROM)
136
137
138
139
140phys_size_t fixed_sdram(void)
141{
142#if !defined(CONFIG_SYS_RAMBOOT)
143 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
144 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
145 uint d_init;
146
147 ddr->cs0_bnds = 0x0000001f;
148 ddr->cs0_config = 0x80010202;
149
150 ddr->timing_cfg_3 = 0x00000000;
151 ddr->timing_cfg_0 = 0x00260802;
152 ddr->timing_cfg_1 = 0x3935d322;
153 ddr->timing_cfg_2 = 0x14904cc8;
154 ddr->sdram_mode = 0x00480432;
155 ddr->sdram_mode_2 = 0x00000000;
156 ddr->sdram_interval = 0x06180fff;
157 ddr->sdram_data_init = 0xDEADBEEF;
158 ddr->sdram_clk_cntl = 0x03800000;
159 ddr->sdram_cfg_2 = 0x04400010;
160
161#if defined(CONFIG_DDR_ECC)
162 ddr->err_int_en = 0x0000000d;
163 ddr->err_disable = 0x00000000;
164 ddr->err_sbe = 0x00010000;
165#endif
166 asm("sync;isync");
167
168 udelay(500);
169
170 ddr->sdram_cfg = 0xc3000000;
171
172
173#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
174 d_init = 1;
175 debug("DDR - 1st controller: memory initializing\n");
176
177
178
179
180 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
181 udelay(1000);
182
183 debug("DDR: memory initialized\n\n");
184 asm("sync; isync");
185 udelay(500);
186#endif
187
188 return 512 * 1024 * 1024;
189#endif
190 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
191}
192
193#endif
194
195#if defined(CONFIG_PCI)
196
197
198
199
200#ifndef CONFIG_PCI_PNP
201static struct pci_config_table pci_fsl86xxads_config_table[] = {
202 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
203 PCI_IDSEL_NUMBER, PCI_ANY_ID,
204 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
205 PCI_ENET0_MEMADDR,
206 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
207 {}
208};
209#endif
210
211
212static struct pci_controller pci1_hose = {
213#ifndef CONFIG_PCI_PNP
214config_table:pci_mpc86xxcts_config_table
215#endif
216};
217#endif
218
219#ifdef CONFIG_PCIE1
220static struct pci_controller pcie1_hose;
221#endif
222
223#ifdef CONFIG_PCIE2
224static struct pci_controller pcie2_hose;
225#endif
226
227void pci_init_board(void)
228{
229 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
230 volatile ccsr_gur_t *gur = &immap->im_gur;
231 struct fsl_pci_info pci_info[3];
232 u32 devdisr, pordevsr, io_sel;
233 int first_free_busno = 0;
234 int num = 0;
235
236 int pci_agent, pcie_ep, pcie_configured;
237
238 devdisr = in_be32(&gur->devdisr);
239 pordevsr = in_be32(&gur->pordevsr);
240 io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
241 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
242
243 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
244
245#ifdef CONFIG_PCIE1
246 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
247
248 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
249 SET_STD_PCIE_INFO(pci_info[num], 1);
250 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
251 printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
252 pcie_ep ? "Endpoint" : "Root Complex",
253 pci_info[num].regs);
254
255 first_free_busno = fsl_pci_init_port(&pci_info[num++],
256 &pcie1_hose, first_free_busno);
257 } else {
258 printf (" PCIE1: disabled\n");
259 }
260
261 puts("\n");
262#else
263 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1);
264#endif
265
266#ifdef CONFIG_PCIE2
267 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
268
269 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
270 SET_STD_PCIE_INFO(pci_info[num], 2);
271 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
272 printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
273 pcie_ep ? "Endpoint" : "Root Complex",
274 pci_info[num].regs);
275 first_free_busno = fsl_pci_init_port(&pci_info[num++],
276 &pcie2_hose, first_free_busno);
277 } else {
278 printf (" PCIE2: disabled\n");
279 }
280
281 puts("\n");
282#else
283 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2);
284#endif
285
286#ifdef CONFIG_PCI1
287 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
288 SET_STD_PCI_INFO(pci_info[num], 1);
289 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
290 printf(" PCI connected to PCI slots as %s" \
291 " (base address %lx)\n",
292 pci_agent ? "Agent" : "Host",
293 pci_info[num].regs);
294 first_free_busno = fsl_pci_init_port(&pci_info[num++],
295 &pci1_hose, first_free_busno);
296 } else {
297 printf (" PCI: disabled\n");
298 }
299
300 puts("\n");
301#else
302 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1);
303#endif
304}
305
306#if defined(CONFIG_OF_BOARD_SETUP)
307void
308ft_board_setup(void *blob, bd_t *bd)
309{
310 ft_cpu_setup(blob, bd);
311
312#ifdef CONFIG_PCI1
313 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
314#endif
315#ifdef CONFIG_PCIE1
316 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
317#endif
318#ifdef CONFIG_PCIE2
319 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
320#endif
321}
322#endif
323
324
325
326
327
328
329unsigned long
330get_board_sys_clk(ulong dummy)
331{
332 u8 i;
333 ulong val = 0;
334 u8 *pixis_base = (u8 *)PIXIS_BASE;
335
336 i = in_8(pixis_base + PIXIS_SPD);
337 i &= 0x07;
338
339 switch (i) {
340 case 0:
341 val = 33333000;
342 break;
343 case 1:
344 val = 39999600;
345 break;
346 case 2:
347 val = 49999500;
348 break;
349 case 3:
350 val = 66666000;
351 break;
352 case 4:
353 val = 83332500;
354 break;
355 case 5:
356 val = 99999000;
357 break;
358 case 6:
359 val = 133332000;
360 break;
361 case 7:
362 val = 166665000;
363 break;
364 }
365
366 return val;
367}
368
369int board_eth_init(bd_t *bis)
370{
371 return pci_eth_init(bis);
372}
373
374void board_reset(void)
375{
376 u8 *pixis_base = (u8 *)PIXIS_BASE;
377
378 out_8(pixis_base + PIXIS_RST, 0);
379
380 while (1)
381 ;
382}
383
