LXR uboot/board/freescale/p2020ds/ddr.c

   1/*
   2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * Version 2 as published by the Free Software Foundation.
   7 */
   8
   9#include <common.h>
  10#include <i2c.h>
  11
  12#include <asm/fsl_ddr_sdram.h>
  13#include <asm/fsl_ddr_dimm_params.h>
  14
  15static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
  16{
  17        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
  18}
  19
  20unsigned int fsl_ddr_get_mem_data_rate(void)
  21{
  22        return get_ddr_freq(0);
  23}
  24
  25void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
  26                      unsigned int ctrl_num)
  27{
  28        unsigned int i;
  29        unsigned int i2c_address = 0;
  30
  31        for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
  32                if (ctrl_num == 0 && i == 0)
  33                        i2c_address = SPD_EEPROM_ADDRESS1;
  34                get_spd(&(ctrl_dimms_spd[i]), i2c_address);
  35        }
  36}
  37
  38typedef struct {
  39        u32 datarate_mhz_low;
  40        u32 datarate_mhz_high;
  41        u32 n_ranks;
  42        u32 clk_adjust;
  43        u32 cpo;
  44        u32 write_data_delay;
  45        u32 force_2T;
  46} board_specific_parameters_t;
  47
  48/* ranges for parameters:
  49 *  wr_data_delay = 0-6
  50 *  clk adjust = 0-8
  51 *  cpo 2-0x1E (30)
  52 */
  53
  54
  55/* XXX: these values need to be checked for all interleaving modes.  */
  56/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
  57 *      seem reliable, but errors will appear when memory intensive
  58 *      program is run. */
  59/* XXX: Single rank at 800 MHz is OK.  */
  60const board_specific_parameters_t board_specific_parameters[][20] = {
  61        {
  62        /*      memory controller 0                     */
  63        /*        lo|  hi|  num|  clk| cpo|wrdata|2T    */
  64        /*       mhz| mhz|ranks|adjst|    | delay|      */
  65                {  0, 333,    2,    6,   7,    3,  0},
  66                {334, 400,    2,    6,   9,    3,  0},
  67                {401, 549,    2,    6,  11,    3,  0},
  68                {550, 680,    2,    1,  10,    5,  0},
  69                {681, 850,    2,    1,  12,    5,  1},
  70                {  0, 333,    1,    6,   7,    3,  0},
  71                {334, 400,    1,    6,   9,    3,  0},
  72                {401, 549,    1,    6,  11,    3,  0},
  73                {550, 680,    1,    1,  10,    5,  0},
  74                {681, 850,    1,    1,  12,    5,  0}
  75        },
  76};
  77
  78void fsl_ddr_board_options(memctl_options_t *popts,
  79                                dimm_params_t *pdimm,
  80                                unsigned int ctrl_num)
  81{
  82        const board_specific_parameters_t *pbsp =
  83                                &(board_specific_parameters[ctrl_num][0]);
  84        u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
  85                                sizeof(board_specific_parameters[0][0]);
  86        u32 i;
  87        ulong ddr_freq;
  88
  89        /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
  90         * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
  91         * there are two dimms in the controller, set odt_rd_cfg to 3 and
  92         * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
  93         */
  94        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  95                if (i&1) {      /* odd CS */
  96                        popts->cs_local_opts[i].odt_rd_cfg = 0;
  97                        popts->cs_local_opts[i].odt_wr_cfg = 0;
  98                } else {        /* even CS */
  99                        if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 100                                popts->cs_local_opts[i].odt_rd_cfg = 0;
 101                                popts->cs_local_opts[i].odt_wr_cfg = 4;
 102                        } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 103                                popts->cs_local_opts[i].odt_rd_cfg = 3;
 104                                popts->cs_local_opts[i].odt_wr_cfg = 3;
 105                        }
 106                }
 107        }
 108
 109        /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 110         * freqency and n_banks specified in board_specific_parameters table.
 111         */
 112        ddr_freq = get_ddr_freq(0) / 1000000;
 113        for (i = 0; i < num_params; i++) {
 114                if (ddr_freq >= pbsp->datarate_mhz_low &&
 115                    ddr_freq <= pbsp->datarate_mhz_high &&
 116                    pdimm->n_ranks == pbsp->n_ranks) {
 117                        popts->clk_adjust = pbsp->clk_adjust;
 118                        popts->cpo_override = pbsp->cpo;
 119                        popts->write_data_delay = pbsp->write_data_delay;
 120                        popts->twoT_en = pbsp->force_2T;
 121                }
 122                pbsp++;
 123        }
 124
 125        /*
 126         * Factors to consider for half-strength driver enable:
 127         *      - number of DIMMs installed
 128         */
 129        popts->half_strength_driver_enable = 0;
 130}
 131