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27#include <common.h>
28#include "pip405.h"
29#include <asm/processor.h>
30#include <i2c.h>
31#include <stdio_dev.h>
32#include "../common/isa.h"
33#include "../common/common_util.h"
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#undef SDRAM_DEBUG
38
39#define FALSE 0
40#define TRUE 1
41
42
43#ifndef __ldiv_t_defined
44typedef struct {
45 long int quot;
46 long int rem;
47} ldiv_t;
48extern ldiv_t ldiv (long int __numer, long int __denom);
49
50# define __ldiv_t_defined 1
51#endif
52
53
54typedef enum {
55 SDRAM_NO_ERR,
56 SDRAM_SPD_COMM_ERR,
57 SDRAM_SPD_CHKSUM_ERR,
58 SDRAM_UNSUPPORTED_ERR,
59 SDRAM_UNKNOWN_ERR
60} SDRAM_ERR;
61
62typedef struct {
63 const unsigned char mode;
64 const unsigned char row;
65 const unsigned char col;
66 const unsigned char bank;
67} SDRAM_SETUP;
68
69static const SDRAM_SETUP sdram_setup_table[] = {
70 {1, 11, 9, 2},
71 {1, 11, 10, 2},
72 {2, 12, 9, 4},
73 {2, 12, 10, 4},
74 {3, 13, 9, 4},
75 {3, 13, 10, 4},
76 {3, 13, 11, 4},
77 {4, 12, 8, 2},
78 {4, 12, 8, 4},
79 {5, 11, 8, 2},
80 {5, 11, 8, 4},
81 {6, 13, 8, 2},
82 {6, 13, 8, 4},
83 {7, 13, 9, 2},
84 {7, 13, 10, 2},
85 {0, 0, 0, 0}
86};
87
88static const unsigned char cal_indextable[] = {
89 9, 23, 25
90};
91
92
93
94
95
96
97
98unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
99{
100 unsigned short ns, ns10;
101
102
103 ns = (spd_byte >> 4) & 0x0F;
104
105 ns10 = (spd_byte & 0x0F);
106
107 return (ns * 100 + ns10 * 10);
108}
109
110
111
112
113
114
115unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
116{
117 unsigned short ns, ns4;
118
119
120 ns = (spd_byte >> 2) & 0x3F;
121
122 ns4 = (spd_byte & 0x03);
123
124 return (ns * 100 + ns4 * 25);
125}
126
127
128
129
130
131
132unsigned short NSto10PS (unsigned char spd_byte)
133{
134 return (spd_byte * 100);
135}
136
137void SDRAM_err (const char *s)
138{
139#ifndef SDRAM_DEBUG
140 (void) get_clocks ();
141 gd->baudrate = 9600;
142 serial_init ();
143#endif
144 serial_puts ("\n");
145 serial_puts (s);
146 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
147 for (;;);
148}
149
150
151#ifdef SDRAM_DEBUG
152
153void write_hex (unsigned char i)
154{
155 char cc;
156
157 cc = i >> 4;
158 cc &= 0xf;
159 if (cc > 9)
160 serial_putc (cc + 55);
161 else
162 serial_putc (cc + 48);
163 cc = i & 0xf;
164 if (cc > 9)
165 serial_putc (cc + 55);
166 else
167 serial_putc (cc + 48);
168}
169
170void write_4hex (unsigned long val)
171{
172 write_hex ((unsigned char) (val >> 24));
173 write_hex ((unsigned char) (val >> 16));
174 write_hex ((unsigned char) (val >> 8));
175 write_hex ((unsigned char) val);
176}
177
178#endif
179
180int board_early_init_f (void)
181{
182 unsigned char dataout[1];
183 unsigned char datain[128];
184 unsigned long sdram_size = 0;
185 SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
186 unsigned long memclk;
187 unsigned long tmemclk = 0;
188 unsigned long tmp, bank, baseaddr, bank_size;
189 unsigned short i;
190 unsigned char rows, cols, banks, sdram_banks, density;
191 unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
192 trc_clocks, tctp_clocks;
193 unsigned char cal_index, cal_val, spd_version, spd_chksum;
194 unsigned char buf[8];
195
196 mtdcr (EBC0_CFGADDR, PB7AP);
197 mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
198 mtdcr (EBC0_CFGADDR, PB7CR);
199 mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
200
201 memclk = get_bus_freq (tmemclk);
202 tmemclk = 1000000000 / (memclk / 100);
203
204#ifdef SDRAM_DEBUG
205 (void) get_clocks ();
206 gd->baudrate = 9600;
207 serial_init ();
208 serial_puts ("\nstart SDRAM Setup\n");
209#endif
210
211
212 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
213 dataout[0] = 0;
214 for (i = 0; i < 128; i++)
215 datain[i] = 127;
216 i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
217#ifdef SDRAM_DEBUG
218 serial_puts ("\ni2c_read returns ");
219 write_hex (i);
220 serial_puts ("\n");
221#endif
222
223#ifdef SDRAM_DEBUG
224 for (i = 0; i < 128; i++) {
225 write_hex (datain[i]);
226 serial_puts (" ");
227 if (((i + 1) % 16) == 0)
228 serial_puts ("\n");
229 }
230 serial_puts ("\n");
231#endif
232 spd_chksum = 0;
233 for (i = 0; i < 63; i++) {
234 spd_chksum += datain[i];
235 }
236 if (datain[63] != spd_chksum) {
237#ifdef SDRAM_DEBUG
238 serial_puts ("SPD chksum: 0x");
239 write_hex (datain[63]);
240 serial_puts (" != calc. chksum: 0x");
241 write_hex (spd_chksum);
242 serial_puts ("\n");
243#endif
244 SDRAM_err ("SPD checksum Error");
245 }
246
247
248
249 spd_version = datain[62];
250
251
252 if ((datain[0] < 0x80) ||
253 (datain[2] != 0x04) ||
254 (!((datain[6] == 0x40) || (datain[6] == 0x48))) ||
255 (datain[7] != 0x00) || (datain[8] != 0x01) ||
256 (datain[126] == 0x66))
257 SDRAM_err ("unsupported SDRAM");
258#ifdef SDRAM_DEBUG
259 serial_puts ("SDRAM sanity ok\n");
260#endif
261
262
263 rows = datain[3];
264 cols = datain[4];
265 banks = datain[5];
266
267
268
269 sdram_banks = datain[17];
270 supported_cal = datain[18] & ~0x81;
271
272 while (t->mode != 0) {
273 if ((t->row == rows) && (t->col == cols)
274 && (t->bank == sdram_banks))
275 break;
276 t++;
277 }
278
279#ifdef SDRAM_DEBUG
280 serial_puts ("rows: ");
281 write_hex (rows);
282 serial_puts (" cols: ");
283 write_hex (cols);
284 serial_puts (" banks: ");
285 write_hex (banks);
286 serial_puts (" mode: ");
287 write_hex (t->mode);
288 serial_puts ("\n");
289#endif
290 if (t->mode == 0)
291 SDRAM_err ("unsupported SDRAM");
292
293#ifdef SDRAM_DEBUG
294 serial_puts ("tRP: ");
295 write_hex (datain[27]);
296 serial_puts ("\ntRCD: ");
297 write_hex (datain[29]);
298 serial_puts ("\ntRAS: ");
299 write_hex (datain[30]);
300 serial_puts ("\n");
301#endif
302
303 trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
304 trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
305 tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
306 density = datain[31];
307
308
309 trc_clocks = trp_clocks + tras_clocks;
310
311 tctp_clocks =
312 ((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
313 (tmemclk - 1)) / tmemclk;
314
315#ifdef SDRAM_DEBUG
316 serial_puts ("c_RP: ");
317 write_hex (trp_clocks);
318 serial_puts ("\nc_RCD: ");
319 write_hex (trcd_clocks);
320 serial_puts ("\nc_RAS: ");
321 write_hex (tras_clocks);
322 serial_puts ("\nc_RC: (RP+RAS): ");
323 write_hex (trc_clocks);
324 serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
325 write_hex (tctp_clocks);
326 serial_puts ("\nt_CTP: RAS - RCD: ");
327 write_hex ((unsigned
328 char) ((NSto10PS (datain[30]) -
329 NSto10PS (datain[29])) >> 8));
330 write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
331 serial_puts ("\ntmemclk: ");
332 write_hex ((unsigned char) (tmemclk >> 8));
333 write_hex ((unsigned char) (tmemclk));
334 serial_puts ("\n");
335#endif
336
337
338 cal_val = 255;
339 for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
340
341 if ((supported_cal >> i) & 0x01) {
342 buf[0] = datain[cal_indextable[cal_index]];
343 if (cal_index < 2) {
344 if (NS10to10PS (buf[0], spd_version) <= tmemclk)
345 cal_val = i;
346 } else {
347
348 if (NS4to10PS (buf[0], spd_version) <= tmemclk)
349 cal_val = i;
350 }
351 cal_index++;
352 }
353 }
354#ifdef SDRAM_DEBUG
355 serial_puts ("CAL: ");
356 write_hex (cal_val + 1);
357 serial_puts ("\n");
358#endif
359
360 if (cal_val == 255)
361 SDRAM_err ("unsupported SDRAM");
362
363
364 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
365 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
366
367
368 tmp |= ((unsigned long) cal_val) << 23;
369
370 tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
371
372
373 tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
374
375 tmp |= ((unsigned long) 0x01) << 14;
376
377 tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
378
379 tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
380
381#ifdef SDRAM_DEBUG
382 serial_puts ("sdtr: ");
383 write_4hex (tmp);
384 serial_puts ("\n");
385#endif
386
387
388 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
389 mtdcr (SDRAM0_CFGDATA, tmp);
390 baseaddr = CONFIG_SYS_SDRAM_BASE;
391 bank_size = (((unsigned long) density) << 22) / 2;
392
393 tmp = ((unsigned long) t->mode - 1) << 13;
394
395 switch (bank_size) {
396 case 0x00400000:
397 tmp |= ((unsigned long) 0x00) << 17;
398 break;
399 case 0x00800000:
400 tmp |= ((unsigned long) 0x01) << 17;
401 break;
402 case 0x01000000:
403 tmp |= ((unsigned long) 0x02) << 17;
404 break;
405 case 0x02000000:
406 tmp |= ((unsigned long) 0x03) << 17;
407 break;
408 case 0x04000000:
409 tmp |= ((unsigned long) 0x04) << 17;
410 break;
411 case 0x08000000:
412 tmp |= ((unsigned long) 0x05) << 17;
413 break;
414 case 0x10000000:
415 tmp |= ((unsigned long) 0x06) << 17;
416 break;
417 default:
418 SDRAM_err ("unsupported SDRAM");
419 }
420
421 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
422 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
423 bank |= (baseaddr | tmp | 0x01);
424#ifdef SDRAM_DEBUG
425 serial_puts ("bank0: baseaddr: ");
426 write_4hex (baseaddr);
427 serial_puts (" banksize: ");
428 write_4hex (bank_size);
429 serial_puts (" mb0cf: ");
430 write_4hex (bank);
431 serial_puts ("\n");
432#endif
433 baseaddr += bank_size;
434 sdram_size += bank_size;
435
436
437 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
438 mtdcr (SDRAM0_CFGDATA, bank);
439
440
441 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
442 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
443 sdram_size = 0;
444
445#ifdef SDRAM_DEBUG
446 serial_puts ("bank1: baseaddr: ");
447 write_4hex (baseaddr);
448 serial_puts (" banksize: ");
449 write_4hex (bank_size);
450#endif
451 if (banks == 2) {
452 bank |= (baseaddr | tmp | 0x01);
453 baseaddr += bank_size;
454 sdram_size += bank_size;
455 }
456#ifdef SDRAM_DEBUG
457 serial_puts (" mb1cf: ");
458 write_4hex (bank);
459 serial_puts ("\n");
460#endif
461
462 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
463 mtdcr (SDRAM0_CFGDATA, bank);
464
465
466 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
467 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
468
469 bank |= (baseaddr | tmp | 0x01);
470
471#ifdef SDRAM_DEBUG
472 serial_puts ("bank2: baseaddr: ");
473 write_4hex (baseaddr);
474 serial_puts (" banksize: ");
475 write_4hex (bank_size);
476 serial_puts (" mb2cf: ");
477 write_4hex (bank);
478 serial_puts ("\n");
479#endif
480
481 baseaddr += bank_size;
482 sdram_size += bank_size;
483
484
485 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
486 mtdcr (SDRAM0_CFGDATA, bank);
487
488
489 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
490 bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
491
492#ifdef SDRAM_DEBUG
493 serial_puts ("bank3: baseaddr: ");
494 write_4hex (baseaddr);
495 serial_puts (" banksize: ");
496 write_4hex (bank_size);
497#endif
498
499 if (banks == 2) {
500 bank |= (baseaddr | tmp | 0x01);
501 baseaddr += bank_size;
502 sdram_size += bank_size;
503 }
504
505#ifdef SDRAM_DEBUG
506 serial_puts (" mb3cf: ");
507 write_4hex (bank);
508 serial_puts ("\n");
509#endif
510
511
512 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
513 mtdcr (SDRAM0_CFGDATA, bank);
514
515
516
517 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
518 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
519
520 if (tmemclk < NSto10PS (16))
521 tmp |= 0x05F00000;
522 else
523 tmp |= 0x03F80000;
524
525
526 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
527 mtdcr (SDRAM0_CFGDATA, tmp);
528
529
530 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
531 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
532 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
533 mtdcr (SDRAM0_CFGDATA, tmp);
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555 mtdcr (UIC0SR, 0xFFFFFFFF);
556 mtdcr (UIC0ER, 0x00000000);
557 mtdcr (UIC0CR, 0x00000000);
558 mtdcr (UIC0PR, 0xFFFFFF80);
559 mtdcr (UIC0TR, 0x10000000);
560 mtdcr (UIC0VCR, 0x00000001);
561 mtdcr (UIC0SR, 0xFFFFFFFF);
562
563 return 0;
564}
565
566
567
568
569
570
571
572
573int checkboard (void)
574{
575 char s[50];
576 unsigned char bc;
577 int i;
578 backup_t *b = (backup_t *) s;
579
580 puts ("Board: ");
581
582 i = getenv_r ("serial#", (char *)s, 32);
583 if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
584 get_backup_values (b);
585 if (strncmp (b->signature, "MPL\0", 4) != 0) {
586 puts ("### No HW ID - assuming PIP405");
587 } else {
588 b->serial_name[6] = 0;
589 printf ("%s SN: %s", b->serial_name,
590 &b->serial_name[7]);
591 }
592 } else {
593 s[6] = 0;
594 printf ("%s SN: %s", s, &s[7]);
595 }
596 bc = in8 (CONFIG_PORT_ADDR);
597 printf (" Boot Config: 0x%x\n", bc);
598 return (0);
599}
600
601
602
603
604
605
606
607
608
609
610static int test_dram (unsigned long ramsize);
611
612phys_size_t initdram (int board_type)
613{
614 unsigned long bank_reg[4], tmp, bank_size;
615 int i, ds;
616 unsigned long TotalSize;
617
618 ds = 0;
619
620
621
622 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
623 bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
624 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
625 bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
626 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
627 bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
628 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
629 bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
630 TotalSize = 0;
631 for (i = 0; i < 4; i++) {
632 if ((bank_reg[i] & 0x1) == 0x1) {
633 tmp = (bank_reg[i] >> 17) & 0x7;
634 bank_size = 4 << tmp;
635 TotalSize += bank_size;
636 } else
637 ds = 1;
638 }
639 if (ds == 1)
640 printf ("single-sided DIMM ");
641 else
642 printf ("double-sided DIMM ");
643 test_dram (TotalSize * 1024 * 1024);
644
645 (void) get_clocks();
646 if (gd->cpu_clk > 220000000)
647 TotalSize /= 2;
648 return (TotalSize * 1024 * 1024);
649}
650
651
652
653
654static int test_dram (unsigned long ramsize)
655{
656
657 return (1);
658}
659
660
661extern flash_info_t flash_info[];
662
663int misc_init_r (void)
664{
665
666 gd->bd->bi_flashstart=0-flash_info[0].size;
667 gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
668 gd->bd->bi_flashoffset=0;
669
670
671 if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
672 mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
673
674 return (0);
675}
676
677
678
679
680
681int overwrite_console (void)
682{
683 return (in8 (CONFIG_PORT_ADDR) & 0x1);
684}
685
686
687extern int isa_init (void);
688
689
690void print_pip405_rev (void)
691{
692 unsigned char part, vers, cfg;
693
694 part = in8 (PLD_PART_REG);
695 vers = in8 (PLD_VERS_REG);
696 cfg = in8 (PLD_BOARD_CFG_REG);
697 printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
698 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
699 vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
700}
701
702extern void check_env(void);
703
704
705int last_stage_init (void)
706{
707 print_pip405_rev ();
708 isa_init ();
709 stdio_print_current_devices ();
710 check_env();
711 return 0;
712}
713
714
715
716
717void print_pip405_info (void)
718{
719 unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
720 compwr, nicvga, scsirst;
721
722 part = in8 (PLD_PART_REG);
723 vers = in8 (PLD_VERS_REG);
724 cfg = in8 (PLD_BOARD_CFG_REG);
725 ledu = in8 (PLD_LED_USER_REG);
726 sysman = in8 (PLD_SYS_MAN_REG);
727 flashcom = in8 (PLD_FLASH_COM_REG);
728 can = in8 (PLD_CAN_REG);
729 serpwr = in8 (PLD_SER_PWR_REG);
730 compwr = in8 (PLD_COM_PWR_REG);
731 nicvga = in8 (PLD_NIC_VGA_REG);
732 scsirst = in8 (PLD_SCSI_RST_REG);
733 printf ("PLD Part %d version %d\n",
734 part & 0xf, vers & 0xf);
735 printf ("PLD Part %d version %d\n",
736 (part >> 4) & 0xf, (vers >> 4) & 0xf);
737 printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
738 printf ("Population Options %d %d %d %d\n",
739 (cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
740 (cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
741 printf ("User LED0 %s User LED1 %s\n",
742 ((ledu & 0x1) == 0x1) ? "on" : "off",
743 ((ledu & 0x2) == 0x2) ? "on" : "off");
744 printf ("Additionally Options %d %d\n",
745 (ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
746 printf ("User Config Switch %d %d %d %d\n",
747 (ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
748 (ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
749 switch (sysman & 0x3) {
750 case 0:
751 printf ("PCI Clocks are running\n");
752 break;
753 case 1:
754 printf ("PCI Clocks are stopped in POS State\n");
755 break;
756 case 2:
757 printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
758 break;
759 case 3:
760 printf ("PCI Clocks are stopped\n");
761 break;
762 }
763 switch ((sysman >> 2) & 0x3) {
764 case 0:
765 printf ("Main Clocks are running\n");
766 break;
767 case 1:
768 printf ("Main Clocks are stopped in POS State\n");
769 break;
770 case 2:
771 case 3:
772 printf ("PCI Clocks are stopped\n");
773 break;
774 }
775 printf ("INIT asserts %sINT2# (SMI)\n",
776 ((sysman & 0x10) == 0x10) ? "" : "not ");
777 printf ("INIT asserts %sINT1# (NMI)\n",
778 ((sysman & 0x20) == 0x20) ? "" : "not ");
779 printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
780 printf ("SER1 is routed to %s\n",
781 ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
782 printf ("COM2 is routed to %s\n",
783 ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
784 printf ("RS485 is configured as %s duplex\n",
785 ((flashcom & 0x4) == 0x4) ? "full" : "half");
786 printf ("RS485 is connected to %s\n",
787 ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
788 printf ("SER1 uses handshakes %s\n",
789 ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
790 printf ("Bootflash is %swriteprotected\n",
791 ((flashcom & 0x20) == 0x20) ? "not " : "");
792 printf ("Bootflash VPP is %s\n",
793 ((flashcom & 0x40) == 0x40) ? "on" : "off");
794 printf ("Bootsector is %swriteprotected\n",
795 ((flashcom & 0x80) == 0x80) ? "not " : "");
796 switch ((can) & 0x3) {
797 case 0:
798 printf ("CAN Controller is on address 0x1000..0x10FF\n");
799 break;
800 case 1:
801 printf ("CAN Controller is on address 0x8000..0x80FF\n");
802 break;
803 case 2:
804 printf ("CAN Controller is on address 0xE000..0xE0FF\n");
805 break;
806 case 3:
807 printf ("CAN Controller is disabled\n");
808 break;
809 }
810 switch ((can >> 2) & 0x3) {
811 case 0:
812 printf ("CAN Controller Reset is ISA Reset\n");
813 break;
814 case 1:
815 printf ("CAN Controller Reset is ISA Reset and POS State\n");
816 break;
817 case 2:
818 case 3:
819 printf ("CAN Controller is in reset\n");
820 break;
821 }
822 if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
823 printf ("CAN Interrupt is disabled\n");
824 else
825 printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
826 switch (serpwr & 0x3) {
827 case 0:
828 printf ("SER0 Drivers are enabled\n");
829 break;
830 case 1:
831 printf ("SER0 Drivers are disabled in the POS state\n");
832 break;
833 case 2:
834 case 3:
835 printf ("SER0 Drivers are disabled\n");
836 break;
837 }
838 switch ((serpwr >> 2) & 0x3) {
839 case 0:
840 printf ("SER1 Drivers are enabled\n");
841 break;
842 case 1:
843 printf ("SER1 Drivers are disabled in the POS state\n");
844 break;
845 case 2:
846 case 3:
847 printf ("SER1 Drivers are disabled\n");
848 break;
849 }
850 switch (compwr & 0x3) {
851 case 0:
852 printf ("COM1 Drivers are enabled\n");
853 break;
854 case 1:
855 printf ("COM1 Drivers are disabled in the POS state\n");
856 break;
857 case 2:
858 case 3:
859 printf ("COM1 Drivers are disabled\n");
860 break;
861 }
862 switch ((compwr >> 2) & 0x3) {
863 case 0:
864 printf ("COM2 Drivers are enabled\n");
865 break;
866 case 1:
867 printf ("COM2 Drivers are disabled in the POS state\n");
868 break;
869 case 2:
870 case 3:
871 printf ("COM2 Drivers are disabled\n");
872 break;
873 }
874 switch ((nicvga) & 0x3) {
875 case 0:
876 printf ("PHY is running\n");
877 break;
878 case 1:
879 printf ("PHY is in Power save mode in POS state\n");
880 break;
881 case 2:
882 case 3:
883 printf ("PHY is in Power save mode\n");
884 break;
885 }
886 switch ((nicvga >> 2) & 0x3) {
887 case 0:
888 printf ("VGA is running\n");
889 break;
890 case 1:
891 printf ("VGA is in Power save mode in POS state\n");
892 break;
893 case 2:
894 case 3:
895 printf ("VGA is in Power save mode\n");
896 break;
897 }
898 printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
899 printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
900 printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
901 (nicvga >> 7) & 0x1);
902 switch ((scsirst) & 0x3) {
903 case 0:
904 printf ("SCSI Controller is running\n");
905 break;
906 case 1:
907 printf ("SCSI Controller is in Power save mode in POS state\n");
908 break;
909 case 2:
910 case 3:
911 printf ("SCSI Controller is in Power save mode\n");
912 break;
913 }
914 printf ("SCSI termination is %s\n",
915 ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
916 printf ("SCSI Controller is %sreseted\n",
917 ((scsirst & 0x10) == 0x10) ? "" : "not ");
918 printf ("IDE disks are %sreseted\n",
919 ((scsirst & 0x20) == 0x20) ? "" : "not ");
920 printf ("ISA Bus is %sreseted\n",
921 ((scsirst & 0x40) == 0x40) ? "" : "not ");
922 printf ("Super IO is %sreseted\n",
923 ((scsirst & 0x80) == 0x80) ? "" : "not ");
924}
925
926void user_led0 (unsigned char on)
927{
928 if (on == TRUE)
929 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
930 else
931 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
932}
933
934void user_led1 (unsigned char on)
935{
936 if (on == TRUE)
937 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
938 else
939 out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
940}
941
942void ide_set_reset (int idereset)
943{
944
945 unsigned char resreg;
946
947 resreg = in8 (PLD_SCSI_RST_REG);
948 if (idereset == 1)
949 resreg |= 0x20;
950 else {
951 udelay(10000);
952 resreg &= 0xdf;
953 }
954 out8 (PLD_SCSI_RST_REG, resreg);
955}
956
