LXR uboot/board/siemens/IAD210/IAD210.c

   1/*
   2 * (C) Copyright 2001
   3 * Paul Geerinckx
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <mpc8xx.h>
  26#include <net.h>
  27#include "atm.h"
  28#include <i2c.h>
  29
  30/* ------------------------------------------------------------------------- */
  31
  32static long int dram_size (long int, long int *, long int);
  33
  34/* ------------------------------------------------------------------------- */
  35
  36/* used PLD registers */
  37#  define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
  38#  define PLD_EXT_RES  (unsigned char *) (0x10000000 + 10)
  39#  define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
  40#  define PLD_EXT_LED  (unsigned char *) (0x10000000 + 12)
  41#  define PLD_EXT_X21  (unsigned char *) (0x10000000 + 13)
  42
  43#define _NOT_USED_      0xFFFFFFFF
  44
  45const uint sdram_table[] = {
  46        /*
  47         * Single Read. (Offset 0 in UPMA RAM)
  48         */
  49        0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
  50        _NOT_USED_,
  51        /*
  52         * SDRAM Initialization (offset 5 in UPMA RAM)
  53         *
  54         * This is no UPM entry point. The following definition uses
  55         * the remaining space to establish an initialization
  56         * sequence, which is executed by a RUN command.
  57         *
  58         */
  59        0xFFFAF834, 0xFFE5B435, /* last */
  60        _NOT_USED_,
  61        /*
  62         * Burst Read. (Offset 8 in UPMA RAM)
  63         */
  64        0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
  65        0xF0AFFC00, 0xF0AAF800, 0xF1A5E447,     /* last */
  66        _NOT_USED_,
  67        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  68        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  69        /*
  70         * Single Write. (Offset 18 in UPMA RAM)
  71         */
  72        0xFE29B300, 0xF1A27304, 0xFFA5F747,     /* last */
  73        _NOT_USED_,
  74        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  75        /*
  76         * Burst Write. (Offset 20 in UPMA RAM)
  77         */
  78        0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
  79        0xF1AAF804, 0xFFA5F447, /* last */
  80        _NOT_USED_, _NOT_USED_,
  81        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  82        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  83        /*
  84         * Refresh  (Offset 30 in UPMA RAM)
  85         */
  86        0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
  87        0xFFAFFC07,             /* last */
  88        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  89        /*
  90         * MRS sequence  (Offset 38 in UPMA RAM)
  91         */
  92        0xFFAAB834, 0xFFA57434, 0xFFAFFC05,     /* last */
  93        _NOT_USED_,
  94        /*
  95         * Exception. (Offset 3c in UPMA RAM)
  96         */
  97        0xFFAFFC04, 0xFFAFFC05, /* last */
  98        _NOT_USED_, _NOT_USED_,
  99};
 100
 101/* ------------------------------------------------------------------------- */
 102
 103
 104phys_size_t initdram (int board_type)
 105{
 106        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 107        volatile memctl8xx_t *memctl = &immap->im_memctl;
 108        volatile iop8xx_t *iop = &immap->im_ioport;
 109        volatile fec_t *fecp = &immap->im_cpm.cp_fec;
 110        long int size;
 111
 112        upmconfig (UPMA, (uint *) sdram_table,
 113                   sizeof (sdram_table) / sizeof (uint));
 114
 115        /*
 116         * Preliminary prescaler for refresh (depends on number of
 117         * banks): This value is selected for four cycles every 62.4 us
 118         * with two SDRAM banks or four cycles every 31.2 us with one
 119         * bank. It will be adjusted after memory sizing.
 120         */
 121        memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 122
 123        memctl->memc_mar = 0x00000088;
 124
 125        /*
 126         * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
 127         * preliminary addresses - these have to be modified after the
 128         * SDRAM size has been determined.
 129         */
 130        memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
 131        memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 132
 133        memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));   /* no refresh yet */
 134
 135        udelay (200);
 136
 137        /* perform SDRAM initializsation sequence */
 138
 139        memctl->memc_mcr = 0x80004105;  /* SDRAM bank 0 */
 140        udelay (1);
 141        memctl->memc_mcr = 0x80004230;  /* SDRAM bank 0 - execute twice */
 142        udelay (1);
 143
 144        memctl->memc_mcr = 0x80004105;  /* SDRAM precharge */
 145        udelay (1);
 146        memctl->memc_mcr = 0x80004030;  /* SDRAM 16x autorefresh */
 147        udelay (1);
 148        memctl->memc_mcr = 0x80004138;  /* SDRAM upload parameters */
 149        udelay (1);
 150
 151        memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 152
 153        udelay (1000);
 154
 155        /*
 156         * Check Bank 0 Memory Size for re-configuration
 157         *
 158         */
 159        size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM,
 160                          SDRAM_MAX_SIZE);
 161
 162        udelay (1000);
 163
 164
 165        memctl->memc_mamr = CONFIG_SYS_MAMR;
 166        udelay (1000);
 167
 168        /*
 169         * Final mapping
 170         */
 171        memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM;
 172        memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
 173
 174        udelay (10000);
 175
 176        /* prepare pin multiplexing for fast ethernet */
 177
 178        atmLoad ();
 179        fecp->fec_ecntrl = 0x00000004;  /* rev D3 pinmux SET */
 180        iop->iop_pdpar |= 0x0080;       /* set pin as MII_clock */
 181
 182
 183        return (size);
 184}
 185
 186/* ------------------------------------------------------------------------- */
 187
 188/*
 189 * Check memory range for valid RAM. A simple memory test determines
 190 * the actually available RAM size between addresses `base' and
 191 * `base + maxsize'. Some (not all) hardware errors are detected:
 192 * - short between address lines
 193 * - short between data lines
 194 */
 195
 196static long int dram_size (long int mamr_value, long int *base,
 197                           long int maxsize)
 198{
 199        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 200        volatile memctl8xx_t *memctl = &immap->im_memctl;
 201
 202        memctl->memc_mamr = mamr_value;
 203
 204        return (get_ram_size (base, maxsize));
 205}
 206
 207/*
 208 * Check Board Identity:
 209 */
 210
 211int checkboard (void)
 212{
 213        return (0);
 214}
 215
 216void board_serial_init (void)
 217{
 218        ;                       /* nothing to do here */
 219}
 220
 221void board_ether_init (void)
 222{
 223        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 224        volatile iop8xx_t *iop = &immap->im_ioport;
 225        volatile fec_t *fecp = &immap->im_cpm.cp_fec;
 226
 227        atmLoad ();
 228        fecp->fec_ecntrl = 0x00000004;  /* rev D3 pinmux SET */
 229        iop->iop_pdpar |= 0x0080;       /* set pin as MII_clock */
 230}
 231
 232int board_early_init_f (void)
 233{
 234        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 235        volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
 236        volatile memctl8xx_t *memctl = &immap->im_memctl;
 237        volatile iop8xx_t *iop = &immap->im_ioport;
 238
 239        /* configure the LED timing output pins - port A pin 4 */
 240        iop->iop_papar = 0x0800;
 241        iop->iop_padir = 0x0800;
 242
 243        /* start timer 2 for the 4hz LED blink rate */
 244        timers->cpmt_tmr2 = 0xff2c;     /* 4HZ for 64MHz */
 245        timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
 246        timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
 247
 248        /* chip select for PLD access */
 249        memctl->memc_br6 = 0x10000401;
 250        memctl->memc_or6 = 0xFC000908;
 251
 252        /* PLD initial values ( set LEDs, remove reset on LXT) */
 253
 254        *PLD_GCR1_REG = 0x06;
 255        *PLD_EXT_RES = 0xC0;
 256        *PLD_EXT_FETH = 0x40;
 257        *PLD_EXT_LED = 0xFF;
 258        *PLD_EXT_X21 = 0x04;
 259        return 0;
 260}
 261
 262static void board_get_enetaddr(uchar *addr)
 263{
 264        int i;
 265        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 266        volatile cpm8xx_t *cpm = &immap->im_cpm;
 267        unsigned int rccrtmp;
 268
 269        char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
 270
 271        for (i = 0; i < 6; i++)
 272                addr[i] = default_mac_addr[i];
 273
 274        printf ("There is an error in the i2c driver .. /n");
 275        printf ("You need to fix it first....../n");
 276
 277        rccrtmp = cpm->cp_rccr;
 278        cpm->cp_rccr |= 0x0020;
 279
 280        i2c_reg_read (0xa0, 0);
 281        printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
 282                i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
 283                i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
 284                i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
 285
 286        cpm->cp_rccr = rccrtmp;
 287}
 288
 289int misc_init_r(void)
 290{
 291        uchar enetaddr[6];
 292
 293        if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 294                board_get_enetaddr(enetaddr);
 295                eth_setenv_enetaddr("ethaddr", enetaddr);
 296        }
 297
 298        return 0;
 299}
 300