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28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32
33
34
35
36#define CONFIG_405GP 1
37#define CONFIG_4xx 1
38#define CONFIG_CPCI405 1
39#define CONFIG_CPCI405_VER2 1
40#undef CONFIG_CPCI405_6U
41
42#define CONFIG_BOARD_EARLY_INIT_F 1
43#define CONFIG_MISC_INIT_R 1
44
45#define CONFIG_SYS_CLK_FREQ 33330000
46
47#define CONFIG_BAUDRATE 9600
48#define CONFIG_BOOTDELAY 3
49
50#undef CONFIG_BOOTARGS
51#undef CONFIG_BOOTCOMMAND
52
53#define CONFIG_PREBOOT
54
55#define CONFIG_LOADS_ECHO 1
56#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
57
58#define CONFIG_PPC4xx_EMAC
59#define CONFIG_MII 1
60#define CONFIG_PHY_ADDR 0
61#define CONFIG_LXT971_NO_SLEEP 1
62#define CONFIG_RESET_PHY_R 1
63
64#define CONFIG_NET_MULTI 1
65#undef CONFIG_HAS_ETH1
66
67#define CONFIG_RTC_M48T35A 1
68
69
70
71
72#define CONFIG_BOOTP_SUBNETMASK
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_DNS
77#define CONFIG_BOOTP_DNS2
78#define CONFIG_BOOTP_SEND_HOSTNAME
79
80
81
82
83
84#include <config_cmd_default.h>
85
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_PCI
88#define CONFIG_CMD_IRQ
89#define CONFIG_CMD_IDE
90#define CONFIG_CMD_FAT
91#define CONFIG_CMD_ELF
92#define CONFIG_CMD_DATE
93#define CONFIG_CMD_I2C
94#define CONFIG_CMD_MII
95#define CONFIG_CMD_PING
96#define CONFIG_CMD_BSP
97#define CONFIG_CMD_EEPROM
98
99#define CONFIG_MAC_PARTITION
100#define CONFIG_DOS_PARTITION
101
102#define CONFIG_SUPPORT_VFAT
103
104#undef CONFIG_WATCHDOG
105
106#define CONFIG_SDRAM_BANK0 1
107
108
109
110
111#define CONFIG_SYS_LONGHELP
112#define CONFIG_SYS_PROMPT "=> "
113
114#undef CONFIG_SYS_HUSH_PARSER
115#ifdef CONFIG_SYS_HUSH_PARSER
116#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
117#endif
118
119#if defined(CONFIG_CMD_KGDB)
120#define CONFIG_SYS_CBSIZE 1024
121#else
122#define CONFIG_SYS_CBSIZE 256
123#endif
124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
125#define CONFIG_SYS_MAXARGS 16
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
127
128#define CONFIG_SYS_DEVICE_NULLDEV 1
129
130#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
131
132#define CONFIG_AUTO_COMPLETE 1
133
134#define CONFIG_SYS_MEMTEST_START 0x0400000
135#define CONFIG_SYS_MEMTEST_END 0x0C00000
136
137#undef CONFIG_SYS_EXT_SERIAL_CLOCK
138#define CONFIG_SYS_BASE_BAUD 691200
139
140
141#define CONFIG_SYS_BAUDRATE_TABLE \
142 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
143 57600, 115200, 230400, 460800, 921600 }
144
145#define CONFIG_SYS_LOAD_ADDR 0x100000
146#define CONFIG_SYS_EXTBDINFO 1
147
148#define CONFIG_SYS_HZ 1000
149
150#define CONFIG_CMDLINE_EDITING
151
152#define CONFIG_LOOPW 1
153
154#define CONFIG_ZERO_BOOTDELAY_CHECK
155
156#define CONFIG_VERSION_VARIABLE 1
157
158#define CONFIG_AUTOBOOT_KEYED 1
159#define CONFIG_AUTOBOOT_PROMPT \
160 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
161#undef CONFIG_AUTOBOOT_DELAY_STR
162#define CONFIG_AUTOBOOT_STOP_STR " "
163
164#define CONFIG_SYS_RX_ETH_BUFFER 16
165
166
167
168
169
170#define PCI_HOST_ADAPTER 0
171#define PCI_HOST_FORCE 1
172#define PCI_HOST_AUTO 2
173
174#define CONFIG_PCI
175#define CONFIG_PCI_HOST PCI_HOST_AUTO
176#define CONFIG_PCI_PNP
177
178
179#define CONFIG_PCI_SCAN_SHOW
180
181#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
182
183#define CONFIG_PCI_BOOTDELAY 0
184
185#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
186#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
187#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406
188#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
189#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart)
190#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1)
191#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
192#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
193#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
194#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
195
196#define CONFIG_PCI_4xx_PTM_OVERWRITE 1
197
198
199
200
201
202#undef CONFIG_IDE_8xx_DIRECT
203#undef CONFIG_IDE_LED
204#define CONFIG_IDE_RESET 1
205
206#define CONFIG_SYS_IDE_MAXBUS 1
207#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
208
209#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
210#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
211
212#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
213#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
214#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
215
216
217
218
219
220
221#define CONFIG_SYS_SDRAM_BASE 0x00000000
222#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
223#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
224#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
225#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
226
227#define CONFIG_PRAM 0
228
229
230
231
232
233
234#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
235
236#define CONFIG_OF_LIBFDT
237#define CONFIG_OF_BOARD_SETUP
238
239
240
241
242#define CONFIG_SYS_MAX_FLASH_BANKS 2
243#define CONFIG_SYS_MAX_FLASH_SECT 256
244
245#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
246#define CONFIG_SYS_FLASH_WRITE_TOUT 500
247
248#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
249#define CONFIG_SYS_FLASH_ADDR0 0x5555
250#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
251
252
253
254
255#define CONFIG_SYS_FLASH_READ0 0x0000
256#define CONFIG_SYS_FLASH_READ1 0x0001
257#define CONFIG_SYS_FLASH_READ2 0x0002
258
259#define CONFIG_SYS_FLASH_EMPTY_INFO
260
261#if 0
262
263
264
265#define CONFIG_ENV_IS_IN_NVRAM 1
266#define CONFIG_ENV_SIZE 0x0ff8
267#define CONFIG_ENV_ADDR \
268 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))
269
270#else
271
272#define CONFIG_ENV_IS_IN_EEPROM 1
273#define CONFIG_ENV_OFFSET 0x000
274#define CONFIG_ENV_SIZE 0x800
275
276#endif
277
278#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000
279#define CONFIG_SYS_NVRAM_SIZE (32*1024)
280#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900)
281
282
283
284
285#define CONFIG_HARD_I2C
286#define CONFIG_PPC4XX_I2C
287#define CONFIG_SYS_I2C_SPEED 400000
288#define CONFIG_SYS_I2C_SLAVE 0x7F
289
290#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
291#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
292
293#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
294#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
295
296
297#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
298
299
300
301
302
303
304
305#define FLASH_BASE0_PRELIM 0xFF800000
306#define FLASH_BASE1_PRELIM 0xFFC00000
307
308
309
310
311
312
313#define CONFIG_SYS_EBC_PB0AP 0x92015480
314#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
315
316
317#define CONFIG_SYS_EBC_PB1AP 0x92015480
318#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
319
320
321#define CONFIG_SYS_EBC_PB2AP 0x010053C0
322#define CONFIG_SYS_EBC_PB2CR 0xF0018000
323#define CONFIG_SYS_LED_ADDR 0xF0000380
324
325
326#define CONFIG_SYS_EBC_PB3AP 0x010053C0
327#define CONFIG_SYS_EBC_PB3CR 0xF011A000
328
329
330
331#define CONFIG_SYS_EBC_PB4AP 0x01805680
332#define CONFIG_SYS_EBC_PB4CR 0xF0218000
333
334
335#define CONFIG_SYS_EBC_PB5AP 0x04005B80
336#define CONFIG_SYS_EBC_PB5CR 0xF0318000
337
338
339#define CONFIG_SYS_EBC_PB6AP 0x010053C0
340#define CONFIG_SYS_EBC_PB6CR 0xF041A000
341#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
342
343
344
345
346
347#define CONFIG_SYS_FPGA_MODE 0x00
348#define CONFIG_SYS_FPGA_STATUS 0x02
349#define CONFIG_SYS_FPGA_TS 0x04
350#define CONFIG_SYS_FPGA_TS_LOW 0x06
351#define CONFIG_SYS_FPGA_TS_CAP0 0x10
352#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
353#define CONFIG_SYS_FPGA_TS_CAP1 0x14
354#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
355#define CONFIG_SYS_FPGA_TS_CAP2 0x18
356#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
357#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
358#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
359
360
361#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
362#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
363#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004
364#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
365#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
366#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
367
368
369#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
370#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
371#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
372#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
373#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
374
375#define CONFIG_SYS_FPGA_SPARTAN2 1
376#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024
377
378
379#define CONFIG_SYS_FPGA_PRG 0x04000000
380#define CONFIG_SYS_FPGA_CLK 0x02000000
381#define CONFIG_SYS_FPGA_DATA 0x01000000
382#define CONFIG_SYS_FPGA_INIT 0x00010000
383#define CONFIG_SYS_FPGA_DONE 0x00008000
384
385
386
387
388#define CONFIG_SYS_INIT_DCACHE_CS 7
389
390#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
391#define CONFIG_SYS_INIT_RAM_END 0x2000
392#define CONFIG_SYS_GBL_DATA_SIZE 128
393#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
394#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
395
396
397
398
399
400
401
402#define BOOTFLAG_COLD 0x01
403#define BOOTFLAG_WARM 0x02
404
405#endif
406