1/* 2 * (C) Copyright 2001, 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/*********************************************************** 32 * High Level Configuration Options 33 * (easy to change) 34 ***********************************************************/ 35#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 36#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 37#define CONFIG_MIP405 1 /* ...on a MIP405 board */ 38/*********************************************************** 39 * Note that it may also be a MIP405T board which is a subset of the 40 * MIP405 41 ***********************************************************/ 42/*********************************************************** 43 * WARNING: 44 * CONFIG_BOOT_PCI is only used for first boot-up and should 45 * NOT be enabled for production bootloader 46 ***********************************************************/ 47/*#define CONFIG_BOOT_PCI 1*/ 48/*********************************************************** 49 * Clock 50 ***********************************************************/ 51#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 52 53 54/* 55 * BOOTP options 56 */ 57#define CONFIG_BOOTP_BOOTFILESIZE 58#define CONFIG_BOOTP_BOOTPATH 59#define CONFIG_BOOTP_GATEWAY 60#define CONFIG_BOOTP_HOSTNAME 61 62 63/* 64 * Command line configuration. 65 */ 66#include <config_cmd_default.h> 67 68#define CONFIG_CMD_CACHE 69#define CONFIG_CMD_DATE 70#define CONFIG_CMD_DHCP 71#define CONFIG_CMD_EEPROM 72#define CONFIG_CMD_ELF 73#define CONFIG_CMD_FAT 74#define CONFIG_CMD_I2C 75#define CONFIG_CMD_IDE 76#define CONFIG_CMD_IRQ 77#define CONFIG_CMD_JFFS2 78#define CONFIG_CMD_MII 79#define CONFIG_CMD_PCI 80#define CONFIG_CMD_PING 81#define CONFIG_CMD_REGINFO 82#define CONFIG_CMD_SAVES 83#define CONFIG_CMD_BSP 84 85#if !defined(CONFIG_MIP405T) 86 #define CONFIG_CMD_USB 87#endif 88 89 90#define CONFIG_SYS_HUSH_PARSER 91#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 92/************************************************************** 93 * I2C Stuff: 94 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address 95 * 0x53. 96 * The Atmel EEPROM uses 16Bit addressing. 97 ***************************************************************/ 98 99#define CONFIG_HARD_I2C /* I2c with hardware support */ 100#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 101#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ 102#define CONFIG_SYS_I2C_SLAVE 0x7F 103 104#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ 105#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ 106/* mask of address bits that overflow into the "EEPROM chip address" */ 107#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 108#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ 109 /* 64 byte page write mode using*/ 110 /* last 6 bits of the address */ 111#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 112 113 114#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 115#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ 116#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ 117 118/*************************************************************** 119 * Definitions for Serial Presence Detect EEPROM address 120 * (to get SDRAM settings) 121 ***************************************************************/ 122/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 123#define SDRAM_EEPROM_READ_ADDRESS 0xA1 124*/ 125/************************************************************** 126 * Environment definitions 127 **************************************************************/ 128#define CONFIG_BAUDRATE 9600 /* STD Baudrate */ 129#define CONFIG_BOOTDELAY 5 130/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ 131/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ 132#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ 133 134#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ 135#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ 136 137#define CONFIG_IPADDR 10.0.0.100 138#define CONFIG_SERVERIP 10.0.0.1 139#define CONFIG_PREBOOT 140/*************************************************************** 141 * defines if the console is stored in the environment 142 ***************************************************************/ 143#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ 144/*************************************************************** 145 * defines if an overwrite_console function exists 146 *************************************************************/ 147#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 148#define CONFIG_SYS_CONSOLE_INFO_QUIET 149/*************************************************************** 150 * defines if the overwrite_console should be stored in the 151 * environment 152 **************************************************************/ 153#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 154 155/************************************************************** 156 * loads config 157 *************************************************************/ 158#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 159#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 160 161#define CONFIG_MISC_INIT_R 162/*********************************************************** 163 * Miscellaneous configurable options 164 **********************************************************/ 165#define CONFIG_SYS_LONGHELP /* undef to save memory */ 166#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 167#if defined(CONFIG_CMD_KGDB) 168#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 169#else 170#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 171#endif 172#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 173#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 175 176#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 177#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ 178 179#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 180#define CONFIG_SYS_BASE_BAUD 916667 181 182/* The following table includes the supported baudrates */ 183#define CONFIG_SYS_BAUDRATE_TABLE \ 184 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 185 57600, 115200, 230400, 460800, 921600 } 186 187#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ 188#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 189 190#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 191 192/*----------------------------------------------------------------------- 193 * PCI stuff 194 *----------------------------------------------------------------------- 195 */ 196#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 197#define PCI_HOST_FORCE 1 /* configure as pci host */ 198#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 199 200#define CONFIG_PCI /* include pci support */ 201#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ 202#define CONFIG_PCI_PNP /* pci plug-and-play */ 203 /* resource configuration */ 204#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ 205#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ 206#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 207#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ 208#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 209#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ 210#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ 211#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ 212 213/*----------------------------------------------------------------------- 214 * Start addresses for the final memory configuration 215 * (Set up by the startup code) 216 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 217 */ 218#define CONFIG_SYS_SDRAM_BASE 0x00000000 219#define CONFIG_SYS_FLASH_BASE 0xFFF80000 220#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 221#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ 222#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ 223 224/* 225 * For booting Linux, the board info and command line data 226 * have to be in the first 8 MB of memory, since this is 227 * the maximum mapped by the Linux kernel during initialization. 228 */ 229#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 230/*----------------------------------------------------------------------- 231 * FLASH organization 232 */ 233#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 234#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 235 236#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 237#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 238 239/* 240 * JFFS2 partitions 241 * 242 */ 243/* No command line, one static partition, whole device */ 244#undef CONFIG_CMD_MTDPARTS 245#define CONFIG_JFFS2_DEV "nor0" 246#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 247#define CONFIG_JFFS2_PART_OFFSET 0x00000000 248 249/* mtdparts command line support */ 250/* Note: fake mtd_id used, no linux mtd map file */ 251/* 252#define CONFIG_CMD_MTDPARTS 253#define MTDIDS_DEFAULT "nor0=mip405-0" 254#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" 255*/ 256 257/*----------------------------------------------------------------------- 258 * Logbuffer Configuration 259 */ 260#undef CONFIG_LOGBUFFER /* supported but not enabled */ 261/*----------------------------------------------------------------------- 262 * Bootcountlimit Configuration 263 */ 264#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ 265 266/*----------------------------------------------------------------------- 267 * POST Configuration 268 */ 269#if 0 /* enable this if POST is desired (is supported but not enabled) */ 270#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 271 CONFIG_SYS_POST_CPU | \ 272 CONFIG_SYS_POST_RTC | \ 273 CONFIG_SYS_POST_I2C) 274 275#endif 276/* 277 * Init Memory Controller: 278 */ 279#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ 280#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ 281/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ 282#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ 283 284#define CONFIG_BOARD_EARLY_INIT_F 1 285 286/* Peripheral Bus Mapping */ 287#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ 288#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ 289#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ 290 291#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 292#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 293 294 295/*----------------------------------------------------------------------- 296 * Definitions for initial stack pointer and data area (in On Chip SRAM) 297 */ 298#define CONFIG_SYS_TEMP_STACK_OCM 1 299#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 300#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 301#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ 302#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */ 303#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 304#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 305/* reserve some memory for POST and BOOT limit info */ 306#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 307 308#ifdef CONFIG_POST /* reserve one word for POST Info */ 309#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4) 310#endif 311 312#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ 313#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12) 314#endif 315 316/* 317 * Internal Definitions 318 * 319 * Boot Flags 320 */ 321#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 322#define BOOTFLAG_WARM 0x02 /* Software reboot */ 323 324 325/*********************************************************************** 326 * External peripheral base address 327 ***********************************************************************/ 328#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 329 330/*********************************************************************** 331 * Last Stage Init 332 ***********************************************************************/ 333#define CONFIG_LAST_STAGE_INIT 334/************************************************************ 335 * Ethernet Stuff 336 ***********************************************************/ 337#define CONFIG_PPC4xx_EMAC 338#define CONFIG_MII 1 /* MII PHY management */ 339#define CONFIG_PHY_ADDR 1 /* PHY address */ 340#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ 341#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ 342#define CONFIG_NET_MULTI 343/************************************************************ 344 * RTC 345 ***********************************************************/ 346#define CONFIG_RTC_MC146818 347#undef CONFIG_WATCHDOG /* watchdog disabled */ 348 349/************************************************************ 350 * IDE/ATA stuff 351 ************************************************************/ 352#if defined(CONFIG_MIP405T) 353#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ 354#else 355#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ 356#endif 357 358#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ 359 360#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ 361#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 362#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ 363#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 364#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 365#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 366 367#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 368#undef CONFIG_IDE_LED /* no led for ide supported */ 369#define CONFIG_IDE_RESET /* reset for ide supported... */ 370#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ 371#define CONFIG_SUPPORT_VFAT 372/************************************************************ 373 * ATAPI support (experimental) 374 ************************************************************/ 375#define CONFIG_ATAPI /* enable ATAPI Support */ 376 377/************************************************************ 378 * DISK Partition support 379 ************************************************************/ 380#define CONFIG_DOS_PARTITION 381#define CONFIG_MAC_PARTITION 382#define CONFIG_ISO_PARTITION /* Experimental */ 383 384/************************************************************ 385 * Keyboard support 386 ************************************************************/ 387#undef CONFIG_ISA_KEYBOARD 388 389/************************************************************ 390 * Video support 391 ************************************************************/ 392#define CONFIG_VIDEO /*To enable video controller support */ 393#define CONFIG_VIDEO_CT69000 394#define CONFIG_CFB_CONSOLE 395#define CONFIG_VIDEO_LOGO 396#define CONFIG_CONSOLE_EXTRA_INFO 397#define CONFIG_VGA_AS_SINGLE_DEVICE 398#define CONFIG_VIDEO_SW_CURSOR 399#undef CONFIG_VIDEO_ONBOARD 400/************************************************************ 401 * USB support EXPERIMENTAL 402 ************************************************************/ 403#if !defined(CONFIG_MIP405T) 404#define CONFIG_USB_UHCI 405#define CONFIG_USB_KEYBOARD 406#define CONFIG_USB_STORAGE 407 408/* Enable needed helper functions */ 409#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ 410#endif 411/************************************************************ 412 * Debug support 413 ************************************************************/ 414#if defined(CONFIG_CMD_KGDB) 415#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 416#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 417#endif 418 419/************************************************************ 420 * support BZIP2 compression 421 ************************************************************/ 422#define CONFIG_BZIP2 1 423 424/************************************************************ 425 * Ident 426 ************************************************************/ 427 428#define VERSION_TAG "released" 429#if !defined(CONFIG_MIP405T) 430#define CONFIG_ISO_STRING "MEV-10072-001" 431#else 432#define CONFIG_ISO_STRING "MEV-10082-001" 433#endif 434 435#if !defined(CONFIG_BOOT_PCI) 436#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG 437#else 438#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version" 439#endif 440 441 442#endif /* __CONFIG_H */ 443