LXR uboot/include/configs/PMC405.h

   1/*
   2 * (C) Copyright 2001-2004
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __CONFIG_H
  25#define __CONFIG_H
  26
  27/*
  28 * High Level Configuration Options
  29 */
  30
  31#define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  32#define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  33#define CONFIG_PMC405           1       /* ...on a PMC405 board         */
  34
  35#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  36#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  37
  38#define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  39
  40#define CONFIG_BAUDRATE         9600
  41#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  42
  43/* Only interrupt boot if space is pressed. */
  44#define CONFIG_AUTOBOOT_KEYED 1
  45#define CONFIG_AUTOBOOT_PROMPT  \
  46        "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  47#undef CONFIG_AUTOBOOT_DELAY_STR
  48#define CONFIG_AUTOBOOT_STOP_STR " "
  49
  50#undef CONFIG_BOOTARGS
  51#undef CONFIG_BOOTCOMMAND
  52
  53#define CONFIG_PREBOOT                  /* enable preboot variable      */
  54
  55#define CFG_BOOTM_LEN           0x1000000 /* support booting of huge images */
  56
  57#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  58#define CONFIG_SYS_LOADS_BAUD_CHANGE 1  /* allow baudrate change        */
  59
  60#define CONFIG_NET_MULTI        1
  61#undef  CONFIG_HAS_ETH1
  62
  63#define CONFIG_PPC4xx_EMAC
  64#define CONFIG_MII              1       /* MII PHY management           */
  65#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  66#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  67#define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
  68
  69/*
  70 * BOOTP options
  71 */
  72#define CONFIG_BOOTP_BOOTFILESIZE
  73#define CONFIG_BOOTP_BOOTPATH
  74#define CONFIG_BOOTP_GATEWAY
  75#define CONFIG_BOOTP_HOSTNAME
  76
  77/*
  78 * Command line configuration.
  79 */
  80#include <config_cmd_default.h>
  81
  82#define CONFIG_CMD_BSP
  83#define CONFIG_CMD_PCI
  84#define CONFIG_CMD_IRQ
  85#define CONFIG_CMD_ELF
  86#define CONFIG_CMD_DATE
  87#define CONFIG_CMD_JFFS2
  88#define CONFIG_CMD_MII
  89#define CONFIG_CMD_I2C
  90#define CONFIG_CMD_PING
  91#define CONFIG_CMD_UNIVERSE
  92#define CONFIG_CMD_EEPROM
  93
  94#define CONFIG_MAC_PARTITION
  95#define CONFIG_DOS_PARTITION
  96
  97#undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  98
  99#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible */
 100#define CONFIG_SYS_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address */
 101
 102#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 103
 104/*
 105 * Miscellaneous configurable options
 106 */
 107#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 108#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 109
 110#undef CONFIG_SYS_HUSH_PARSER                   /* use "hush" command parser */
 111#ifdef CONFIG_SYS_HUSH_PARSER
 112#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 113#endif
 114
 115#if defined(CONFIG_CMD_KGDB)
 116#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 117#else
 118#define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 119#endif
 120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 121#define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 122#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
 123
 124#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
 125
 126#define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console info */
 127
 128#define CONFIG_AUTO_COMPLETE            1       /* add autocompletion support */
 129
 130#define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 131#define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 132
 133#undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external serial clock */
 134#define CONFIG_SYS_BASE_BAUD    806400
 135
 136/* The following table includes the supported baudrates */
 137#define CONFIG_SYS_BAUDRATE_TABLE       \
 138        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 139
 140#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 141#define CONFIG_SYS_EXTBDINFO    1       /* To use extended board_into (bd_t) */
 142
 143#define CONFIG_SYS_HZ           1000    /* decrementer freq: 1 ms ticks */
 144
 145#define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 146#define CONFIG_LOOPW            1       /* enable loopw command */
 147
 148#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 149
 150#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 151
 152#define CONFIG_SYS_RX_ETH_BUFFER        16
 153
 154/*
 155 * PCI stuff
 156 */
 157#define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
 158#define PCI_HOST_FORCE          1       /* configure as pci host        */
 159#define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 160
 161#define CONFIG_PCI                      /* include pci support          */
 162#define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 163#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 164                                        /* resource configuration       */
 165
 166#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 167
 168#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
 169
 170#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh */
 171#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
 172#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
 173#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
 174
 175#define CONFIG_SYS_PCI_CLASSCODE       0x0b20 /* Processor/PPC */
 176
 177#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram      */
 178#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
 179#define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address */
 180#define CONFIG_SYS_PCI_PTM2LA  0xef000000       /* point to internal regs */
 181#define CONFIG_SYS_PCI_PTM2MS  0xff000001       /* 16MB, enable */
 182#define CONFIG_SYS_PCI_PTM2PCI 0x00000000       /* Host: use this pci address */
 183
 184#define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 185
 186/*
 187 * Start addresses for the final memory configuration
 188 * (Set up by the startup code)
 189 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 190 */
 191#define CONFIG_SYS_SDRAM_BASE           0x00000000
 192#define CONFIG_SYS_MONITOR_BASE         TEXT_BASE
 193#define CONFIG_SYS_MONITOR_LEN          (~(TEXT_BASE) + 1)
 194#define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* 128 kB for malloc() */
 195
 196#define CONFIG_PRAM                     0 /* use pram variable to overwrite */
 197
 198/*
 199 * For booting Linux, the board info and command line data
 200 * have to be in the first 8 MB of memory, since this is
 201 * the maximum mapped by the Linux kernel during initialization.
 202 */
 203#define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 204
 205/*
 206 * FLASH organization
 207 */
 208#define CONFIG_SYS_FLASH_BASE           0xFE000000
 209#define CONFIG_SYS_FLASH_INCREMENT      0x01000000
 210
 211#define CONFIG_SYS_FLASH_CFI            1 /* Flash is CFI conformant */
 212#define CONFIG_FLASH_CFI_DRIVER         1 /* Use the common driver */
 213#define CONFIG_SYS_FLASH_PROTECTION     1 /* don't use hardware protection */
 214#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
 215#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
 216#define CONFIG_SYS_MAX_FLASH_BANKS      2 /* max num of flash banks */
 217#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 218                        CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
 219#define CONFIG_SYS_MAX_FLASH_SECT       128 /* max num of sects on one chip */
 220#define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on fli */
 221
 222/*
 223 * Environment Variable setup
 224 */
 225#define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 226
 227/* environment starts at the beginning of the EEPROM */
 228#define CONFIG_ENV_OFFSET       0x000
 229#define CONFIG_ENV_SIZE         0x800 /* 2048 bytes may be used for env vars */
 230
 231#define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500      /* NVRAM base address */
 232#define CONFIG_SYS_NVRAM_SIZE           242             /* NVRAM size */
 233
 234/*
 235 * I2C EEPROM (CAT24WC16) for environment
 236 */
 237#define CONFIG_HARD_I2C                 /* I2c with hardware support */
 238#define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 239#define CONFIG_SYS_I2C_SPEED            100000 /* I2C speed and slave address */
 240#define CONFIG_SYS_I2C_SLAVE            0x7F
 241
 242#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24W16 */
 243#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 244/* mask of address bits that overflow into the "EEPROM chip address" */
 245#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 246#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24W16 has */
 247                                        /* 16 byte page write mode using*/
 248                                        /* last 4 bits of the address */
 249
 250#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
 251
 252/*
 253 * External Bus Controller (EBC) Setup
 254 */
 255#define FLASH0_BA       0xFF000000      /* FLASH 0 Base Address */
 256#define FLASH1_BA       0xFE000000      /* FLASH 1 Base Address */
 257#define CAN_BA          0xF0000000      /* CAN Base Addres      */
 258#define RTC_BA          0xF0000500      /* RTC Base Address     */
 259#define NVRAM_BA        0xF0200000      /* NVRAM Base Address   */
 260
 261/* Memory Bank 0 (Flash Bank 0) initialization */
 262#define CONFIG_SYS_EBC_PB0AP    0x92015480
 263/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
 264#define CONFIG_SYS_EBC_PB0CR    (FLASH0_BA | 0x9A000)
 265
 266/* Memory Bank 1 (Flash Bank 1) initialization */
 267#define CONFIG_SYS_EBC_PB1AP    0x92015480
 268/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 269#define CONFIG_SYS_EBC_PB1CR    (FLASH1_BA | 0x9A000)
 270
 271/* Memory Bank 2 (CAN0, 1, RTC) initialization */
 272/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
 273#define CONFIG_SYS_EBC_PB2AP    0x03000440
 274/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 275#define CONFIG_SYS_EBC_PB2CR    (CAN_BA | 0x18000)
 276
 277/* Memory Bank 3 -> unused */
 278
 279/* Memory Bank 4 (NVRAM) initialization */
 280/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
 281#define CONFIG_SYS_EBC_PB4AP    0x03000440
 282/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 283#define CONFIG_SYS_EBC_PB4CR    (NVRAM_BA | 0x18000)
 284
 285/*
 286 * FPGA stuff
 287 */
 288/* FPGA program pin configuration */
 289#define CONFIG_SYS_FPGA_PRG             0x04000000 /* JTAG TMS pin (output) */
 290#define CONFIG_SYS_FPGA_CLK             0x02000000 /* JTAG TCK pin (output) */
 291#define CONFIG_SYS_FPGA_DATA            0x01000000 /* JTAG TDO pin (output) */
 292#define CONFIG_SYS_FPGA_INIT            0x00010000 /* unused (ppc input) */
 293#define CONFIG_SYS_FPGA_DONE            0x00008000 /* JTAG TDI pin (input) */
 294
 295/* pass Ethernet MAC to VxWorks */
 296#define CONFIG_SYS_VXWORKS_MAC_PTR      0x00000000
 297
 298/*
 299 * GPIOs
 300 */
 301#define CONFIG_SYS_VPEN                 (0x80000000 >>  3) /* GPIO3 */
 302#define CONFIG_SYS_NONMONARCH           (0x80000000 >> 14) /* GPIO14 */
 303#define CONFIG_SYS_XEREADY              (0x80000000 >> 15) /* GPIO15 */
 304#define CONFIG_SYS_INTA_FAKE            (0x80000000 >> 19) /* GPIO19 */
 305#define CONFIG_SYS_SELF_RST             (0x80000000 >> 21) /* GPIO21 */
 306#define CONFIG_SYS_REV1_2               (0x80000000 >> 23) /* GPIO23 */
 307
 308/*
 309 * Definitions for initial stack pointer and data area (in data cache)
 310 */
 311
 312/* use on chip memory (OCM) for temperary stack until sdram is tested */
 313#define CONFIG_SYS_TEMP_STACK_OCM       1
 314
 315/* On Chip Memory location */
 316#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 317#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 318
 319/* inside of SDRAM */
 320#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR
 321
 322/* End of used area in RAM */
 323#define CONFIG_SYS_INIT_RAM_END         CONFIG_SYS_OCM_DATA_SIZE
 324
 325/* size in bytes reserved for initial data */
 326#define CONFIG_SYS_GBL_DATA_SIZE        128
 327#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - \
 328                                         CONFIG_SYS_GBL_DATA_SIZE)
 329#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 330
 331/*
 332 * Internal Definitions
 333 *
 334 * Boot Flags
 335 */
 336#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 337#define BOOTFLAG_WARM   0x02            /* Software reboot */
 338
 339#define CONFIG_OF_LIBFDT
 340#define CONFIG_OF_BOARD_SETUP
 341
 342#endif /* __CONFIG_H */
 343