LXR uboot/include/configs/PMC440.h

   1/*
   2 * (C) Copyright 2007-2008
   3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4 * Based on the sequoia configuration file.
   5 *
   6 * (C) Copyright 2006-2007
   7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8 *
   9 * (C) Copyright 2006
  10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  11 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29/************************************************************************
  30 * PMC440.h - configuration for esd PMC440 boards
  31 ***********************************************************************/
  32#ifndef __CONFIG_H
  33#define __CONFIG_H
  34
  35/*-----------------------------------------------------------------------
  36 * High Level Configuration Options
  37 *----------------------------------------------------------------------*/
  38#define CONFIG_440EPX           1       /* Specific PPC440EPx   */
  39#define CONFIG_440              1       /* ... PPC440 family    */
  40#define CONFIG_4xx              1       /* ... PPC4xx family    */
  41
  42#define CONFIG_SYS_CLK_FREQ     33333400
  43
  44#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
  45#define CONFIG_4xx_DCACHE               /* enable dcache        */
  46#endif
  47
  48#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f */
  49#define CONFIG_MISC_INIT_F      1
  50#define CONFIG_MISC_INIT_R      1       /* Call misc_init_r     */
  51#define CONFIG_BOARD_TYPES      1       /* support board types  */
  52/*-----------------------------------------------------------------------
  53 * Base addresses -- Note these are effective addresses where the
  54 * actual resources get mapped (not physical addresses)
  55 *----------------------------------------------------------------------*/
  56#define CONFIG_SYS_MONITOR_LEN          (384  * 1024)   /* Reserve 384 kB for Monitor   */
  57#define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserve 256 kB for malloc()  */
  58
  59#define CONFIG_PRAM             0       /* use pram variable to overwrite */
  60
  61#define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  62#define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  63#define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  64#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  65#define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  66#define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  67#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  68#define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  69#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  70#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  71#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  72#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  73#define CONFIG_SYS_PCI_MEMSIZE          0x80000000      /* 2GB! */
  74
  75/* Don't change either of these */
  76#define CONFIG_SYS_PERIPHERAL_BASE      0xef600000      /* internal peripherals */
  77
  78#define CONFIG_SYS_USB2D0_BASE          0xe0000100
  79#define CONFIG_SYS_USB_DEVICE           0xe0000000
  80#define CONFIG_SYS_USB_HOST             0xe0000400
  81#define CONFIG_SYS_FPGA_BASE0           0xef000000      /* 32 bit */
  82#define CONFIG_SYS_FPGA_BASE1           0xef100000      /* 16 bit */
  83#define CONFIG_SYS_RESET_BASE           0xef200000
  84
  85/*-----------------------------------------------------------------------
  86 * Initial RAM & stack pointer
  87 *----------------------------------------------------------------------*/
  88/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  89#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  90#define CONFIG_SYS_INIT_RAM_END (4 << 10)
  91#define CONFIG_SYS_GBL_DATA_SIZE        256     /* num bytes initial data */
  92#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  93#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_POST_WORD_ADDR
  94
  95/*-----------------------------------------------------------------------
  96 * Serial Port
  97 *----------------------------------------------------------------------*/
  98#undef CONFIG_SYS_EXT_SERIAL_CLOCK
  99#define CONFIG_BAUDRATE         115200
 100#define CONFIG_SERIAL_MULTI     1
 101#undef CONFIG_UART1_CONSOLE     /* console on front panel */
 102
 103#define CONFIG_SYS_BAUDRATE_TABLE                                               \
 104        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 105
 106/*-----------------------------------------------------------------------
 107 * Environment
 108 *----------------------------------------------------------------------*/
 109#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 110#define CONFIG_ENV_IS_IN_EEPROM 1       /* use FLASH for environment vars */
 111#else
 112#define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars */
 113#define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 114#endif
 115
 116/*-----------------------------------------------------------------------
 117 * RTC
 118 *----------------------------------------------------------------------*/
 119#define CONFIG_RTC_RX8025
 120
 121/*-----------------------------------------------------------------------
 122 * FLASH related
 123 *----------------------------------------------------------------------*/
 124#define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible  */
 125#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver        */
 126
 127#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 128
 129#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 130#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 131
 132#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 133#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 134
 135#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 136#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 137
 138#define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
 139#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 140
 141#ifdef CONFIG_ENV_IS_IN_FLASH
 142#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 143#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 144#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 145
 146/* Address and size of Redundant Environment Sector     */
 147#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 148#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 149#endif
 150
 151#ifdef CONFIG_ENV_IS_IN_EEPROM
 152#define CONFIG_ENV_OFFSET               0       /* environment starts at the beginning of the EEPROM */
 153#define CONFIG_ENV_SIZE         0x1000  /* 4096 bytes may be used for env vars */
 154#endif
 155
 156/*
 157 * IPL (Initial Program Loader, integrated inside CPU)
 158 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 159 *
 160 * SPL (Secondary Program Loader)
 161 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 162 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 163 * controller and the NAND controller so that the special U-Boot image can be
 164 * loaded from NAND to SDRAM.
 165 *
 166 * NUB (NAND U-Boot)
 167 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 168 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 169 *
 170 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 171 * set up. While still running from cache, I experienced problems accessing
 172 * the NAND controller. sr - 2006-08-25
 173 */
 174#if defined (CONFIG_NAND_U_BOOT)
 175#define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 176#define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 177#define CONFIG_SYS_NAND_BOOT_SPL_DST    (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here    */
 178#define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 179#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
 180#define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 181
 182/*
 183 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 184 */
 185#define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 186#define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 187
 188/*
 189 * Now the NAND chip has to be defined (no autodetection used!)
 190 */
 191#define CONFIG_SYS_NAND_PAGE_SIZE       512     /* NAND chip page size          */
 192#define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10) /* NAND chip block size      */
 193#define CONFIG_SYS_NAND_PAGE_COUNT      32      /* NAND chip page count         */
 194#define CONFIG_SYS_NAND_BAD_BLOCK_POS   5       /* Location of bad block marker */
 195#undef CONFIG_SYS_NAND_4_ADDR_CYCLE             /* No fourth addr used (<=32MB) */
 196
 197#define CONFIG_SYS_NAND_ECCSIZE 256
 198#define CONFIG_SYS_NAND_ECCBYTES        3
 199#define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 200#define CONFIG_SYS_NAND_OOBSIZE 16
 201#define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 202#define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 203#endif
 204
 205#ifdef CONFIG_ENV_IS_IN_NAND
 206/*
 207 * For NAND booting the environment is embedded in the U-Boot image. Please take
 208 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 209 */
 210#define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 211#define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 212#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 213#endif
 214
 215/*-----------------------------------------------------------------------
 216 * DDR SDRAM
 217 *----------------------------------------------------------------------*/
 218#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 219#define CONFIG_DDR_DATA_EYE     /* use DDR2 optimization        */
 220#endif
 221#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
 222                                                  /* 440EPx errata CHIP 11 */
 223
 224/*-----------------------------------------------------------------------
 225 * I2C
 226 *----------------------------------------------------------------------*/
 227#define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 228#undef  CONFIG_SOFT_I2C         /* I2C bit-banged               */
 229#define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 230#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 231#define CONFIG_SYS_I2C_SLAVE            0x7F
 232
 233#define CONFIG_I2C_MULTI_BUS    1
 234
 235#define CONFIG_SYS_I2C_MULTI_EEPROMS
 236
 237#define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 238#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 239#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 240#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 241#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 242
 243#define CONFIG_SYS_EEPROM_WREN                  1
 244#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 245
 246/*
 247 * standard dtt sensor configuration - bottom bit will determine local or
 248 * remote sensor of the TMP401
 249 */
 250#define CONFIG_DTT_SENSORS              { 0, 1 }
 251
 252/*
 253 * The PMC440 uses a TI TMP401 temperature sensor. This part
 254 * is basically compatible to the ADM1021 that is supported
 255 * by U-Boot.
 256 *
 257 * - i2c addr 0x4c
 258 * - conversion rate 0x02 = 0.25 conversions/second
 259 * - ALERT ouput disabled
 260 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 261 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 262 */
 263#define CONFIG_DTT_ADM1021
 264#define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 265
 266#define CONFIG_PREBOOT          "echo Add \\\"run fpga\\\" and "        \
 267                                "\\\"painit\\\" to preboot command"
 268
 269#undef  CONFIG_BOOTARGS
 270
 271/* Setup some board specific values for the default environment variables */
 272#define CONFIG_HOSTNAME         pmc440
 273#define CONFIG_SYS_BOOTFILE     "bootfile=/tftpboot/pmc440/uImage\0"
 274#define CONFIG_SYS_ROOTPATH     "rootpath=/opt/eldk/ppc_4xxFP\0"
 275
 276#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 277        CONFIG_SYS_BOOTFILE                                             \
 278        CONFIG_SYS_ROOTPATH                                             \
 279        "fdt_file=/tftpboot/pmc440/pmc440.dtb\0"                        \
 280        "netdev=eth0\0"                                                 \
 281        "ethrotate=no\0"                                                \
 282        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 283        "nfsroot=${serverip}:${rootpath}\0"                             \
 284        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 285        "addip=setenv bootargs ${bootargs} "                            \
 286                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 287                ":${hostname}:${netdev}:off panic=1\0"                  \
 288        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 289        "addmisc=setenv bootargs ${bootargs} mem=${mem}\0"              \
 290        "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
 291        "nand_boot_fdt=run nandargs addip addtty addmisc;"              \
 292                "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 293        "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"                \
 294                "tftp  ${fdt_addr_r} ${fdt_file};"                      \
 295                "run nfsargs addip addtty addmisc;"                     \
 296                "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 297        "kernel_addr=ffc00000\0"                                        \
 298        "kernel_addr_r=200000\0"                                        \
 299        "fpga_addr=fff00000\0"                                          \
 300        "fdt_addr=fff80000\0"                                           \
 301        "fdt_addr_r=800000\0"                                           \
 302        "fpga=fpga loadb 0 ${fpga_addr}\0"                              \
 303        "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"                \
 304        "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"   \
 305                "cp.b 200000 fffa0000 60000\0"                          \
 306        ""
 307
 308#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 309
 310#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 311#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 312
 313#define CONFIG_PPC4xx_EMAC
 314#define CONFIG_IBM_EMAC4_V4     1
 315#define CONFIG_MII              1       /* MII PHY management           */
 316#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 317
 318#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 319
 320#define CONFIG_HAS_ETH0
 321#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 322
 323#define CONFIG_NET_MULTI        1
 324#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 325#define CONFIG_PHY1_ADDR        1
 326#define CONFIG_RESET_PHY_R      1
 327
 328/* USB */
 329#define CONFIG_USB_OHCI_NEW
 330#define CONFIG_USB_STORAGE
 331#define CONFIG_SYS_OHCI_BE_CONTROLLER
 332
 333#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 334#define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 335#define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 336#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 337#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 338
 339/* Comment this out to enable USB 1.1 device */
 340#define USB_2_0_DEVICE
 341
 342/* Partitions */
 343#define CONFIG_MAC_PARTITION
 344#define CONFIG_DOS_PARTITION
 345#define CONFIG_ISO_PARTITION
 346
 347#include <config_cmd_default.h>
 348
 349#define CONFIG_CMD_BSP
 350#define CONFIG_CMD_DATE
 351#define CONFIG_CMD_DHCP
 352#define CONFIG_CMD_DTT
 353#define CONFIG_CMD_EEPROM
 354#define CONFIG_CMD_ELF
 355#define CONFIG_CMD_FAT
 356#define CONFIG_CMD_I2C
 357#define CONFIG_CMD_MII
 358#define CONFIG_CMD_NAND
 359#define CONFIG_CMD_NET
 360#define CONFIG_CMD_NFS
 361#define CONFIG_CMD_PCI
 362#define CONFIG_CMD_PING
 363#define CONFIG_CMD_USB
 364#define CONFIG_CMD_REGINFO
 365
 366/* POST support */
 367#define CONFIG_POST             (CONFIG_SYS_POST_MEMORY |       \
 368                                 CONFIG_SYS_POST_CPU    |       \
 369                                 CONFIG_SYS_POST_UART   |       \
 370                                 CONFIG_SYS_POST_I2C    |       \
 371                                 CONFIG_SYS_POST_CACHE  |       \
 372                                 CONFIG_SYS_POST_FPU    |       \
 373                                 CONFIG_SYS_POST_ETHER  |       \
 374                                 CONFIG_SYS_POST_SPR)
 375
 376#define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 377#define CONFIG_LOGBUFFER
 378#define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 379
 380#define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 381
 382#define CONFIG_SUPPORT_VFAT
 383
 384/*-----------------------------------------------------------------------
 385 * Miscellaneous configurable options
 386 *----------------------------------------------------------------------*/
 387#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 388#define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 389#if defined(CONFIG_CMD_KGDB)
 390#define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 391#else
 392#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 393#endif
 394#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 395#define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 396#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 397
 398#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on          */
 399#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM       */
 400
 401#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address      */
 402#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 403
 404#define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 405
 406#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 407#define CONFIG_LOOPW            1       /* enable loopw command         */
 408#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 409#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 410#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 411
 412#define CONFIG_AUTOBOOT_KEYED   1
 413#define CONFIG_AUTOBOOT_PROMPT  \
 414        "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 415#undef CONFIG_AUTOBOOT_DELAY_STR
 416#define CONFIG_AUTOBOOT_STOP_STR " "
 417
 418/*-----------------------------------------------------------------------
 419 * PCI stuff
 420 *----------------------------------------------------------------------*/
 421/* General PCI */
 422#define CONFIG_PCI              /* include pci support          */
 423#define CONFIG_PCI_PNP          /* do (not) pci plug-and-play   */
 424#define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 425#define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup  */
 426#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 427
 428/* Board-specific PCI */
 429#define CONFIG_SYS_PCI_TARGET_INIT
 430#define CONFIG_SYS_PCI_MASTER_INIT
 431#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 432
 433/* PCI identification */
 434#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 435#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441      /* PCI Device ID: Non-Monarch */
 436#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
 437/* for weak __pci_target_init() */
 438#define CONFIG_SYS_PCI_SUBSYS_ID        CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
 439#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH     PCI_CLASS_PROCESSOR_POWERPC
 440#define CONFIG_SYS_PCI_CLASSCODE_MONARCH        PCI_CLASS_BRIDGE_HOST
 441
 442/*
 443 * For booting Linux, the board info and command line data
 444 * have to be in the first 8 MB of memory, since this is
 445 * the maximum mapped by the Linux kernel during initialization.
 446 */
 447#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 448
 449/*-----------------------------------------------------------------------
 450 * FPGA stuff
 451 *----------------------------------------------------------------------*/
 452#define CONFIG_FPGA
 453#define CONFIG_FPGA_XILINX
 454#define CONFIG_FPGA_SPARTAN2
 455#define CONFIG_FPGA_SPARTAN3
 456
 457#define CONFIG_FPGA_COUNT       2
 458/*-----------------------------------------------------------------------
 459 * External Bus Controller (EBC) Setup
 460 *----------------------------------------------------------------------*/
 461
 462/*
 463 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 464 */
 465#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 466#define CONFIG_SYS_NAND_CS              2       /* NAND chip connected to CSx   */
 467
 468/* Memory Bank 0 (NOR-FLASH) initialization */
 469#define CONFIG_SYS_EBC_PB0AP            0x03017200
 470#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 471
 472/* Memory Bank 2 (NAND-FLASH) initialization */
 473#define CONFIG_SYS_EBC_PB2AP            0x018003c0
 474#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 475#else
 476#define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 477/* Memory Bank 2 (NOR-FLASH) initialization */
 478#define CONFIG_SYS_EBC_PB2AP            0x03017200
 479#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 480
 481/* Memory Bank 0 (NAND-FLASH) initialization */
 482#define CONFIG_SYS_EBC_PB0AP            0x018003c0
 483#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 484#endif
 485
 486/* Memory Bank 1 (RESET) initialization */
 487#define CONFIG_SYS_EBC_PB1AP            0x7f817200 /* 0x03017200 */
 488#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_RESET_BASE | 0x1c000)
 489
 490/* Memory Bank 4 (FPGA / 32Bit) initialization */
 491#define CONFIG_SYS_EBC_PB4AP            0x03840f40      /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
 492#define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_FPGA_BASE0 | 0x1c000)       /* BS=1M,BU=R/W,BW=32bit */
 493
 494/* Memory Bank 5 (FPGA / 16Bit) initialization */
 495#define CONFIG_SYS_EBC_PB5AP            0x03840f40      /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
 496#define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_FPGA_BASE1 | 0x1a000)       /* BS=1M,BU=R/W,BW=16bit */
 497
 498/*-----------------------------------------------------------------------
 499 * NAND FLASH
 500 *----------------------------------------------------------------------*/
 501#define CONFIG_SYS_MAX_NAND_DEVICE      1
 502#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 503#define CONFIG_SYS_NAND_SELECT_DEVICE   1 /* nand driver supports mutipl. chips */
 504#define CONFIG_SYS_NAND_QUIET_TEST      1
 505
 506/*
 507 * Internal Definitions
 508 *
 509 * Boot Flags
 510 */
 511#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 512#define BOOTFLAG_WARM   0x02    /* Software reboot                      */
 513
 514#if defined(CONFIG_CMD_KGDB)
 515#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 516#define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 517#endif
 518
 519/* pass open firmware flat tree */
 520#define CONFIG_OF_LIBFDT        1
 521#define CONFIG_OF_BOARD_SETUP   1
 522
 523#define CONFIG_API              1
 524
 525#endif /* __CONFIG_H */
 526