1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC860 1 37#define CONFIG_MPC860T 1 38#define CONFIG_MPC862 1 39 40#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ 41 42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 43#define CONFIG_SYS_SMC_RXBUFLEN 128 44#define CONFIG_SYS_MAXIDLE 10 45#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 46 47#define CONFIG_BOOTCOUNT_LIMIT 48 49#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 50 51#define CONFIG_BOARD_TYPES 1 /* support board types */ 52 53#define CONFIG_PREBOOT "echo;" \ 54 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 55 "echo" 56 57#undef CONFIG_BOOTARGS 58 59#define CONFIG_EXTRA_ENV_SETTINGS \ 60 "netdev=eth0\0" \ 61 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 62 "nfsroot=${serverip}:${rootpath}\0" \ 63 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 64 "addip=setenv bootargs ${bootargs} " \ 65 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 66 ":${hostname}:${netdev}:off panic=1\0" \ 67 "flash_nfs=run nfsargs addip;" \ 68 "bootm ${kernel_addr}\0" \ 69 "flash_self=run ramargs addip;" \ 70 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 71 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 72 "rootpath=/opt/eldk/ppc_8xx\0" \ 73 "hostname=TQM862L\0" \ 74 "bootfile=TQM862L/uImage\0" \ 75 "fdt_addr=40040000\0" \ 76 "kernel_addr=40060000\0" \ 77 "ramdisk_addr=40200000\0" \ 78 "u-boot=TQM862L/u-image.bin\0" \ 79 "load=tftp 200000 ${u-boot}\0" \ 80 "update=prot off 40000000 +${filesize};" \ 81 "era 40000000 +${filesize};" \ 82 "cp.b 200000 40000000 ${filesize};" \ 83 "sete filesize;save\0" \ 84 "" 85#define CONFIG_BOOTCOMMAND "run flash_self" 86 87#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 88#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 89 90#undef CONFIG_WATCHDOG /* watchdog disabled */ 91 92#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 93 94#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 95 96/* 97 * BOOTP options 98 */ 99#define CONFIG_BOOTP_SUBNETMASK 100#define CONFIG_BOOTP_GATEWAY 101#define CONFIG_BOOTP_HOSTNAME 102#define CONFIG_BOOTP_BOOTPATH 103#define CONFIG_BOOTP_BOOTFILESIZE 104 105 106#define CONFIG_MAC_PARTITION 107#define CONFIG_DOS_PARTITION 108 109#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 110 111 112/* 113 * Command line configuration. 114 */ 115#include <config_cmd_default.h> 116 117#define CONFIG_CMD_ASKENV 118#define CONFIG_CMD_DATE 119#define CONFIG_CMD_DHCP 120#define CONFIG_CMD_ELF 121#define CONFIG_CMD_EXT2 122#define CONFIG_CMD_IDE 123#define CONFIG_CMD_JFFS2 124#define CONFIG_CMD_NFS 125#define CONFIG_CMD_SNTP 126 127 128#define CONFIG_NETCONSOLE 129 130 131/* 132 * Miscellaneous configurable options 133 */ 134#define CONFIG_SYS_LONGHELP /* undef to save memory */ 135#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 136 137#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 138#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 139#ifdef CONFIG_SYS_HUSH_PARSER 140#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 141#endif 142 143#if defined(CONFIG_CMD_KGDB) 144#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 145#else 146#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 147#endif 148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 151 152#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 153#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 154 155#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 156 157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 158 159#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 160 161/* 162 * Low Level Configuration Settings 163 * (address mappings, register initial values, etc.) 164 * You should know what you are doing if you make changes here. 165 */ 166/*----------------------------------------------------------------------- 167 * Internal Memory Mapped Register 168 */ 169#define CONFIG_SYS_IMMR 0xFFF00000 170 171/*----------------------------------------------------------------------- 172 * Definitions for initial stack pointer and data area (in DPRAM) 173 */ 174#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 175#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 176#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 177#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 178#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 180/*----------------------------------------------------------------------- 181 * Start addresses for the final memory configuration 182 * (Set up by the startup code) 183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 184 */ 185#define CONFIG_SYS_SDRAM_BASE 0x00000000 186#define CONFIG_SYS_FLASH_BASE 0x40000000 187#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 188#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 189#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 190 191/* 192 * For booting Linux, the board info and command line data 193 * have to be in the first 8 MB of memory, since this is 194 * the maximum mapped by the Linux kernel during initialization. 195 */ 196#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 197 198/*----------------------------------------------------------------------- 199 * FLASH organization 200 */ 201 202/* use CFI flash driver */ 203#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 204#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 205#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 206#define CONFIG_SYS_FLASH_EMPTY_INFO 207#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 208#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 209#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 210 211#define CONFIG_ENV_IS_IN_FLASH 1 212#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 213#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 214 215/* Address and size of Redundant Environment Sector */ 216#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 217#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 218 219#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 220 221#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 222 223/*----------------------------------------------------------------------- 224 * Dynamic MTD partition support 225 */ 226#define CONFIG_CMD_MTDPARTS 227#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 228#define CONFIG_FLASH_CFI_MTD 229#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 230 231#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 232 "128k(dtb)," \ 233 "1664k(kernel)," \ 234 "2m(rootfs)," \ 235 "4m(data)" 236 237/*----------------------------------------------------------------------- 238 * Hardware Information Block 239 */ 240#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 241#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 242#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 243 244/*----------------------------------------------------------------------- 245 * Cache Configuration 246 */ 247#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 248#if defined(CONFIG_CMD_KGDB) 249#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 250#endif 251 252/*----------------------------------------------------------------------- 253 * SYPCR - System Protection Control 11-9 254 * SYPCR can only be written once after reset! 255 *----------------------------------------------------------------------- 256 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 257 */ 258#if defined(CONFIG_WATCHDOG) 259#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 260 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 261#else 262#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 263#endif 264 265/*----------------------------------------------------------------------- 266 * SIUMCR - SIU Module Configuration 11-6 267 *----------------------------------------------------------------------- 268 * PCMCIA config., multi-function pin tri-state 269 */ 270#ifndef CONFIG_CAN_DRIVER 271#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 272#else /* we must activate GPL5 in the SIUMCR for CAN */ 273#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 274#endif /* CONFIG_CAN_DRIVER */ 275 276/*----------------------------------------------------------------------- 277 * TBSCR - Time Base Status and Control 11-26 278 *----------------------------------------------------------------------- 279 * Clear Reference Interrupt Status, Timebase freezing enabled 280 */ 281#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 282 283/*----------------------------------------------------------------------- 284 * RTCSC - Real-Time Clock Status and Control Register 11-27 285 *----------------------------------------------------------------------- 286 */ 287#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 288 289/*----------------------------------------------------------------------- 290 * PISCR - Periodic Interrupt Status and Control 11-31 291 *----------------------------------------------------------------------- 292 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 293 */ 294#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 295 296/*----------------------------------------------------------------------- 297 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 298 *----------------------------------------------------------------------- 299 * Reset PLL lock status sticky bit, timer expired status bit and timer 300 * interrupt status bit 301 */ 302#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 303 304/*----------------------------------------------------------------------- 305 * SCCR - System Clock and reset Control Register 15-27 306 *----------------------------------------------------------------------- 307 * Set clock output, timebase and RTC source and divider, 308 * power management and some other internal clocks 309 */ 310#define SCCR_MASK SCCR_EBDF11 311#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 312 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 313 SCCR_DFALCD00) 314 315/*----------------------------------------------------------------------- 316 * PCMCIA stuff 317 *----------------------------------------------------------------------- 318 * 319 */ 320#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 321#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 322#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 323#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 324#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 325#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 326#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 327#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 328 329/*----------------------------------------------------------------------- 330 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 331 *----------------------------------------------------------------------- 332 */ 333 334#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 335 336#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 337#undef CONFIG_IDE_LED /* LED for ide not supported */ 338#undef CONFIG_IDE_RESET /* reset for ide not supported */ 339 340#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 341#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 342 343#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 344 345#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 346 347/* Offset for data I/O */ 348#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 349 350/* Offset for normal register accesses */ 351#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 352 353/* Offset for alternate registers */ 354#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 355 356/*----------------------------------------------------------------------- 357 * 358 *----------------------------------------------------------------------- 359 * 360 */ 361#define CONFIG_SYS_DER 0 362 363/* 364 * Init Memory Controller: 365 * 366 * BR0/1 and OR0/1 (FLASH) 367 */ 368 369#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 370#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ 371 372/* used to re-map FLASH both when starting from SRAM or FLASH: 373 * restrict access enough to keep SRAM working (if any) 374 * but not too much to meddle with FLASH accesses 375 */ 376#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 377#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 378 379/* 380 * FLASH timing: 381 */ 382#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 383 OR_SCY_3_CLK | OR_EHTR | OR_BI) 384 385#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 386#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 387#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 388 389#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 390#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 391#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 392 393/* 394 * BR2/3 and OR2/3 (SDRAM) 395 * 396 */ 397#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 398#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 399#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 400 401/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 402#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 403 404#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 405#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 406 407#ifndef CONFIG_CAN_DRIVER 408#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 409#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 410#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 411#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 412#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 413#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 414#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 415 BR_PS_8 | BR_MS_UPMB | BR_V ) 416#endif /* CONFIG_CAN_DRIVER */ 417 418/* 419 * Memory Periodic Timer Prescaler 420 * 421 * The Divider for PTA (refresh timer) configuration is based on an 422 * example SDRAM configuration (64 MBit, one bank). The adjustment to 423 * the number of chip selects (NCS) and the actually needed refresh 424 * rate is done by setting MPTPR. 425 * 426 * PTA is calculated from 427 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 428 * 429 * gclk CPU clock (not bus clock!) 430 * Trefresh Refresh cycle * 4 (four word bursts used) 431 * 432 * 4096 Rows from SDRAM example configuration 433 * 1000 factor s -> ms 434 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 435 * 4 Number of refresh cycles per period 436 * 64 Refresh cycle in ms per number of rows 437 * -------------------------------------------- 438 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 439 * 440 * 50 MHz => 50.000.000 / Divider = 98 441 * 66 Mhz => 66.000.000 / Divider = 129 442 * 80 Mhz => 80.000.000 / Divider = 156 443 * 100 Mhz => 100.000.000 / Divider = 195 444 */ 445 446#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 447#define CONFIG_SYS_MAMR_PTA 98 448 449/* 450 * For 16 MBit, refresh rates could be 31.3 us 451 * (= 64 ms / 2K = 125 / quad bursts). 452 * For a simpler initialization, 15.6 us is used instead. 453 * 454 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 455 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 456 */ 457#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 458#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 459 460/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 461#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 462#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 463 464/* 465 * MAMR settings for SDRAM 466 */ 467 468/* 8 column SDRAM */ 469#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 470 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 471 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 472/* 9 column SDRAM */ 473#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 474 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 476 477 478/* 479 * Internal Definitions 480 * 481 * Boot Flags 482 */ 483#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 484#define BOOTFLAG_WARM 0x02 /* Software reboot */ 485 486#define CONFIG_NET_MULTI 487#define CONFIG_SCC1_ENET 488#define CONFIG_FEC_ENET 489#define CONFIG_ETHPRIME "SCC ETHERNET" 490 491/* pass open firmware flat tree */ 492#define CONFIG_OF_LIBFDT 1 493#define CONFIG_OF_BOARD_SETUP 1 494#define CONFIG_HWCONFIG 1 495 496#endif /* __CONFIG_H */ 497