1/* 2 * Copyright (C) 2007 Atmel Corporation 3 * 4 * Configuration settings for the ATSTK1003 CPU daughterboard 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27#include <asm/arch/memory-map.h> 28 29#define CONFIG_AVR32 1 30#define CONFIG_AT32AP 1 31#define CONFIG_AT32AP7002 1 32#define CONFIG_ATSTK1004 1 33#define CONFIG_ATSTK1000 1 34 35#define CONFIG_ATSTK1000_EXT_FLASH 1 36 37/* 38 * Timer clock frequency. We're using the CPU-internal COUNT register 39 * for this, so this is equivalent to the CPU core clock frequency 40 */ 41#define CONFIG_SYS_HZ 1000 42 43/* 44 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL 45 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the 46 * PLL frequency. 47 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz 48 */ 49#define CONFIG_PLL 1 50#define CONFIG_SYS_POWER_MANAGER 1 51#define CONFIG_SYS_OSC0_HZ 20000000 52#define CONFIG_SYS_PLL0_DIV 1 53#define CONFIG_SYS_PLL0_MUL 7 54#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 55/* 56 * Set the CPU running at: 57 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz 58 */ 59#define CONFIG_SYS_CLKDIV_CPU 0 60/* 61 * Set the HSB running at: 62 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz 63 */ 64#define CONFIG_SYS_CLKDIV_HSB 1 65/* 66 * Set the PBA running at: 67 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz 68 */ 69#define CONFIG_SYS_CLKDIV_PBA 2 70/* 71 * Set the PBB running at: 72 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz 73 */ 74#define CONFIG_SYS_CLKDIV_PBB 1 75 76/* 77 * The PLLOPT register controls the PLL like this: 78 * icp = PLLOPT<2> 79 * ivco = PLLOPT<1:0> 80 * 81 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). 82 */ 83#define CONFIG_SYS_PLL0_OPT 0x04 84 85#undef CONFIG_USART0 86#define CONFIG_USART1 1 87#undef CONFIG_USART2 88#undef CONFIG_USART3 89 90/* User serviceable stuff */ 91#define CONFIG_DOS_PARTITION 1 92 93#define CONFIG_CMDLINE_TAG 1 94#define CONFIG_SETUP_MEMORY_TAGS 1 95#define CONFIG_INITRD_TAG 1 96 97#define CONFIG_STACKSIZE (2048) 98 99#define CONFIG_BAUDRATE 115200 100#define CONFIG_BOOTARGS \ 101 "console=ttyS0 root=/dev/mmcblk0p1 rootwait" 102 103#define CONFIG_BOOTCOMMAND \ 104 "mmcinit; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm" 105 106/* 107 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage 108 * data on the serial line may interrupt the boot sequence. 109 */ 110#define CONFIG_BOOTDELAY 1 111#define CONFIG_AUTOBOOT 1 112#define CONFIG_AUTOBOOT_KEYED 1 113#define CONFIG_AUTOBOOT_PROMPT \ 114 "Press SPACE to abort autoboot in %d seconds\n", bootdelay 115#define CONFIG_AUTOBOOT_DELAY_STR "d" 116#define CONFIG_AUTOBOOT_STOP_STR " " 117 118/* 119 * Command line configuration. 120 */ 121#include <config_cmd_default.h> 122 123#define CONFIG_CMD_ASKENV 124#define CONFIG_CMD_EXT2 125#define CONFIG_CMD_FAT 126#define CONFIG_CMD_JFFS2 127#define CONFIG_CMD_MMC 128 129#undef CONFIG_CMD_FPGA 130#undef CONFIG_CMD_NET 131#undef CONFIG_CMD_NFS 132#undef CONFIG_CMD_SETGETDCR 133#undef CONFIG_CMD_XIMG 134 135#define CONFIG_ATMEL_USART 1 136#define CONFIG_PORTMUX_PIO 1 137#define CONFIG_SYS_HSDRAMC 1 138#define CONFIG_MMC 1 139#define CONFIG_ATMEL_MCI 1 140 141#define CONFIG_SYS_DCACHE_LINESZ 32 142#define CONFIG_SYS_ICACHE_LINESZ 32 143 144#define CONFIG_NR_DRAM_BANKS 1 145 146/* External flash on STK1000 */ 147#if 0 148#define CONFIG_SYS_FLASH_CFI 1 149#define CONFIG_FLASH_CFI_DRIVER 1 150#endif 151 152#define CONFIG_SYS_FLASH_BASE 0x00000000 153#define CONFIG_SYS_FLASH_SIZE 0x800000 154#define CONFIG_SYS_MAX_FLASH_BANKS 1 155#define CONFIG_SYS_MAX_FLASH_SECT 135 156 157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 158 159#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE 160#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE 161#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE 162 163#define CONFIG_ENV_IS_IN_FLASH 1 164#define CONFIG_ENV_SIZE 65536 165#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) 166 167#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) 168 169#define CONFIG_SYS_MALLOC_LEN (256*1024) 170 171/* Allow 2MB for the kernel run-time image */ 172#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000) 173#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) 174 175/* Other configuration settings that shouldn't have to change all that often */ 176#define CONFIG_SYS_PROMPT "U-Boot> " 177#define CONFIG_SYS_CBSIZE 256 178#define CONFIG_SYS_MAXARGS 16 179#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 180#define CONFIG_SYS_LONGHELP 1 181 182#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE 183#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) 184#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } 185 186#endif /* __CONFIG_H */ 187