1/* 2 * (C) Copyright 2000 3 * Murray Jensen <Murray.Jensen@cmst.csiro.au> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * Config header file for Cogent platform using an MPC8xx CPU module 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC860 1 /* This is an MPC860 CPU */ 37#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ 38 39#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ 40#define CONFIG_MISC_INIT_R /* Use misc_init_r() */ 41 42/* Cogent Modular Architecture options */ 43#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */ 44#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */ 45#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */ 46 47/* serial console configuration */ 48#undef CONFIG_8xx_CONS_SMC1 49#undef CONFIG_8xx_CONS_SMC2 50#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */ 51 52#if defined(CONFIG_CMA286_60_OLD) 53#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */ 54#endif 55 56#define CONFIG_BAUDRATE 230400 57 58#define CONFIG_HARD_I2C /* I2C with hardware support */ 59#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 60#define CONFIG_SYS_I2C_SLAVE 0x7F 61 62 63/* 64 * BOOTP options 65 */ 66#define CONFIG_BOOTP_BOOTFILESIZE 67#define CONFIG_BOOTP_BOOTPATH 68#define CONFIG_BOOTP_GATEWAY 69#define CONFIG_BOOTP_HOSTNAME 70 71 72/* 73 * Command line configuration. 74 */ 75#include <config_cmd_default.h> 76 77#define CONFIG_CMD_KGDB 78#define CONFIG_CMD_I2C 79 80#undef CONFIG_CMD_NET 81 82 83#if 0 84#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 85#else 86#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 87#endif 88#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ 89 90#define CONFIG_BOOTARGS "root=/dev/ram rw" 91 92#if defined(CONFIG_CMD_KGDB) 93#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ 94#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ 95#define CONFIG_KGDB_NONE /* define if kgdb on something else */ 96#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */ 97#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 98#endif 99 100#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ 101 102/* 103 * Miscellaneous configurable options 104 */ 105#define CONFIG_SYS_LONGHELP /* undef to save memory */ 106#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 107#if defined(CONFIG_CMD_KGDB) 108#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 109#else 110#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 111#endif 112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 115 116#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 117#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ 118 119#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 120 121#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 122 123#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 124 125#define CONFIG_SYS_ALLOC_DPRAM 126 127/* 128 * Low Level Configuration Settings 129 * (address mappings, register initial values, etc.) 130 * You should know what you are doing if you make changes here. 131 */ 132 133/*----------------------------------------------------------------------- 134 * Low Level Cogent settings 135 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not. 136 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be 137 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B 138 * (second 2 for CMA120 only) 139 */ 140#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */ 141 142#include <configs/cogent_common.h> 143 144#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ 145#define CONFIG_CONS_INDEX 1 146#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ 147#define CONFIG_SHOW_ACTIVITY 148#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) 149/* 150 * flash exists on the motherboard 151 * set these four according to TOP dipsw: 152 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) 153 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) 154 */ 155#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE 156#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE 157#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE 158#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE 159#endif 160#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE 161#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE 162 163/*----------------------------------------------------------------------- 164 * Internal Memory Mapped Register 165 */ 166#define CONFIG_SYS_IMMR 0xFF000000 167 168/*----------------------------------------------------------------------- 169 * Definitions for initial stack pointer and data area (in DPRAM) 170 */ 171#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 172#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 173#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 174#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 177/*----------------------------------------------------------------------- 178 * Start addresses for the final memory configuration 179 * (Set up by the startup code) 180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 181 */ 182#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE 183#ifdef CONFIG_CMA302 184#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ 185#else 186#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ 187#endif 188#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 189#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ 190#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 191 192/* 193 * For booting Linux, the board info and command line data 194 * have to be in the first 8 MB of memory, since this is 195 * the maximum mapped by the Linux kernel during initialization. 196 */ 197#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 198/*----------------------------------------------------------------------- 199 * FLASH organization 200 */ 201#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 202#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 203 204#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 205#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 206 207#define CONFIG_ENV_IS_IN_FLASH 1 208#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */ 209#ifdef CONFIG_CMA302 210#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 211#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ 212#else 213#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 214#endif 215/*----------------------------------------------------------------------- 216 * Cache Configuration 217 */ 218#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 219#if defined(CONFIG_CMD_KGDB) 220#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 221#endif 222 223 224/*----------------------------------------------------------------------- 225 * SYPCR - System Protection Control 11-9 226 * SYPCR can only be written once after reset! 227 *----------------------------------------------------------------------- 228 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 229 */ 230#if defined(CONFIG_WATCHDOG) 231#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 232 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 233#else 234#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 235#endif /* CONFIG_WATCHDOG */ 236 237/*----------------------------------------------------------------------- 238 * SIUMCR - SIU Module Configuration 11-6 239 *----------------------------------------------------------------------- 240 * PCMCIA config., multi-function pin tri-state 241 */ 242#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 243 244/*----------------------------------------------------------------------- 245 * TBSCR - Time Base Status and Control 11-26 246 *----------------------------------------------------------------------- 247 * Clear Reference Interrupt Status, Timebase freezing enabled 248 */ 249#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 250 251/*----------------------------------------------------------------------- 252 * PISCR - Periodic Interrupt Status and Control 11-31 253 *----------------------------------------------------------------------- 254 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 255 */ 256#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 257 258/*----------------------------------------------------------------------- 259 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 260 *----------------------------------------------------------------------- 261 * Reset PLL lock status sticky bit, timer expired status bit and timer 262 * interrupt status bit - leave PLL multiplication factor unchanged ! 263 */ 264#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 265 266/*----------------------------------------------------------------------- 267 * SCCR - System Clock and reset Control Register 15-27 268 *----------------------------------------------------------------------- 269 * Set clock output, timebase and RTC source and divider, 270 * power management and some other internal clocks 271 */ 272#define SCCR_MASK SCCR_EBDF11 273#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ 274 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 275 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 276 SCCR_DFALCD00) 277 278/*----------------------------------------------------------------------- 279 * PCMCIA stuff 280 *----------------------------------------------------------------------- 281 * 282 */ 283#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 284#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 285#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 286#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 287#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 288#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 289#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 290#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 291 292/*----------------------------------------------------------------------- 293 * 294 *----------------------------------------------------------------------- 295 * 296 */ 297/*#define CONFIG_SYS_DER 0x2002000F*/ 298#define CONFIG_SYS_DER 0 299 300#if defined(CONFIG_CMA286_60_OLD) 301 302/* 303 * Init Memory Controller: 304 * 305 * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings, 306 * they are actually the final settings for this cpu/board, because the 307 * flash and RAM are on the motherboard, accessed via the CMAbus, and the 308 * mappings are pretty much fixed. 309 * 310 * (the *_SIZE vars must be a power of 2) 311 */ 312 313#define CONFIG_SYS_CMA_CS0_BASE TEXT_BASE /* EPROM */ 314#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20) 315#define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */ 316#define CONFIG_SYS_CMA_CS1_SIZE (64 << 20) 317#define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */ 318#define CONFIG_SYS_CMA_CS2_SIZE (64 << 20) 319#define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */ 320#define CONFIG_SYS_CMA_CS3_SIZE (32 << 20) 321 322/* 323 * CS0 maps the EPROM on the cpu module 324 * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M 325 * 326 * Note: We must have already transferred control to the final location 327 * of the EPROM before these are used, because when BR0/OR0 are set, the 328 * mirror of the eprom at any other addresses will disappear. 329 */ 330 331/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */ 332#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V) 333/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */ 334#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK) 335 336/* 337 * CS1 maps motherboard DRAM and motherboard I/O slot 1 338 * (each 32Mbyte in size) 339 */ 340 341/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */ 342#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V) 343/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */ 344#define CONFIG_SYS_OR1_PRELIM ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA) 345 346/* 347 * CS2 maps motherboard I/O slots 2 and 3 348 * (each 32Mbyte in size) 349 */ 350 351/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */ 352#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V) 353/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */ 354#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA) 355 356/* 357 * CS3 maps motherboard I/O 358 * (32Mbyte in size) 359 */ 360 361/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */ 362#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V) 363/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */ 364#define CONFIG_SYS_OR3_PRELIM ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA) 365 366#endif 367 368/* 369 * Internal Definitions 370 * 371 * Boot Flags 372 */ 373#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 374#define BOOTFLAG_WARM 0x02 /* Software reboot */ 375 376#endif /* __CONFIG_H */ 377