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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37
38
39
40#ifdef CONFIG_MK_caddy2
41#define VME_CADDY2
42#endif
43
44
45
46
47#define CONFIG_E300 1
48#define CONFIG_MPC83xx 1
49#define CONFIG_MPC834x 1
50#define CONFIG_MPC8349 1
51#define CONFIG_VME8349 1
52
53#define CONFIG_MISC_INIT_R
54
55#define CONFIG_PCI
56
57#undef CONFIG_MPC83XX_PCI2
58
59#define PCI_66M
60#ifdef PCI_66M
61#define CONFIG_83XX_CLKIN 66000000
62#else
63#define CONFIG_83XX_CLKIN 33000000
64#endif
65
66#ifndef CONFIG_SYS_CLK_FREQ
67#ifdef PCI_66M
68#define CONFIG_SYS_CLK_FREQ 66000000
69#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
70#else
71#define CONFIG_SYS_CLK_FREQ 33000000
72#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
73#endif
74#endif
75
76#define CONFIG_SYS_IMMR 0xE0000000
77
78#undef CONFIG_SYS_DRAM_TEST
79#define CONFIG_SYS_MEMTEST_START 0x00000000
80#define CONFIG_SYS_MEMTEST_END 0x00100000
81
82
83
84
85#define CONFIG_DDR_ECC
86#define CONFIG_DDR_ECC_CMD
87#define CONFIG_SPD_EEPROM
88#define SPD_EEPROM_ADDRESS 0x54
89#define CONFIG_SYS_READ_SPD vme8349_read_spd
90#define CONFIG_SYS_83XX_DDR_USES_CS0
91
92
93
94
95
96
97
98
99
100
101
102#undef CONFIG_DDR_32BIT
103
104#define CONFIG_SYS_DDR_BASE 0x00000000
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
106#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
107#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
108 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
109#define CONFIG_DDR_2T_TIMING
110#define CONFIG_SYS_DDRCDR 0x80080001
111
112
113
114
115#define CONFIG_SYS_FLASH_CFI
116#define CONFIG_FLASH_CFI_DRIVER
117#ifdef VME_CADDY2
118#define CONFIG_SYS_FLASH_BASE 0xffc00000
119#define CONFIG_SYS_FLASH_SIZE 4
120#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
121 (2 << BR_PS_SHIFT) | \
122 BR_V)
123
124#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7
125#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
126#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015
127#else
128#define CONFIG_SYS_FLASH_BASE 0xf8000000
129#define CONFIG_SYS_FLASH_SIZE 128
130#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
131 (2 << BR_PS_SHIFT) | \
132 BR_V)
133
134#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7
135#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
136#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a
137#endif
138
139
140#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
141#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
142#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
143#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
144
145#define CONFIG_SYS_MAX_FLASH_BANKS 1
146#define CONFIG_SYS_MAX_FLASH_SECT 1024
147
148#undef CONFIG_SYS_FLASH_CHECKSUM
149#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
150#define CONFIG_SYS_FLASH_WRITE_TOUT 500
151
152#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
153
154#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
155#define CONFIG_SYS_RAMBOOT
156#else
157#undef CONFIG_SYS_RAMBOOT
158#endif
159
160#define CONFIG_SYS_INIT_RAM_LOCK 1
161#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000
162#define CONFIG_SYS_INIT_RAM_END 0x1000
163
164#define CONFIG_SYS_GBL_DATA_SIZE 0x100
165#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
166 CONFIG_SYS_GBL_DATA_SIZE)
167#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
168
169#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
170#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
171
172
173
174
175
176
177
178#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
179#define CONFIG_SYS_LBC_LBCR 0x00000000
180
181#undef CONFIG_SYS_LB_SDRAM
182
183
184
185
186#define CONFIG_CONS_INDEX 1
187#undef CONFIG_SERIAL_SOFTWARE_FIFO
188#define CONFIG_SYS_NS16550
189#define CONFIG_SYS_NS16550_SERIAL
190#define CONFIG_SYS_NS16550_REG_SIZE 1
191#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
192
193#define CONFIG_SYS_BAUDRATE_TABLE \
194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
195
196#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
197#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
198
199#define CONFIG_CMDLINE_EDITING
200#define CONFIG_AUTO_COMPLETE
201
202#define CONFIG_SYS_HUSH_PARSER
203#ifdef CONFIG_SYS_HUSH_PARSER
204#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
205#endif
206
207
208#define CONFIG_OF_LIBFDT
209#define CONFIG_OF_BOARD_SETUP
210#define CONFIG_OF_STDOUT_VIA_ALIAS
211
212
213#define CONFIG_I2C_MULTI_BUS
214#define CONFIG_HARD_I2C
215#undef CONFIG_SOFT_I2C
216#define CONFIG_FSL_I2C
217#define CONFIG_I2C_CMD_TREE
218#define CONFIG_SYS_I2C_SPEED 400000
219#define CONFIG_SYS_I2C_SLAVE 0x7F
220#define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}}
221#define CONFIG_SYS_I2C1_OFFSET 0x3000
222#define CONFIG_SYS_I2C2_OFFSET 0x3100
223#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
224
225
226#define CONFIG_SYS_I2C_8574_ADDR2 0x20
227
228
229#define CONFIG_SYS_TSEC1_OFFSET 0x24000
230#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
231#define CONFIG_SYS_TSEC2_OFFSET 0x25000
232#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
233
234
235
236
237
238#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
239#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
240#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
241#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
242#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
243#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
244#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
245#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
246#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
247
248#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
249#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
250#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000
251#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
252#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
253#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000
254#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
255#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
256#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
257
258#if defined(CONFIG_PCI)
259
260#define PCI_64BIT
261#define PCI_ONE_PCI1
262#if defined(PCI_64BIT)
263#undef PCI_ALL_PCI1
264#undef PCI_TWO_PCI1
265#undef PCI_ONE_PCI1
266#endif
267
268#ifndef VME_CADDY2
269#define CONFIG_NET_MULTI
270#endif
271#define CONFIG_PCI_PNP
272
273#undef CONFIG_EEPRO100
274#undef CONFIG_TULIP
275
276#if !defined(CONFIG_PCI_PNP)
277 #define PCI_ENET0_IOADDR 0xFIXME
278 #define PCI_ENET0_MEMADDR 0xFIXME
279 #define PCI_IDSEL_NUMBER 0xFIXME
280#endif
281
282#define CONFIG_PCI_SCAN_SHOW
283#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
284
285#endif
286
287
288
289
290#ifdef VME_CADDY2
291#define CONFIG_E1000
292#else
293#define CONFIG_TSEC_ENET
294#endif
295
296#if defined(CONFIG_TSEC_ENET)
297#ifndef CONFIG_NET_MULTI
298#define CONFIG_NET_MULTI
299#endif
300
301#define CONFIG_GMII
302#define CONFIG_TSEC1
303#define CONFIG_TSEC1_NAME "TSEC0"
304#define CONFIG_TSEC2
305#define CONFIG_TSEC2_NAME "TSEC1"
306#define CONFIG_PHY_M88E1111
307#define TSEC1_PHY_ADDR 0x08
308#define TSEC2_PHY_ADDR 0x10
309#define TSEC1_PHYIDX 0
310#define TSEC2_PHYIDX 0
311#define TSEC1_FLAGS TSEC_GIGABIT
312#define TSEC2_FLAGS TSEC_GIGABIT
313
314
315#define CONFIG_ETHPRIME "TSEC0"
316
317#endif
318
319#if defined(CONFIG_E1000)
320#ifndef CONFIG_NET_MULTI
321#define CONFIG_NET_MULTI
322#endif
323#endif
324
325
326
327
328#ifndef CONFIG_SYS_RAMBOOT
329 #define CONFIG_ENV_IS_IN_FLASH
330 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
331 #define CONFIG_ENV_SECT_SIZE 0x20000
332 #define CONFIG_ENV_SIZE 0x2000
333
334
335#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
336#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
337
338#else
339 #define CONFIG_SYS_NO_FLASH
340 #define CONFIG_ENV_IS_NOWHERE
341 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
342 #define CONFIG_ENV_SIZE 0x2000
343#endif
344
345#define CONFIG_LOADS_ECHO
346#define CONFIG_SYS_LOADS_BAUD_CHANGE
347
348
349
350
351#define CONFIG_BOOTP_BOOTFILESIZE
352#define CONFIG_BOOTP_BOOTPATH
353#define CONFIG_BOOTP_GATEWAY
354#define CONFIG_BOOTP_HOSTNAME
355
356
357
358
359#include <config_cmd_default.h>
360
361#define CONFIG_CMD_I2C
362#define CONFIG_CMD_MII
363#define CONFIG_CMD_PING
364#define CONFIG_CMD_DATE
365#define CONFIG_SYS_RTC_BUS_NUM 0x01
366#define CONFIG_SYS_I2C_RTC_ADDR 0x32
367#define CONFIG_RTC_RX8025
368#define CONFIG_CMD_TSI148
369
370#if defined(CONFIG_PCI)
371 #define CONFIG_CMD_PCI
372#endif
373
374#if defined(CONFIG_SYS_RAMBOOT)
375 #undef CONFIG_CMD_ENV
376 #undef CONFIG_CMD_LOADS
377#endif
378
379#define CONFIG_CMD_ELF
380
381#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
382
383#undef CONFIG_WATCHDOG
384
385
386
387
388#define CONFIG_SYS_LONGHELP
389#define CONFIG_SYS_LOAD_ADDR 0x2000000
390#define CONFIG_SYS_PROMPT "=> "
391
392#if defined(CONFIG_CMD_KGDB)
393 #define CONFIG_SYS_CBSIZE 1024
394#else
395 #define CONFIG_SYS_CBSIZE 256
396#endif
397
398#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
399#define CONFIG_SYS_MAXARGS 16
400#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
401#define CONFIG_SYS_HZ 1000
402
403
404
405
406
407
408#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
409
410#define CONFIG_SYS_RCWH_PCIHOST 0x80000000
411
412#define CONFIG_SYS_HRCW_LOW (\
413 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
414 HRCWL_DDR_TO_SCB_CLK_1X1 |\
415 HRCWL_CSB_TO_CLKIN |\
416 HRCWL_VCO_1X2 |\
417 HRCWL_CORE_TO_CSB_2X1)
418
419#if defined(PCI_64BIT)
420#define CONFIG_SYS_HRCW_HIGH (\
421 HRCWH_PCI_HOST |\
422 HRCWH_64_BIT_PCI |\
423 HRCWH_PCI1_ARBITER_ENABLE |\
424 HRCWH_PCI2_ARBITER_DISABLE |\
425 HRCWH_CORE_ENABLE |\
426 HRCWH_FROM_0X00000100 |\
427 HRCWH_BOOTSEQ_DISABLE |\
428 HRCWH_SW_WATCHDOG_DISABLE |\
429 HRCWH_ROM_LOC_LOCAL_16BIT |\
430 HRCWH_TSEC1M_IN_GMII |\
431 HRCWH_TSEC2M_IN_GMII)
432#else
433#define CONFIG_SYS_HRCW_HIGH (\
434 HRCWH_PCI_HOST |\
435 HRCWH_32_BIT_PCI |\
436 HRCWH_PCI1_ARBITER_ENABLE |\
437 HRCWH_PCI2_ARBITER_ENABLE |\
438 HRCWH_CORE_ENABLE |\
439 HRCWH_FROM_0X00000100 |\
440 HRCWH_BOOTSEQ_DISABLE |\
441 HRCWH_SW_WATCHDOG_DISABLE |\
442 HRCWH_ROM_LOC_LOCAL_16BIT |\
443 HRCWH_TSEC1M_IN_GMII |\
444 HRCWH_TSEC2M_IN_GMII)
445#endif
446
447
448#define CONFIG_SYS_SICRH 0
449#define CONFIG_SYS_SICRL SICRL_LDP_A
450
451#define CONFIG_SYS_HID0_INIT 0x000000000
452#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
453 HID0_ENABLE_INSTRUCTION_CACHE)
454
455#define CONFIG_SYS_HID2 HID2_HBE
456
457#define CONFIG_SYS_GPIO1_PRELIM
458#define CONFIG_SYS_GPIO1_DIR 0x00100000
459#define CONFIG_SYS_GPIO1_DAT 0x00100000
460
461#define CONFIG_SYS_GPIO2_PRELIM
462#define CONFIG_SYS_GPIO2_DIR 0x78900000
463#define CONFIG_SYS_GPIO2_DAT 0x70100000
464
465#define CONFIG_HIGH_BATS
466
467
468#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
469 BATL_MEMCOHERENCE)
470#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
471 BATU_VS | BATU_VP)
472
473
474#ifdef CONFIG_PCI
475#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \
476 BATL_MEMCOHERENCE)
477#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
478 BATU_VS | BATU_VP)
479#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
480 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
481#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
482 BATU_VS | BATU_VP)
483#else
484#define CONFIG_SYS_IBAT1L (0)
485#define CONFIG_SYS_IBAT1U (0)
486#define CONFIG_SYS_IBAT2L (0)
487#define CONFIG_SYS_IBAT2U (0)
488#endif
489
490#ifdef CONFIG_MPC83XX_PCI2
491#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \
492 BATL_MEMCOHERENCE)
493#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
494 BATU_VS | BATU_VP)
495#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \
496 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
497#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
498 BATU_VS | BATU_VP)
499#else
500#define CONFIG_SYS_IBAT3L (0)
501#define CONFIG_SYS_IBAT3U (0)
502#define CONFIG_SYS_IBAT4L (0)
503#define CONFIG_SYS_IBAT4U (0)
504#endif
505
506
507#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \
508 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
509#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
510 BATU_VS | BATU_VP)
511
512#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
513#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
514
515#if (CONFIG_SYS_DDR_SIZE == 512)
516#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
517 BATL_PP_10 | BATL_MEMCOHERENCE)
518#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
519 BATU_BL_256M | BATU_VS | BATU_VP)
520#else
521#define CONFIG_SYS_IBAT7L (0)
522#define CONFIG_SYS_IBAT7U (0)
523#endif
524
525#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
526#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
527#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
528#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
529#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
530#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
531#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
532#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
533#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
534#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
535#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
536#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
537#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
538#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
539#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
540#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
541
542
543
544
545
546
547#define BOOTFLAG_COLD 0x01
548#define BOOTFLAG_WARM 0x02
549
550#if defined(CONFIG_CMD_KGDB)
551#define CONFIG_KGDB_BAUDRATE 230400
552#define CONFIG_KGDB_SER_INDEX 2
553#endif
554
555
556
557
558#define CONFIG_ENV_OVERWRITE
559
560#if defined(CONFIG_TSEC_ENET)
561#define CONFIG_HAS_ETH0
562#define CONFIG_HAS_ETH1
563#endif
564
565#define CONFIG_HOSTNAME VME8349
566#define CONFIG_ROOTPATH /tftpboot/rootfs
567#define CONFIG_BOOTFILE uImage
568
569#define CONFIG_LOADADDR 800000
570
571#define CONFIG_BOOTDELAY 6
572#undef CONFIG_BOOTARGS
573
574#define CONFIG_BAUDRATE 9600
575
576#define CONFIG_EXTRA_ENV_SETTINGS \
577 "netdev=eth0\0" \
578 "hostname=vme8349\0" \
579 "nfsargs=setenv bootargs root=/dev/nfs rw " \
580 "nfsroot=${serverip}:${rootpath}\0" \
581 "ramargs=setenv bootargs root=/dev/ram rw\0" \
582 "addip=setenv bootargs ${bootargs} " \
583 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
584 ":${hostname}:${netdev}:off panic=1\0" \
585 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
586 "flash_nfs=run nfsargs addip addtty;" \
587 "bootm ${kernel_addr}\0" \
588 "flash_self=run ramargs addip addtty;" \
589 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
590 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
591 "bootm\0" \
592 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
593 "update=protect off fff00000 fff3ffff; " \
594 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
595 "upd=run load update\0" \
596 "fdtaddr=780000\0" \
597 "fdtfile=vme8349.dtb\0" \
598 ""
599
600#define CONFIG_NFSBOOTCOMMAND \
601 "setenv bootargs root=/dev/nfs rw " \
602 "nfsroot=$serverip:$rootpath " \
603 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
604 "console=$consoledev,$baudrate $othbootargs;" \
605 "tftp $loadaddr $bootfile;" \
606 "tftp $fdtaddr $fdtfile;" \
607 "bootm $loadaddr - $fdtaddr"
608
609#define CONFIG_RAMBOOTCOMMAND \
610 "setenv bootargs root=/dev/ram rw " \
611 "console=$consoledev,$baudrate $othbootargs;" \
612 "tftp $ramdiskaddr $ramdiskfile;" \
613 "tftp $loadaddr $bootfile;" \
614 "tftp $fdtaddr $fdtfile;" \
615 "bootm $loadaddr $ramdiskaddr $fdtaddr"
616
617#define CONFIG_BOOTCOMMAND "run flash_self"
618
619#ifndef __ASSEMBLY__
620int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
621 unsigned char *buffer, int len);
622#endif
623
624#endif
625